tree bb660611a7d73b99346f6ecd2ecabbafc975cd45
parent 27796989ac55983e95bc0538310fd5ee2eefba59
author Fea.Wang <fea.wang@sifive.com> 1717682093 +0800
committer Alistair Francis <alistair.francis@wdc.com> 1719406669 +1000

target/riscv: Reserve exception codes for sw-check and hw-err

Based on the priv-1.13.0, add the exception codes for Software-check and
Hardware-error.

Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240606135454.119186-6-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>