axis_dev88: convert to memory API
Signed-off-by: Avi Kivity <avi@redhat.com>
diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c
index 73eb39d..c5405ce 100644
--- a/hw/axis_dev88.c
+++ b/hw/axis_dev88.c
@@ -39,6 +39,7 @@
struct nand_state_t
{
DeviceState *nand;
+ MemoryRegion iomem;
unsigned int rdy:1;
unsigned int ale:1;
unsigned int cle:1;
@@ -46,7 +47,7 @@
};
static struct nand_state_t nand_state;
-static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t nand_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
struct nand_state_t *s = opaque;
uint32_t r;
@@ -61,31 +62,25 @@
}
static void
-nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
+nand_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+ unsigned size)
{
struct nand_state_t *s = opaque;
int rdy;
- DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
+ DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
nand_setio(s->nand, value);
nand_getpins(s->nand, &rdy);
s->rdy = rdy;
}
-static CPUReadMemoryFunc * const nand_read[] = {
- &nand_readl,
- &nand_readl,
- &nand_readl,
+static const MemoryRegionOps nand_ops = {
+ .read = nand_read,
+ .write = nand_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const nand_write[] = {
- &nand_writel,
- &nand_writel,
- &nand_writel,
-};
-
-
struct tempsensor_t
{
unsigned int shiftreg;
@@ -165,12 +160,13 @@
static struct gpio_state_t
{
+ MemoryRegion iomem;
struct nand_state_t *nand;
struct tempsensor_t tempsensor;
uint32_t regs[0x5c / 4];
} gpio_state;
-static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t gpio_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
struct gpio_state_t *s = opaque;
uint32_t r = 0;
@@ -199,10 +195,11 @@
D(printf("%s %x=%x\n", __func__, addr, r));
}
-static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void gpio_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+ unsigned size)
{
struct gpio_state_t *s = opaque;
- D(printf("%s %x=%x\n", __func__, addr, value));
+ D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));
addr >>= 2;
switch (addr)
@@ -230,14 +227,14 @@
}
}
-static CPUReadMemoryFunc * const gpio_read[] = {
- NULL, NULL,
- &gpio_readl,
-};
-
-static CPUWriteMemoryFunc * const gpio_write[] = {
- NULL, NULL,
- &gpio_writel,
+static const MemoryRegionOps gpio_ops = {
+ .read = gpio_read,
+ .write = gpio_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
#define INTMEM_SIZE (128 * 1024)
@@ -258,8 +255,6 @@
void *etraxfs_dmac;
struct etraxfs_dma_client *dma_eth;
int i;
- int nand_regs;
- int gpio_regs;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
@@ -283,14 +278,16 @@
nand = drive_get(IF_MTD, 0, 0);
nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
NAND_MFR_STMICRO, 0x39);
- nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);
+ memory_region_init_io(&nand_state.iomem, &nand_ops, &nand_state,
+ "nand", 0x05000000);
+ memory_region_add_subregion(address_space_mem, 0x10000000,
+ &nand_state.iomem);
gpio_state.nand = &nand_state;
- gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);
+ memory_region_init_io(&gpio_state.iomem, &gpio_ops, &gpio_state,
+ "gpio", 0x5c);
+ memory_region_add_subregion(address_space_mem, 0x3001a000,
+ &gpio_state.iomem);
cpu_irq = cris_pic_init_cpu(env);
