Introduce reset notifier order
Add the parameter 'order' to qemu_register_reset and sort callbacks on
registration. On system reset, callbacks with lower order will be
invoked before those with higher order. Update all existing users to the
standard order 0.
Note: At least for x86, the existing users seem to assume that handlers
are called in their registration order. Therefore, the patch preserves
this property. If someone feels bored, (s)he could try to identify this
dependency and express it properly on callback registration.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
diff --git a/hw/ac97.c b/hw/ac97.c
index 0ff2941..288f428 100644
--- a/hw/ac97.c
+++ b/hw/ac97.c
@@ -1369,7 +1369,7 @@
pci_register_io_region (&d->dev, 0, 256 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);
pci_register_io_region (&d->dev, 1, 64 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);
register_savevm ("ac97", 0, 2, ac97_save, ac97_load, s);
- qemu_register_reset (ac97_on_reset, s);
+ qemu_register_reset (ac97_on_reset, 0, s);
AUD_register_card ("ac97", &s->card);
ac97_on_reset (s);
return 0;
diff --git a/hw/acpi.c b/hw/acpi.c
index dbaf18a..0bbb2d8 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -550,7 +550,7 @@
s->smbus = i2c_init_bus();
s->irq = sci_irq;
- qemu_register_reset(piix4_reset, s);
+ qemu_register_reset(piix4_reset, 0, s);
return s->smbus;
}
diff --git a/hw/adb.c b/hw/adb.c
index c57aeaa..cceb098 100644
--- a/hw/adb.c
+++ b/hw/adb.c
@@ -122,7 +122,7 @@
d->devreq = devreq;
d->devreset = devreset;
d->opaque = opaque;
- qemu_register_reset((QEMUResetHandler *)devreset, d);
+ qemu_register_reset((QEMUResetHandler *)devreset, 0, d);
d->devreset(d);
return d;
}
diff --git a/hw/apic.c b/hw/apic.c
index d63d74b..8c8b2de 100644
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -924,7 +924,7 @@
s->timer = qemu_new_timer(vm_clock, apic_timer, s);
register_savevm("apic", s->id, 2, apic_save, apic_load, s);
- qemu_register_reset(apic_reset, s);
+ qemu_register_reset(apic_reset, 0, s);
local_apics[s->id] = s;
return 0;
diff --git a/hw/arm_boot.c b/hw/arm_boot.c
index 35f0130..acfa67e 100644
--- a/hw/arm_boot.c
+++ b/hw/arm_boot.c
@@ -203,7 +203,7 @@
if (info->nb_cpus == 0)
info->nb_cpus = 1;
env->boot_info = info;
- qemu_register_reset(main_cpu_reset, env);
+ qemu_register_reset(main_cpu_reset, 0, env);
}
/* Assume that raw images are linux kernels, and ELF images are not. */
diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c
index 506ef28..60b719b 100644
--- a/hw/axis_dev88.c
+++ b/hw/axis_dev88.c
@@ -271,7 +271,7 @@
cpu_model = "crisv32";
}
env = cpu_init(cpu_model);
- qemu_register_reset(main_cpu_reset, env);
+ qemu_register_reset(main_cpu_reset, 0, env);
/* allocate RAM */
phys_ram = qemu_ram_alloc(ram_size);
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 48f8960..f0bb8d9 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -3228,7 +3228,7 @@
s->vga.cursor_invalidate = cirrus_cursor_invalidate;
s->vga.cursor_draw_line = cirrus_cursor_draw_line;
- qemu_register_reset(cirrus_reset, s);
+ qemu_register_reset(cirrus_reset, 0, s);
cirrus_reset(s);
register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
}
diff --git a/hw/cs4231.c b/hw/cs4231.c
index 2266980..a5ba221 100644
--- a/hw/cs4231.c
+++ b/hw/cs4231.c
@@ -175,6 +175,6 @@
cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);
cpu_register_physical_memory(base, CS_SIZE, cs_io_memory);
register_savevm("cs4231", base, 1, cs_save, cs_load, s);
- qemu_register_reset(cs_reset, s);
+ qemu_register_reset(cs_reset, 0, s);
cs_reset(s);
}
diff --git a/hw/cs4231a.c b/hw/cs4231a.c
index 33c9460..d08d7c3 100644
--- a/hw/cs4231a.c
+++ b/hw/cs4231a.c
@@ -656,7 +656,7 @@
DMA_register_channel (s->dma, cs_dma_read, s);
register_savevm ("cs4231a", 0, 1, cs_save, cs_load, s);
- qemu_register_reset (cs_reset, s);
+ qemu_register_reset (cs_reset, 0, s);
cs_reset (s);
AUD_register_card ("cs4231a", &s->card);
diff --git a/hw/cuda.c b/hw/cuda.c
index 145aa9c..828ccf7 100644
--- a/hw/cuda.c
+++ b/hw/cuda.c
@@ -762,6 +762,6 @@
s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
*cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
register_savevm("cuda", -1, 1, cuda_save, cuda_load, s);
- qemu_register_reset(cuda_reset, s);
+ qemu_register_reset(cuda_reset, 0, s);
cuda_reset(s);
}
diff --git a/hw/dma.c b/hw/dma.c
index b95407b..c8ed6b0 100644
--- a/hw/dma.c
+++ b/hw/dma.c
@@ -493,7 +493,7 @@
register_ioport_read (base + ((i + 8) << dshift), 1, 1,
read_cont, d);
}
- qemu_register_reset(dma_reset, d);
+ qemu_register_reset(dma_reset, 0, d);
dma_reset(d);
for (i = 0; i < ARRAY_SIZE (d->regs); ++i) {
d->regs[i].transfer_handler = dma_phony_handler;
diff --git a/hw/dp8393x.c b/hw/dp8393x.c
index 4418409..5aa1211 100644
--- a/hw/dp8393x.c
+++ b/hw/dp8393x.c
@@ -892,7 +892,7 @@
nic_receive, nic_can_receive, nic_cleanup, s);
qemu_format_nic_info_str(s->vc, nd->macaddr);
- qemu_register_reset(nic_reset, s);
+ qemu_register_reset(nic_reset, 0, s);
nic_reset(s);
s->mmio_index = cpu_register_io_memory(0, dp8393x_read, dp8393x_write, s);
diff --git a/hw/eccmemctl.c b/hw/eccmemctl.c
index 07f5ef7..aa4218d 100644
--- a/hw/eccmemctl.c
+++ b/hw/eccmemctl.c
@@ -334,7 +334,7 @@
ecc_io_memory);
}
register_savevm("ECC", base, 3, ecc_save, ecc_load, s);
- qemu_register_reset(ecc_reset, s);
+ qemu_register_reset(ecc_reset, 0, s);
ecc_reset(s);
return s;
}
diff --git a/hw/eepro100.c b/hw/eepro100.c
index 1689a3a..fcb091c 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -1771,7 +1771,7 @@
qemu_format_nic_info_str(s->vc, s->macaddr);
- qemu_register_reset(nic_reset, s);
+ qemu_register_reset(nic_reset, 0, s);
register_savevm(s->vc->model, -1, 3, nic_save, nic_load, s);
}
diff --git a/hw/es1370.c b/hw/es1370.c
index 6589547..12f2ace 100644
--- a/hw/es1370.c
+++ b/hw/es1370.c
@@ -1055,7 +1055,7 @@
pci_register_io_region (&d->dev, 0, 256, PCI_ADDRESS_SPACE_IO, es1370_map);
register_savevm ("es1370", 0, 2, es1370_save, es1370_load, s);
- qemu_register_reset (es1370_on_reset, s);
+ qemu_register_reset (es1370_on_reset, 0, s);
AUD_register_card ("es1370", &s->card);
es1370_reset (s);
diff --git a/hw/escc.c b/hw/escc.c
index 53808e5..3d982b5 100644
--- a/hw/escc.c
+++ b/hw/escc.c
@@ -758,7 +758,7 @@
register_savevm("escc", base, 2, escc_save, escc_load, s);
else
register_savevm("escc", -1, 2, escc_save, escc_load, s);
- qemu_register_reset(escc_reset, s);
+ qemu_register_reset(escc_reset, 0, s);
escc_reset(s);
return escc_io_memory;
}
@@ -932,6 +932,6 @@
"QEMU Sun Mouse");
qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]);
register_savevm("slavio_serial_mouse", base, 2, escc_save, escc_load, s);
- qemu_register_reset(escc_reset, s);
+ qemu_register_reset(escc_reset, 0, s);
escc_reset(s);
}
diff --git a/hw/esp.c b/hw/esp.c
index 302e897..6ac8c35 100644
--- a/hw/esp.c
+++ b/hw/esp.c
@@ -682,7 +682,7 @@
esp_reset(s);
register_savevm("esp", -1, 3, esp_save, esp_load, s);
- qemu_register_reset(esp_reset, s);
+ qemu_register_reset(esp_reset, 0, s);
qdev_init_irq_sink(&dev->qdev, parent_esp_reset, 1);
diff --git a/hw/etraxfs.c b/hw/etraxfs.c
index f043c19..f82e1cd 100644
--- a/hw/etraxfs.c
+++ b/hw/etraxfs.c
@@ -64,7 +64,7 @@
cpu_model = "crisv32";
}
env = cpu_init(cpu_model);
- qemu_register_reset(main_cpu_reset, env);
+ qemu_register_reset(main_cpu_reset, 0, env);
/* allocate RAM */
phys_ram = qemu_ram_alloc(ram_size);
diff --git a/hw/etraxfs_timer.c b/hw/etraxfs_timer.c
index f1144ea..793c5eb 100644
--- a/hw/etraxfs_timer.c
+++ b/hw/etraxfs_timer.c
@@ -327,7 +327,7 @@
timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
sysbus_init_mmio(dev, 0x5c, timer_regs);
- qemu_register_reset(etraxfs_timer_reset, t);
+ qemu_register_reset(etraxfs_timer_reset, 0, t);
}
static void etraxfs_timer_register(void)
diff --git a/hw/fdc.c b/hw/fdc.c
index f4a4be0..4c6284c 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -1883,7 +1883,7 @@
}
fdctrl_external_reset(fdctrl);
register_savevm("fdc", io_base, 2, fdc_save, fdc_load, fdctrl);
- qemu_register_reset(fdctrl_external_reset, fdctrl);
+ qemu_register_reset(fdctrl_external_reset, 0, fdctrl);
for (i = 0; i < MAX_FD; i++) {
fd_revalidate(&fdctrl->drives[i]);
}
diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c
index e605cda..8ac0e9d 100644
--- a/hw/fw_cfg.c
+++ b/hw/fw_cfg.c
@@ -281,7 +281,7 @@
fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
register_savevm("fw_cfg", -1, 1, fw_cfg_save, fw_cfg_load, s);
- qemu_register_reset(fw_cfg_reset, s);
+ qemu_register_reset(fw_cfg_reset, 0, s);
fw_cfg_reset(s);
return s;
diff --git a/hw/g364fb.c b/hw/g364fb.c
index 54c201c..b9bb318 100644
--- a/hw/g364fb.c
+++ b/hw/g364fb.c
@@ -598,7 +598,7 @@
s->vram = qemu_get_ram_ptr(s->vram_offset);
s->irq = irq;
- qemu_register_reset(g364fb_reset, s);
+ qemu_register_reset(g364fb_reset, 0, s);
register_savevm("g364fb", 0, 1, g364fb_save, g364fb_load, s);
g364fb_reset(s);
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index e9769cd..8b170d6 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -176,7 +176,7 @@
d->config[0x27] = 0x85;
#endif
register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load, d);
- qemu_register_reset(pci_grackle_reset, d);
+ qemu_register_reset(pci_grackle_reset, 0, d);
pci_grackle_reset(d);
return s->bus;
diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c
index 9a67ec0..38ebe99 100644
--- a/hw/heathrow_pic.c
+++ b/hw/heathrow_pic.c
@@ -230,7 +230,7 @@
register_savevm("heathrow_pic", -1, 1, heathrow_pic_save,
heathrow_pic_load, s);
- qemu_register_reset(heathrow_pic_reset, s);
+ qemu_register_reset(heathrow_pic_reset, 0, s);
heathrow_pic_reset(s);
return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64);
}
diff --git a/hw/hpet.c b/hw/hpet.c
index c7945ec..29db325 100644
--- a/hw/hpet.c
+++ b/hw/hpet.c
@@ -580,7 +580,7 @@
}
hpet_reset(s);
register_savevm("hpet", -1, 1, hpet_save, hpet_load, s);
- qemu_register_reset(hpet_reset, s);
+ qemu_register_reset(hpet_reset, 0, s);
/* HPET Area */
iomemtype = cpu_register_io_memory(0, hpet_ram_read,
hpet_ram_write, s);
diff --git a/hw/hw.h b/hw/hw.h
index dd11f0a..a3f5717 100644
--- a/hw/hw.h
+++ b/hw/hw.h
@@ -258,7 +258,7 @@
typedef void QEMUResetHandler(void *opaque);
-void qemu_register_reset(QEMUResetHandler *func, void *opaque);
+void qemu_register_reset(QEMUResetHandler *func, int order, void *opaque);
/* handler to set the boot_device for a specific type of QEMUMachine */
/* return 0 if success */
diff --git a/hw/i8254.c b/hw/i8254.c
index 44e4531..acdd234 100644
--- a/hw/i8254.c
+++ b/hw/i8254.c
@@ -497,7 +497,7 @@
register_savevm("i8254", base, 1, pit_save, pit_load, pit);
- qemu_register_reset(pit_reset, pit);
+ qemu_register_reset(pit_reset, 0, pit);
register_ioport_write(base, 4, 1, pit_ioport_write, pit);
register_ioport_read(base, 3, 1, pit_ioport_read, pit);
diff --git a/hw/i8259.c b/hw/i8259.c
index adabd2b..40f8bee 100644
--- a/hw/i8259.c
+++ b/hw/i8259.c
@@ -508,7 +508,7 @@
register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
}
register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
- qemu_register_reset(pic_reset, s);
+ qemu_register_reset(pic_reset, 0, s);
}
void pic_info(Monitor *mon)
diff --git a/hw/ide.c b/hw/ide.c
index 2412b87..f8da7c9 100644
--- a/hw/ide.c
+++ b/hw/ide.c
@@ -3330,7 +3330,7 @@
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]);
register_savevm("ide", 0, 2, pci_ide_save, pci_ide_load, d);
- qemu_register_reset(cmd646_reset, d);
+ qemu_register_reset(cmd646_reset, 0, d);
cmd646_reset(d);
}
@@ -3373,7 +3373,7 @@
pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
- qemu_register_reset(piix3_reset, d);
+ qemu_register_reset(piix3_reset, 0, d);
piix3_reset(d);
pci_register_io_region((PCIDevice *)d, 4, 0x10,
@@ -3413,7 +3413,7 @@
pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
- qemu_register_reset(piix3_reset, d);
+ qemu_register_reset(piix3_reset, 0, d);
piix3_reset(d);
pci_register_io_region((PCIDevice *)d, 4, 0x10,
@@ -3754,7 +3754,7 @@
pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
pmac_ide_write, d);
register_savevm("ide", 0, 1, pmac_ide_save, pmac_ide_load, d);
- qemu_register_reset(pmac_ide_reset, d);
+ qemu_register_reset(pmac_ide_reset, 0, d);
pmac_ide_reset(d);
return pmac_ide_memory;
diff --git a/hw/ioapic.c b/hw/ioapic.c
index 317c2c2..83ac25e 100644
--- a/hw/ioapic.c
+++ b/hw/ioapic.c
@@ -255,7 +255,7 @@
cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
- qemu_register_reset(ioapic_reset, s);
+ qemu_register_reset(ioapic_reset, 0, s);
return s;
}
diff --git a/hw/iommu.c b/hw/iommu.c
index d52acd7..ae0c56d 100644
--- a/hw/iommu.c
+++ b/hw/iommu.c
@@ -380,7 +380,7 @@
cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
- qemu_register_reset(iommu_reset, s);
+ qemu_register_reset(iommu_reset, 0, s);
iommu_reset(s);
return s;
}
diff --git a/hw/lm832x.c b/hw/lm832x.c
index decde55..74eeca2 100644
--- a/hw/lm832x.c
+++ b/hw/lm832x.c
@@ -501,7 +501,7 @@
lm_kbd_reset(s);
- qemu_register_reset((void *) lm_kbd_reset, s);
+ qemu_register_reset((void *) lm_kbd_reset, 0, s);
register_savevm("LM8323", -1, 0, lm_kbd_save, lm_kbd_load, s);
}
diff --git a/hw/m48t59.c b/hw/m48t59.c
index c6829be..4804443 100644
--- a/hw/m48t59.c
+++ b/hw/m48t59.c
@@ -641,7 +641,7 @@
}
qemu_get_timedate(&s->alarm, 0);
- qemu_register_reset(m48t59_reset, s);
+ qemu_register_reset(m48t59_reset, 0, s);
save_base = mem_base ? mem_base : io_base;
register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s);
diff --git a/hw/mac_dbdma.c b/hw/mac_dbdma.c
index a94cd09..75a9f17 100644
--- a/hw/mac_dbdma.c
+++ b/hw/mac_dbdma.c
@@ -839,7 +839,7 @@
*dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, s);
register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s);
- qemu_register_reset(dbdma_reset, s);
+ qemu_register_reset(dbdma_reset, 0, s);
dbdma_reset(s);
dbdma_bh = qemu_bh_new(DBDMA_run_bh, s);
diff --git a/hw/mac_nvram.c b/hw/mac_nvram.c
index 36648d1..1a1ca0d 100644
--- a/hw/mac_nvram.c
+++ b/hw/mac_nvram.c
@@ -142,7 +142,7 @@
*mem_index = s->mem_index;
register_savevm("macio_nvram", -1, 1, macio_nvram_save, macio_nvram_load,
s);
- qemu_register_reset(macio_nvram_reset, s);
+ qemu_register_reset(macio_nvram_reset, 0, s);
macio_nvram_reset(s);
return s;
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index bf1621e..e496c28 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -146,7 +146,7 @@
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- qemu_register_reset(main_cpu_reset, env);
+ qemu_register_reset(main_cpu_reset, 0, env);
/* allocate RAM */
ram_offset = qemu_ram_alloc(ram_size);
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index d862182..e71ecc1 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -447,7 +447,7 @@
s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1);
malta_fpga_reset(s);
- qemu_register_reset(malta_fpga_reset, s);
+ qemu_register_reset(malta_fpga_reset, 0, s);
return s;
}
@@ -792,7 +792,7 @@
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- qemu_register_reset(main_cpu_reset, env);
+ qemu_register_reset(main_cpu_reset, 0, env);
/* allocate RAM */
if (ram_size > (256 << 20)) {
diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c
index e4414b4..1117db2 100644
--- a/hw/mips_mipssim.c
+++ b/hw/mips_mipssim.c
@@ -126,7 +126,7 @@
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- qemu_register_reset(main_cpu_reset, env);
+ qemu_register_reset(main_cpu_reset, 0, env);
/* Allocate RAM. */
ram_offset = qemu_ram_alloc(ram_size);
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index 6892060..ba8c7f6 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -171,7 +171,7 @@
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- qemu_register_reset(main_cpu_reset, env);
+ qemu_register_reset(main_cpu_reset, 0, env);
/* allocate RAM */
if (ram_size > (256 << 20)) {
diff --git a/hw/musicpal.c b/hw/musicpal.c
index fe06586..16476f2 100644
--- a/hw/musicpal.c
+++ b/hw/musicpal.c
@@ -441,7 +441,7 @@
musicpal_audio_writefn, s);
cpu_register_physical_memory(MP_AUDIO_BASE, MP_AUDIO_SIZE, iomemtype);
- qemu_register_reset(musicpal_audio_reset, s);
+ qemu_register_reset(musicpal_audio_reset, 0, s);
return i2c;
}
@@ -1046,7 +1046,7 @@
mv88w8618_pic_writefn, s);
sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
- qemu_register_reset(mv88w8618_pic_reset, s);
+ qemu_register_reset(mv88w8618_pic_reset, 0, s);
}
/* PIT register offsets */
diff --git a/hw/nseries.c b/hw/nseries.c
index c219bfe..b412aa0 100644
--- a/hw/nseries.c
+++ b/hw/nseries.c
@@ -1329,7 +1329,7 @@
binfo->initrd_filename = initrd_filename;
arm_load_kernel(s->cpu->env, binfo);
- qemu_register_reset(n8x0_boot_init, s);
+ qemu_register_reset(n8x0_boot_init, 0, s);
n8x0_boot_init(s);
}
diff --git a/hw/omap1.c b/hw/omap1.c
index e6e0b3e..4a479b4 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -4797,7 +4797,7 @@
omap_setup_dsp_mapping(omap15xx_dsp_mm);
omap_setup_mpui_io(s);
- qemu_register_reset(omap1_mpu_reset, s);
+ qemu_register_reset(omap1_mpu_reset, 0, s);
return s;
}
diff --git a/hw/omap2.c b/hw/omap2.c
index 8aaa9c9..6fccca4 100644
--- a/hw/omap2.c
+++ b/hw/omap2.c
@@ -4868,7 +4868,7 @@
* GPMC registers 6800a000 6800afff
*/
- qemu_register_reset(omap2_mpu_reset, s);
+ qemu_register_reset(omap2_mpu_reset, 0, s);
return s;
}
diff --git a/hw/openpic.c b/hw/openpic.c
index 561c609..51c8ad8 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -1249,7 +1249,7 @@
opp->need_swap = 1;
register_savevm("openpic", 0, 2, openpic_save, openpic_load, opp);
- qemu_register_reset(openpic_reset, opp);
+ qemu_register_reset(openpic_reset, 0, opp);
opp->irq_raise = openpic_irq_raise;
opp->reset = openpic_reset;
@@ -1709,7 +1709,7 @@
mpp->reset = mpic_reset;
register_savevm("mpic", 0, 2, openpic_save, openpic_load, mpp);
- qemu_register_reset(mpic_reset, mpp);
+ qemu_register_reset(mpic_reset, 0, mpp);
mpp->reset(mpp);
return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
diff --git a/hw/parallel.c b/hw/parallel.c
index dd2eeda..f66e5eb 100644
--- a/hw/parallel.c
+++ b/hw/parallel.c
@@ -448,7 +448,7 @@
s->irq = irq;
s->chr = chr;
parallel_reset(s);
- qemu_register_reset(parallel_reset, s);
+ qemu_register_reset(parallel_reset, 0, s);
if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
s->hw_driver = 1;
@@ -541,7 +541,7 @@
s->chr = chr;
s->it_shift = it_shift;
parallel_reset(s);
- qemu_register_reset(parallel_reset, s);
+ qemu_register_reset(parallel_reset, 0, s);
io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
cpu_register_physical_memory(base, 8 << it_shift, io_sw);
diff --git a/hw/pc.c b/hw/pc.c
index e9682fa..faaa60f 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -81,7 +81,7 @@
cpu_physical_memory_read(addr, rrd->data, size);
rrd->addr = addr;
rrd->size = size;
- qemu_register_reset(option_rom_reset, rrd);
+ qemu_register_reset(option_rom_reset, 0, rrd);
}
static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
@@ -875,7 +875,7 @@
/* XXX: enable it in all cases */
env->cpuid_features |= CPUID_APIC;
}
- qemu_register_reset(main_cpu_reset, env);
+ qemu_register_reset(main_cpu_reset, 0, env);
if (pci_enabled) {
apic_init(env);
}
diff --git a/hw/pckbd.c b/hw/pckbd.c
index dd52651..3ef3594 100644
--- a/hw/pckbd.c
+++ b/hw/pckbd.c
@@ -381,7 +381,7 @@
#ifdef TARGET_I386
vmmouse_init(s->mouse);
#endif
- qemu_register_reset(kbd_reset, s);
+ qemu_register_reset(kbd_reset, 0, s);
}
/* Memory mapped interface */
@@ -438,5 +438,5 @@
#ifdef TARGET_I386
vmmouse_init(s->mouse);
#endif
- qemu_register_reset(kbd_reset, s);
+ qemu_register_reset(kbd_reset, 0, s);
}
diff --git a/hw/pl181.c b/hw/pl181.c
index 277607c..2ba7f28 100644
--- a/hw/pl181.c
+++ b/hw/pl181.c
@@ -458,7 +458,7 @@
sysbus_init_irq(dev, &s->irq[1]);
bd = qdev_init_bdrv(&dev->qdev, IF_SD);
s->card = sd_init(bd, 0);
- qemu_register_reset(pl181_reset, s);
+ qemu_register_reset(pl181_reset, 0, s);
pl181_reset(s);
/* ??? Save/restore. */
}
diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c
index 1ace32e..a8f9a28 100644
--- a/hw/ppc405_boards.c
+++ b/hw/ppc405_boards.c
@@ -165,7 +165,7 @@
ref405ep_fpga_write, fpga);
cpu_register_physical_memory(base, 0x00000100, fpga_memory);
ref405ep_fpga_reset(fpga);
- qemu_register_reset(&ref405ep_fpga_reset, fpga);
+ qemu_register_reset(&ref405ep_fpga_reset, 0, fpga);
}
static void ref405ep_init (ram_addr_t ram_size,
@@ -483,7 +483,7 @@
taihu_cpld_write, cpld);
cpu_register_physical_memory(base, 0x00000100, cpld_memory);
taihu_cpld_reset(cpld);
- qemu_register_reset(&taihu_cpld_reset, cpld);
+ qemu_register_reset(&taihu_cpld_reset, 0, cpld);
}
static void taihu_405ep_init(ram_addr_t ram_size,
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index dfe1905..8dc33c7 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -173,7 +173,7 @@
ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
ppc4xx_plb_reset(plb);
- qemu_register_reset(ppc4xx_plb_reset, plb);
+ qemu_register_reset(ppc4xx_plb_reset, 0, plb);
}
/*****************************************************************************/
@@ -249,7 +249,7 @@
ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
- qemu_register_reset(ppc4xx_pob_reset, pob);
+ qemu_register_reset(ppc4xx_pob_reset, 0, pob);
ppc4xx_pob_reset(env);
}
@@ -386,7 +386,7 @@
#endif
ppc4xx_mmio_register(env, mmio, offset, 0x002,
opba_read, opba_write, opba);
- qemu_register_reset(ppc4xx_opba_reset, opba);
+ qemu_register_reset(ppc4xx_opba_reset, 0, opba);
ppc4xx_opba_reset(opba);
}
@@ -580,7 +580,7 @@
ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
ebc_reset(ebc);
- qemu_register_reset(&ebc_reset, ebc);
+ qemu_register_reset(&ebc_reset, 0, ebc);
ppc_dcr_register(env, EBC0_CFGADDR,
ebc, &dcr_read_ebc, &dcr_write_ebc);
ppc_dcr_register(env, EBC0_CFGDATA,
@@ -672,7 +672,7 @@
dma = qemu_mallocz(sizeof(ppc405_dma_t));
memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
ppc405_dma_reset(dma);
- qemu_register_reset(&ppc405_dma_reset, dma);
+ qemu_register_reset(&ppc405_dma_reset, 0, dma);
ppc_dcr_register(env, DMA0_CR0,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CT0,
@@ -837,7 +837,7 @@
gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
gpio->base = offset;
ppc405_gpio_reset(gpio);
- qemu_register_reset(&ppc405_gpio_reset, gpio);
+ qemu_register_reset(&ppc405_gpio_reset, 0, gpio);
#ifdef DEBUG_GPIO
printf("%s: offset " PADDRX "\n", __func__, offset);
#endif
@@ -1028,7 +1028,7 @@
ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
ocm->offset = qemu_ram_alloc(4096);
ocm_reset(ocm);
- qemu_register_reset(&ocm_reset, ocm);
+ qemu_register_reset(&ocm_reset, 0, ocm);
ppc_dcr_register(env, OCM0_ISARC,
ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc_dcr_register(env, OCM0_ISACNTL,
@@ -1280,7 +1280,7 @@
#endif
ppc4xx_mmio_register(env, mmio, offset, 0x011,
i2c_read, i2c_write, i2c);
- qemu_register_reset(ppc4xx_i2c_reset, i2c);
+ qemu_register_reset(ppc4xx_i2c_reset, 0, i2c);
}
/*****************************************************************************/
@@ -1562,7 +1562,7 @@
#endif
ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
gpt_read, gpt_write, gpt);
- qemu_register_reset(ppc4xx_gpt_reset, gpt);
+ qemu_register_reset(ppc4xx_gpt_reset, 0, gpt);
}
/*****************************************************************************/
@@ -1787,7 +1787,7 @@
for (i = 0; i < 4; i++)
mal->irqs[i] = irqs[i];
ppc40x_mal_reset(mal);
- qemu_register_reset(&ppc40x_mal_reset, mal);
+ qemu_register_reset(&ppc40x_mal_reset, 0, mal);
ppc_dcr_register(env, MAL0_CFG,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_ESR,
@@ -2171,7 +2171,7 @@
ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc405cr_clk_init(cpc);
- qemu_register_reset(ppc405cr_cpc_reset, cpc);
+ qemu_register_reset(ppc405cr_cpc_reset, 0, cpc);
ppc405cr_cpc_reset(cpc);
}
@@ -2493,7 +2493,7 @@
cpc->jtagid = 0x20267049;
cpc->sysclk = sysclk;
ppc405ep_cpc_reset(cpc);
- qemu_register_reset(&ppc405ep_cpc_reset, cpc);
+ qemu_register_reset(&ppc405ep_cpc_reset, 0, cpc);
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
index ddee8f6..5c8d273 100644
--- a/hw/ppc4xx_devs.c
+++ b/hw/ppc4xx_devs.c
@@ -60,7 +60,7 @@
tb_clk->opaque = env;
ppc_dcr_init(env, NULL, NULL);
/* Register qemu callbacks */
- qemu_register_reset(&cpu_ppc_reset, env);
+ qemu_register_reset(&cpu_ppc_reset, 0, env);
return env;
}
@@ -498,7 +498,7 @@
ppc_dcr_register(env, dcr_base + i, uic,
&dcr_read_uic, &dcr_write_uic);
}
- qemu_register_reset(ppcuic_reset, uic);
+ qemu_register_reset(ppcuic_reset, 0, uic);
ppcuic_reset(uic);
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
@@ -834,7 +834,7 @@
memcpy(sdram->ram_sizes, ram_sizes,
nbanks * sizeof(target_phys_addr_t));
sdram_reset(sdram);
- qemu_register_reset(&sdram_reset, sdram);
+ qemu_register_reset(&sdram_reset, 0, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA,
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index 5198bbb..7ebfcc0 100644
--- a/hw/ppc4xx_pci.c
+++ b/hw/ppc4xx_pci.c
@@ -403,7 +403,7 @@
goto free;
cpu_register_physical_memory(registers, PCI_REG_SIZE, index);
- qemu_register_reset(ppc4xx_pci_reset, controller);
+ qemu_register_reset(ppc4xx_pci_reset, 0, controller);
/* XXX load/save code not tested. */
register_savevm("ppc4xx_pci", ppc4xx_pci_id++, 1,
diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index ce35dd9..88ad99d 100644
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@ -128,7 +128,7 @@
#if 0
env->osi_call = vga_osi_call;
#endif
- qemu_register_reset(&cpu_ppc_reset, env);
+ qemu_register_reset(&cpu_ppc_reset, 0, env);
envs[i] = env;
}
diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
index 377ed59..aeac6ae 100644
--- a/hw/ppc_oldworld.c
+++ b/hw/ppc_oldworld.c
@@ -154,7 +154,7 @@
/* Set time-base frequency to 16.6 Mhz */
cpu_ppc_tb_init(env, 16600000UL);
env->osi_call = vga_osi_call;
- qemu_register_reset(&cpu_ppc_reset, env);
+ qemu_register_reset(&cpu_ppc_reset, 0, env);
envs[i] = env;
}
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index ef499b3..4832107 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -573,7 +573,7 @@
/* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
}
- qemu_register_reset(&cpu_ppc_reset, env);
+ qemu_register_reset(&cpu_ppc_reset, 0, env);
envs[i] = env;
}
diff --git a/hw/ps2.c b/hw/ps2.c
index fb77005..b1352d0 100644
--- a/hw/ps2.c
+++ b/hw/ps2.c
@@ -593,7 +593,7 @@
ps2_reset(&s->common);
register_savevm("ps2kbd", 0, 3, ps2_kbd_save, ps2_kbd_load, s);
qemu_add_kbd_event_handler(ps2_put_keycode, s);
- qemu_register_reset(ps2_reset, &s->common);
+ qemu_register_reset(ps2_reset, 0, &s->common);
return s;
}
@@ -606,6 +606,6 @@
ps2_reset(&s->common);
register_savevm("ps2mouse", 0, 2, ps2_mouse_save, ps2_mouse_load, s);
qemu_add_mouse_event_handler(ps2_mouse_event, s, 0, "QEMU PS/2 Mouse");
- qemu_register_reset(ps2_reset, &s->common);
+ qemu_register_reset(ps2_reset, 0, &s->common);
return s;
}
diff --git a/hw/rc4030.c b/hw/rc4030.c
index 7fe84ff..a35360a 100644
--- a/hw/rc4030.c
+++ b/hw/rc4030.c
@@ -810,7 +810,7 @@
s->timer_irq = timer;
s->jazz_bus_irq = jazz_bus;
- qemu_register_reset(rc4030_reset, s);
+ qemu_register_reset(rc4030_reset, 0, s);
register_savevm("rc4030", 0, 2, rc4030_save, rc4030_load, s);
rc4030_reset(s);
diff --git a/hw/sbi.c b/hw/sbi.c
index 1993eec..a601a59 100644
--- a/hw/sbi.c
+++ b/hw/sbi.c
@@ -155,7 +155,7 @@
cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory);
register_savevm("sbi", addr, 1, sbi_save, sbi_load, s);
- qemu_register_reset(sbi_reset, s);
+ qemu_register_reset(sbi_reset, 0, s);
*irq = qemu_allocate_irqs(sbi_set_irq, s, 32);
*cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS);
sbi_reset(s);
diff --git a/hw/serial.c b/hw/serial.c
index ac089fc..a82c29c 100644
--- a/hw/serial.c
+++ b/hw/serial.c
@@ -718,7 +718,7 @@
s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s);
- qemu_register_reset(serial_reset, s);
+ qemu_register_reset(serial_reset, 0, s);
serial_reset(s);
qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c
index b688934..e39e4f9 100644
--- a/hw/slavio_intctl.c
+++ b/hw/slavio_intctl.c
@@ -407,7 +407,7 @@
register_savevm("slavio_intctl", addr, 1, slavio_intctl_save,
slavio_intctl_load, s);
- qemu_register_reset(slavio_intctl_reset, s);
+ qemu_register_reset(slavio_intctl_reset, 0, s);
*irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
*cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
diff --git a/hw/slavio_misc.c b/hw/slavio_misc.c
index ecece54..f335863 100644
--- a/hw/slavio_misc.c
+++ b/hw/slavio_misc.c
@@ -501,7 +501,7 @@
register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
s);
- qemu_register_reset(slavio_misc_reset, s);
+ qemu_register_reset(slavio_misc_reset, 0, s);
slavio_misc_reset(s);
return s;
diff --git a/hw/slavio_timer.c b/hw/slavio_timer.c
index 725b16d..b5f9ec3 100644
--- a/hw/slavio_timer.c
+++ b/hw/slavio_timer.c
@@ -391,7 +391,7 @@
slavio_timer_io_memory);
register_savevm("slavio_timer", addr, 3, slavio_timer_save,
slavio_timer_load, s);
- qemu_register_reset(slavio_timer_reset, s);
+ qemu_register_reset(slavio_timer_reset, 0, s);
slavio_timer_reset(s);
return s;
diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c
index cab9af7..6893b88 100644
--- a/hw/sparc32_dma.c
+++ b/hw/sparc32_dma.c
@@ -256,7 +256,7 @@
cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory);
register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
- qemu_register_reset(dma_reset, s);
+ qemu_register_reset(dma_reset, 0, s);
*dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
*reset = &s->dev_reset;
diff --git a/hw/sun4c_intctl.c b/hw/sun4c_intctl.c
index 1b55557..8978e48 100644
--- a/hw/sun4c_intctl.c
+++ b/hw/sun4c_intctl.c
@@ -213,7 +213,7 @@
register_savevm("sun4c_intctl", addr, 1, sun4c_intctl_save,
sun4c_intctl_load, s);
- qemu_register_reset(sun4c_intctl_reset, s);
+ qemu_register_reset(sun4c_intctl_reset, 0, s);
*irq = qemu_allocate_irqs(sun4c_set_irq, s, 8);
sun4c_intctl_reset(s);
diff --git a/hw/sun4m.c b/hw/sun4m.c
index a2e0231..af9f871 100644
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -418,9 +418,9 @@
cpu_sparc_set_id(env, i);
envs[i] = env;
if (i == 0) {
- qemu_register_reset(main_cpu_reset, env);
+ qemu_register_reset(main_cpu_reset, 0, env);
} else {
- qemu_register_reset(secondary_cpu_reset, env);
+ qemu_register_reset(secondary_cpu_reset, 0, env);
env->halted = 1;
}
cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
@@ -1201,9 +1201,9 @@
cpu_sparc_set_id(env, i);
envs[i] = env;
if (i == 0) {
- qemu_register_reset(main_cpu_reset, env);
+ qemu_register_reset(main_cpu_reset, 0, env);
} else {
- qemu_register_reset(secondary_cpu_reset, env);
+ qemu_register_reset(secondary_cpu_reset, 0, env);
env->halted = 1;
}
cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
@@ -1416,7 +1416,7 @@
cpu_sparc_set_id(env, 0);
- qemu_register_reset(main_cpu_reset, env);
+ qemu_register_reset(main_cpu_reset, 0, env);
cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
env->prom_addr = hwdef->slavio_base;
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 08789bc..f5bb732 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -374,7 +374,7 @@
reset_info = qemu_mallocz(sizeof(ResetData));
reset_info->env = env;
reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
- qemu_register_reset(main_cpu_reset, reset_info);
+ qemu_register_reset(main_cpu_reset, 0, reset_info);
main_cpu_reset(reset_info);
// Override warm reset address with cold start address
env->pc = hwdef->prom_addr + 0x20ULL;
diff --git a/hw/tcx.c b/hw/tcx.c
index 99e65a0..450ff9d 100644
--- a/hw/tcx.c
+++ b/hw/tcx.c
@@ -560,7 +560,7 @@
dummy_memory);
register_savevm("tcx", addr, 4, tcx_save, tcx_load, s);
- qemu_register_reset(tcx_reset, s);
+ qemu_register_reset(tcx_reset, 0, s);
tcx_reset(s);
qemu_console_resize(s->ds, width, height);
}
diff --git a/hw/tsc2005.c b/hw/tsc2005.c
index 2e71b8e..36d6b53 100644
--- a/hw/tsc2005.c
+++ b/hw/tsc2005.c
@@ -548,7 +548,7 @@
qemu_add_mouse_event_handler(tsc2005_touchscreen_event, s, 1,
"QEMU TSC2005-driven Touchscreen");
- qemu_register_reset((void *) tsc2005_reset, s);
+ qemu_register_reset((void *) tsc2005_reset, 0, s);
register_savevm("tsc2005", -1, 0, tsc2005_save, tsc2005_load, s);
return s;
diff --git a/hw/tsc210x.c b/hw/tsc210x.c
index 16874e0..a5ab574 100644
--- a/hw/tsc210x.c
+++ b/hw/tsc210x.c
@@ -1143,7 +1143,7 @@
AUD_register_card(s->name, &s->card);
- qemu_register_reset((void *) tsc210x_reset, s);
+ qemu_register_reset((void *) tsc210x_reset, 0, s);
register_savevm(s->name, -1, 0,
tsc210x_save, tsc210x_load, s);
@@ -1194,7 +1194,7 @@
AUD_register_card(s->name, &s->card);
- qemu_register_reset((void *) tsc210x_reset, s);
+ qemu_register_reset((void *) tsc210x_reset, 0, s);
register_savevm(s->name, -1, 0, tsc210x_save, tsc210x_load, s);
return &s->chip;
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index 8277b67..b9c1821 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -265,7 +265,7 @@
d->config[0x34] = 0x00; // capabilities_pointer
#endif
register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, d);
- qemu_register_reset(pci_unin_reset, d);
+ qemu_register_reset(pci_unin_reset, 0, d);
pci_unin_reset(d);
return s->bus;
diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c
index 09944d0..1cc1b62 100644
--- a/hw/usb-ohci.c
+++ b/hw/usb-ohci.c
@@ -1695,7 +1695,7 @@
}
ohci->async_td = 0;
- qemu_register_reset(ohci_reset, ohci);
+ qemu_register_reset(ohci_reset, 0, ohci);
ohci_reset(ohci);
}
diff --git a/hw/vga.c b/hw/vga.c
index d228c59..013ff10 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -2306,7 +2306,7 @@
{
int vga_io_memory;
- qemu_register_reset(vga_reset, s);
+ qemu_register_reset(vga_reset, 0, s);
register_savevm("vga", 0, 2, vga_save, vga_load, s);
register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
diff --git a/hw/virtio.c b/hw/virtio.c
index 463d74b..45a49fa 100644
--- a/hw/virtio.c
+++ b/hw/virtio.c
@@ -636,7 +636,8 @@
else
vdev->config = NULL;
- qemu_register_reset(virtio_reset, vdev);
+ qemu_register_reset(virtio_reset, 0, vdev);
+
return vdev;
}
diff --git a/vl.c b/vl.c
index 5079a1c..9d7ee7a 100644
--- a/vl.c
+++ b/vl.c
@@ -3579,6 +3579,7 @@
typedef struct QEMUResetEntry {
QEMUResetHandler *func;
void *opaque;
+ int order;
struct QEMUResetEntry *next;
} QEMUResetEntry;
@@ -3634,16 +3635,18 @@
}
}
-void qemu_register_reset(QEMUResetHandler *func, void *opaque)
+void qemu_register_reset(QEMUResetHandler *func, int order, void *opaque)
{
QEMUResetEntry **pre, *re;
pre = &first_reset_entry;
- while (*pre != NULL)
+ while (*pre != NULL && (*pre)->order >= order) {
pre = &(*pre)->next;
+ }
re = qemu_mallocz(sizeof(QEMUResetEntry));
re->func = func;
re->opaque = opaque;
+ re->order = order;
re->next = NULL;
*pre = re;
}