)]}'
{
  "commit": "81cc5f39aa3042e9c0b2ea772b42a2c8b1488e76",
  "tree": "80042eb7e15a534441fbe333827911c62c244f22",
  "parents": [
    "8767de709f14be5366525c3080dfab983a0a0593",
    "44f2c7f3df0028de7991385f568add12e24aca47"
  ],
  "author": {
    "name": "Stefan Hajnoczi",
    "email": "stefanha@redhat.com",
    "time": "Fri May 29 12:58:24 2026 -0400"
  },
  "committer": {
    "name": "Stefan Hajnoczi",
    "email": "stefanha@redhat.com",
    "time": "Fri May 29 12:58:25 2026 -0400"
  },
  "message": "Merge tag \u0027pull-target-arm-20260529\u0027 of https://gitlab.com/pm215/qemu into staging\n\ntarget-arm queue:\n * target/arm: Implement FEAT_CMPBR emulation\n * target/arm: Implement FEAT_RNG_TRAP emulation\n * target/arm: Don\u0027t assert if 64-bit EL2 AT insn sees a Domain fault\n * target/arm: SME BFCVT, BFCVTN have \"Alternate BFloat16 behaviors\"\n * target/arm: Enable REVD for SVE2.1\n * zynq: Various minor bug fixes\n * hw/misc: Add dummy ZYNQ DDR controller\n * hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d\n * hw/dma/omap_dma: Remove unused ifdeffed out code\n\n# -----BEGIN PGP SIGNATURE-----\n#\n# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmoZfIwZHHBldGVyLm1h\n# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3hUiD/9lXml75H4e0JxPkpxjWAVV\n# ssgdTHavEl33IFk443gacfgm90xZ6IhLtuk/Ba5wQf2OrqmQQw0ttnGUaPuS9cYl\n# n2+TlOLWRbCU8ELymsrIamIW4B8WJteVajBKz2uDhARGHlZNq1UvrNv3w7rs6VdP\n# dwYUQ0WhPMyI2MhQ3dL1CY1Sva7K7BmzFZMMkPpsEiEOGVqIkyfgiOL3DhtFOZ3g\n# P2nTVtzxknpWAYPWsMicMtxH1apRWB8WU5BM31gfxNQ27qAmlbi1jPHKOmo76h6b\n# UL3BFIC8J29/44q6CrVhp7SoDG5l+aQYF/ndl7N7i6/cwxfTIgHl1av8VcGybMwk\n# N40xAw8laHqkReErRxghrdoNir3UBZwwO7thB0aOZhuHHisG4jvAFawspmwQBePV\n# FUEuOmYmK0HR90aurBPOnjgFmF/KA5FPNuC12MJsnFcyrPTDwfPP1FSkCls46KYl\n# Jt/HMCcqUwBO2ZkLjAQvmxjSMvnC2HFCh1MidXpV06SOl6zR0OjUACDfYcbnw+N0\n# TKt86Uu61nabIaY4A79PV9Mju8Tm/RQEf6ZC5bTntIVZjNV9oaOQeXNASXZVEOty\n# eudivT3V5Zy1fwgwMekOMh3ary5J4pc0Bo4SUUaX+xdSklR4zmQ7oCxlyNaDheoA\n# F+GSTl6pshzoaka6k1hl1Q\u003d\u003d\n# \u003dPFSX\n# -----END PGP SIGNATURE-----\n# gpg: Signature made Fri 29 May 2026 07:46:20 EDT\n# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE\n# gpg:                issuer \"peter.maydell@linaro.org\"\n# gpg: Good signature from \"Peter Maydell \u003cpeter.maydell@linaro.org\u003e\" [full]\n# gpg:                 aka \"Peter Maydell \u003cpmaydell@gmail.com\u003e\" [full]\n# gpg:                 aka \"Peter Maydell \u003cpmaydell@chiark.greenend.org.uk\u003e\" [full]\n# gpg:                 aka \"Peter Maydell \u003cpeter@archaic.org.uk\u003e\" [unknown]\n# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE\n\n* tag \u0027pull-target-arm-20260529\u0027 of https://gitlab.com/pm215/qemu: (21 commits)\n  hw/dma/omap_dma: Fix indentation after ifdef removal\n  hw/dma/omap_dma: Fix coding style in omap_dma_transfer_setup()\n  hw/dma/omap_dma: Remove unused ifdeffed out code\n  target/arm: advertise FEAT_RNG_TRAP on cortex-max\n  target/arm: implement FEAT_RNG_TRAP for RNDR/RNDRRS\n  target/arm: SME BFCVT, BFCVTN have \"Alternate BFloat16 behaviors\"\n  target/arm: Don\u0027t assert if 64-bit EL2 AT insn sees a Domain fault\n  target/arm: Enable FEAT_CMPBR for -cpu max\n  target/arm: Implement CB (immediate)\n  target/arm: Implement CB, CBB, CBH\n  target/arm: Add feature predicate for FEAT_CMPBR\n  hw/arm/xilinx_zynq: Split xilinx_zynq into header and implementation files\n  hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d\n  hw/misc/zynq_slcr: Add logic for DCI configuration\n  hw/misc: Add dummy ZYNQ DDR controller\n  hw/dma/zynq-devcfg: Indicate power-up status of PL\n  hw/dma/zynq-devcfg: Simulate dummy PL reset\n  hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in user mode\n  hw/arm/zynq-devcfg: Prevent unintended unlock during initialization\n  hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff\n  ...\n\nSigned-off-by: Stefan Hajnoczi \u003cstefanha@redhat.com\u003e\n",
  "tree_diff": []
}