)]}'
{
  "commit": "818272ac89ca8a98f930d4759762765dc12349bd",
  "tree": "7834a3d2f7789a6e8dd8ab9ab4c34f119aad8e56",
  "parents": [
    "47aad5e8e3f09fe562012fad1e8feb1e1728fa76"
  ],
  "author": {
    "name": "James Hilliard",
    "email": "james.hilliard1@gmail.com",
    "time": "Fri May 08 10:51:24 2026 +0200"
  },
  "committer": {
    "name": "Philippe Mathieu-Daudé",
    "email": "philmd@linaro.org",
    "time": "Thu May 21 08:20:58 2026 +0200"
  },
  "message": "target/mips: add Octeon SAA instruction\n\nSAA atomically adds rt to the naturally aligned 32-bit word at base and\ndiscards the old memory value.\n\nImplement the common SAA/SAAD translator with TCG atomic_fetch_add_i64.\nThe MemOp selects the word or doubleword transaction size.  QEMU only has\none Octeon CPU model today, so keep SAA/SAAD under the existing Octeon\ninstruction feature bucket instead of adding a finer-grained Octeon+\nfeature bit.\n\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nSigned-off-by: James Hilliard \u003cjames.hilliard1@gmail.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nMessage-Id: \u003c20260520172313.23777-14-philmd@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "db7d5f55f0a871384fbfeb17416b81ff8c13b9e1",
      "old_mode": 33188,
      "old_path": "target/mips/tcg/octeon.decode",
      "new_id": "d6b241de421b197f5441d3653aa84e0982f71dd7",
      "new_mode": 33188,
      "new_path": "target/mips/tcg/octeon.decode"
    },
    {
      "type": "modify",
      "old_id": "401c4bd14bb46de914556084a3ffa7afa3bcf6f3",
      "old_mode": 33188,
      "old_path": "target/mips/tcg/octeon_translate.c",
      "new_id": "33b45611f20e8eb4dd6edab3598abda8eb25a645",
      "new_mode": 33188,
      "new_path": "target/mips/tcg/octeon_translate.c"
    }
  ]
}