tree 16d2ed9f0fbb2e06c226425b3ccd4f8b22285983
parent a1f0083c6e3eee2d80e712e8a03abd70b25df097
author Bin Meng <bmeng@tinylab.org> 1677591929 +0800
committer Palmer Dabbelt <palmer@rivosinc.com> 1677717620 -0800
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target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml

It's worth noting that the vector CSR predicate() has a similar
run-time check logic to the FPU CSR. With the previous patch our
gdbstub can correctly report these vector CSRs via the CSR xml.

Commit 719d3561b269 ("target/riscv: gdb: support vector registers for rv64 & rv32")
inserted these vector CSRs in an ad-hoc, non-standard way in the
riscv-vector.xml. Now we can treat these CSRs no different from
other CSRs.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-13-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>