target-xtensa: add regression testsuite
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
diff --git a/tests/xtensa/Makefile b/tests/xtensa/Makefile
new file mode 100644
index 0000000..70bd097
--- /dev/null
+++ b/tests/xtensa/Makefile
@@ -0,0 +1,74 @@
+-include ../../config-host.mak
+
+CROSS=xtensa-dc232b-elf-
+
+ifndef XT
+SIM = qemu-system-xtensa
+SIMFLAGS = -M dc232b -nographic -semihosting $(EXTFLAGS) -kernel
+SIMDEBUG = -s -S
+else
+SIM = xt-run
+SIMFLAGS = --xtensa-core=DC_B_232L --exit_with_target_code $(EXTFLAGS)
+SIMDEBUG = --gdbserve=0
+endif
+
+CC = $(CROSS)gcc
+AS = $(CROSS)gcc -x assembler
+LD = $(CROSS)ld
+
+LDFLAGS = -Tlinker.ld
+
+CRT = crt.o vectors.o
+
+TESTCASES += test_b.tst
+TESTCASES += test_bi.tst
+#TESTCASES += test_boolean.tst
+TESTCASES += test_bz.tst
+TESTCASES += test_clamps.tst
+TESTCASES += test_fail.tst
+TESTCASES += test_interrupt.tst
+TESTCASES += test_loop.tst
+TESTCASES += test_max.tst
+TESTCASES += test_min.tst
+TESTCASES += test_mmu.tst
+TESTCASES += test_mul16.tst
+TESTCASES += test_mul32.tst
+TESTCASES += test_nsa.tst
+ifdef XT
+TESTCASES += test_pipeline.tst
+endif
+TESTCASES += test_quo.tst
+TESTCASES += test_rem.tst
+TESTCASES += test_rst0.tst
+TESTCASES += test_sar.tst
+TESTCASES += test_sext.tst
+TESTCASES += test_shift.tst
+TESTCASES += test_timer.tst
+TESTCASES += test_windowed.tst
+
+all: build
+
+%.o: $(SRC_PATH)/tests/xtensa/%.c
+ $(CC) $(CFLAGS) -c $< -o $@
+
+%.o: $(SRC_PATH)/tests/xtensa/%.S
+ $(AS) $(ASFLAGS) -c $< -o $@
+
+%.tst: %.o macros.inc $(CRT) Makefile
+ $(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $< -o $@
+
+build: $(TESTCASES)
+
+check: $(addprefix run-, $(TESTCASES))
+
+run-%.tst: %.tst
+ $(SIM) $(SIMFLAGS) ./$<
+
+run-test_fail.tst: test_fail.tst
+ ! $(SIM) $(SIMFLAGS) ./$<
+
+debug-%.tst: %.tst
+ $(SIM) $(SIMDEBUG) $(SIMFLAGS) ./$<
+
+clean:
+ $(RM) -fr $(TESTCASES) $(CRT)
diff --git a/tests/xtensa/crt.S b/tests/xtensa/crt.S
new file mode 100644
index 0000000..d9846ac
--- /dev/null
+++ b/tests/xtensa/crt.S
@@ -0,0 +1,24 @@
+.section .init
+ j 1f
+.section .init.text
+1:
+ movi a2, _start
+ jx a2
+
+.text
+.global _start
+_start:
+ movi a2, 1
+ wsr a2, windowstart
+ movi a2, 0
+ wsr a2, windowbase
+ movi a1, _fstack
+ movi a2, 0x4000f
+ wsr a2, ps
+ isync
+
+ call0 main
+
+ mov a3, a2
+ movi a2, 1
+ simcall
diff --git a/tests/xtensa/linker.ld b/tests/xtensa/linker.ld
new file mode 100644
index 0000000..4d0b307
--- /dev/null
+++ b/tests/xtensa/linker.ld
@@ -0,0 +1,112 @@
+OUTPUT_FORMAT("elf32-xtensa-le")
+ENTRY(_start)
+
+__DYNAMIC = 0;
+
+MEMORY {
+ ram : ORIGIN = 0xd0000000, LENGTH = 0x08000000 /* 128M */
+ rom : ORIGIN = 0xfe000000, LENGTH = 0x00001000 /* 4k */
+}
+
+SECTIONS
+{
+ .init :
+ {
+ *(.init)
+ *(.init.*)
+ } > rom
+
+ .vector :
+ {
+ . = 0x00000000;
+ *(.vector.window_overflow_4)
+ *(.vector.window_overflow_4.*)
+ . = 0x00000040;
+ *(.vector.window_underflow_4)
+ *(.vector.window_underflow_4.*)
+ . = 0x00000080;
+ *(.vector.window_overflow_8)
+ *(.vector.window_overflow_8.*)
+ . = 0x000000c0;
+ *(.vector.window_underflow_8)
+ *(.vector.window_underflow_8.*)
+ . = 0x00000100;
+ *(.vector.window_overflow_12)
+ *(.vector.window_overflow_12.*)
+ . = 0x00000140;
+ *(.vector.window_underflow_12)
+ *(.vector.window_underflow_12.*)
+
+ . = 0x00000180;
+ *(.vector.level2)
+ *(.vector.level2.*)
+ . = 0x000001c0;
+ *(.vector.level3)
+ *(.vector.level3.*)
+ . = 0x00000200;
+ *(.vector.level4)
+ *(.vector.level4.*)
+ . = 0x00000240;
+ *(.vector.level5)
+ *(.vector.level5.*)
+ . = 0x00000280;
+ *(.vector.level6)
+ *(.vector.level6.*)
+ . = 0x000002c0;
+ *(.vector.level7)
+ *(.vector.level7.*)
+
+ . = 0x00000300;
+ *(.vector.kernel)
+ *(.vector.kernel.*)
+ . = 0x00000340;
+ *(.vector.user)
+ *(.vector.user.*)
+ . = 0x000003c0;
+ *(.vector.double)
+ *(.vector.double.*)
+ } > ram
+
+ .text :
+ {
+ _ftext = .;
+ *(.text .stub .text.* .gnu.linkonce.t.* .literal .literal.*)
+ _etext = .;
+ } > ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ _frodata = .;
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ *(.rodata1)
+ _erodata = .;
+ } > ram
+
+ .data :
+ {
+ . = ALIGN(4);
+ _fdata = .;
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.data1)
+ _gp = ALIGN(16);
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ _edata = .;
+ } > ram
+
+ .bss :
+ {
+ . = ALIGN(4);
+ _fbss = .;
+ *(.dynsbss)
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ _ebss = .;
+ _end = .;
+ } > ram
+}
+
+PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4);
diff --git a/tests/xtensa/macros.inc b/tests/xtensa/macros.inc
new file mode 100644
index 0000000..2d4515e
--- /dev/null
+++ b/tests/xtensa/macros.inc
@@ -0,0 +1,68 @@
+.macro test_suite name
+.data
+status: .word result
+result: .space 20
+.text
+.global main
+.align 4
+main:
+.endm
+
+.macro reset_ps
+ movi a2, 0x4000f
+ wsr a2, ps
+ isync
+.endm
+
+.macro test_suite_end
+ reset_ps
+ movi a0, status
+ l32i a2, a0, 0
+ movi a0, result
+ sub a2, a2, a0
+ movi a3, 0
+ loopnez a2, 1f
+ l8ui a2, a0, 0
+ or a3, a3, a2
+ addi a0, a0, 1
+1:
+ exit
+.endm
+
+.macro test name
+.endm
+
+.macro test_end
+99:
+ reset_ps
+ movi a2, status
+ l32i a3, a2, 0
+ addi a3, a3, 1
+ s32i a3, a2, 0
+.endm
+
+.macro exit
+ movi a2, 1
+ simcall
+.endm
+
+.macro test_fail
+ movi a2, status
+ l32i a2, a2, 0
+ movi a3, 1
+ s8i a3, a2, 0
+ j 99f
+.endm
+
+.macro assert cond, arg1, arg2
+ b\cond \arg1, \arg2, 90f
+ test_fail
+90:
+ nop
+.endm
+
+.macro set_vector vector, addr
+ movi a2, handler_\vector
+ movi a3, \addr
+ s32i a3, a2, 0
+.endm
diff --git a/tests/xtensa/test_b.S b/tests/xtensa/test_b.S
new file mode 100644
index 0000000..6cbe5f1
--- /dev/null
+++ b/tests/xtensa/test_b.S
@@ -0,0 +1,221 @@
+.include "macros.inc"
+
+test_suite b
+
+test bnone
+ movi a2, 0xa5a5ff00
+ movi a3, 0x5a5a00ff
+ bnone a2, a3, 1f
+ test_fail
+1:
+ movi a2, 0xa5a5ff01
+ bnone a2, a3, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test beq
+ movi a2, 0
+ movi a3, 0
+ beq a2, a3, 1f
+ test_fail
+1:
+ movi a2, 1
+ beq a2, a3, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test blt
+ movi a2, 6
+ movi a3, 7
+ blt a2, a3, 1f
+ test_fail
+1:
+ movi a2, 0xffffffff
+ blt a2, a3, 1f
+ test_fail
+1:
+ movi a2, 7
+ blt a2, a3, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bltu
+ movi a2, 6
+ movi a3, 7
+ bltu a2, a3, 1f
+ test_fail
+1:
+ movi a2, 7
+ bltu a2, a3, 1f
+ j 2f
+1:
+ test_fail
+2:
+ movi a2, 0xffffffff
+ bltu a2, a3, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test ball
+ movi a2, 0xa5a5ffa5
+ movi a3, 0xa5a5ff00
+ ball a2, a3, 1f
+ test_fail
+1:
+ movi a2, 0xa5a5a5a5
+ ball a2, a3, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bbc
+ movi a2, 0xfffffffd
+ movi a3, 0xffffff01
+ bbc a2, a3, 1f
+ test_fail
+1:
+ movi a2, 8
+ movi a3, 0xffffff03
+ bbc a2, a3, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bbci
+ movi a2, 0xfffdffff
+ bbci a2, 17, 1f
+ test_fail
+1:
+ movi a2, 0x00020000
+ bbci a2, 17, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bany
+ movi a2, 0xa5a5ff01
+ movi a3, 0x5a5a00ff
+ bany a2, a3, 1f
+ test_fail
+1:
+ movi a2, 0xa5a5ff00
+ bany a2, a3, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bne
+ movi a2, 1
+ movi a3, 0
+ bne a2, a3, 1f
+ test_fail
+1:
+ movi a2, 0
+ bne a2, a3, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bge
+ movi a2, 7
+ movi a3, 7
+ bge a2, a3, 1f
+ test_fail
+1:
+ movi a2, 6
+ bge a2, a3, 1f
+ j 2f
+1:
+ test_fail
+2:
+ movi a2, 0xffffffff
+ bge a2, a3, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bgeu
+ movi a2, 7
+ movi a3, 7
+ bgeu a2, a3, 1f
+ test_fail
+1:
+ movi a2, 0xffffffff
+ bgeu a2, a3, 1f
+ test_fail
+1:
+ movi a2, 6
+ bgeu a2, a3, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bnall
+ movi a2, 0xa5a5a5a5
+ movi a3, 0xa5a5ff00
+ bnall a2, a3, 1f
+ test_fail
+1:
+ movi a2, 0xa5a5ffa5
+ bnall a2, a3, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bbs
+ movi a2, 8
+ movi a3, 0xffffff03
+ bbs a2, a3, 1f
+ test_fail
+1:
+ movi a2, 0xfffffffd
+ movi a3, 0xffffff01
+ bbs a2, a3, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bbsi
+ movi a2, 0x00020000
+ bbsi a2, 17, 1f
+ test_fail
+1:
+ movi a2, 0xfffdffff
+ bbsi a2, 17, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_bi.S b/tests/xtensa/test_bi.S
new file mode 100644
index 0000000..6a5f1df
--- /dev/null
+++ b/tests/xtensa/test_bi.S
@@ -0,0 +1,103 @@
+.include "macros.inc"
+
+test_suite bi
+
+test beqi
+ movi a2, 7
+ beqi a2, 7, 1f
+ test_fail
+1:
+ movi a2, 1
+ beqi a2, 7, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bnei
+ movi a2, 1
+ bnei a2, 7, 1f
+ test_fail
+1:
+ movi a2, 7
+ bnei a2, 7, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test blti
+ movi a2, 6
+ blti a2, 7, 1f
+ test_fail
+1:
+ movi a2, 0xffffffff
+ blti a2, 7, 1f
+ test_fail
+1:
+ movi a2, 7
+ blti a2, 7, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bgei
+ movi a2, 7
+ bgei a2, 7, 1f
+ test_fail
+1:
+ movi a2, 6
+ bgei a2, 7, 1f
+ j 2f
+1:
+ test_fail
+2:
+ movi a2, 0xffffffff
+ bgei a2, 7, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bltui
+ movi a2, 6
+ bltui a2, 7, 1f
+ test_fail
+1:
+ movi a2, 7
+ bltui a2, 7, 1f
+ j 2f
+1:
+ test_fail
+2:
+ movi a2, 0xffffffff
+ bltui a2, 7, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bgeui
+ movi a2, 7
+ bgeui a2, 7, 1f
+ test_fail
+1:
+ movi a2, 0xffffffff
+ bgeui a2, 7, 1f
+ test_fail
+1:
+ movi a2, 6
+ bgeui a2, 7, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_boolean.S b/tests/xtensa/test_boolean.S
new file mode 100644
index 0000000..50e6d2c
--- /dev/null
+++ b/tests/xtensa/test_boolean.S
@@ -0,0 +1,23 @@
+.include "macros.inc"
+
+test_suite boolean
+
+test all4
+ movi a2, 0xfec0
+ wsr a2, br
+ all4 b0, b0
+ rsr a3, br
+ assert eq, a2, a3
+ all4 b0, b4
+ rsr a3, br
+ assert eq, a2, a3
+ all4 b0, b8
+ rsr a3, br
+ assert eq, a2, a3
+ all4 b0, b12
+ rsr a3, br
+ addi a2, a2, 1
+ assert eq, a2, a3
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_bz.S b/tests/xtensa/test_bz.S
new file mode 100644
index 0000000..f9ba6e2
--- /dev/null
+++ b/tests/xtensa/test_bz.S
@@ -0,0 +1,57 @@
+.include "macros.inc"
+
+test_suite bz
+
+test beqz
+ movi a2, 0
+ _beqz a2, 1f
+ test_fail
+1:
+ movi a2, 1
+ _beqz a2, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bnez
+ movi a2, 1
+ _bnez a2, 1f
+ test_fail
+1:
+ movi a2, 0
+ _bnez a2, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bltz
+ movi a2, 0xffffffff
+ bltz a2, 1f
+ test_fail
+1:
+ movi a2, 0
+ bltz a2, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test bgez
+ movi a2, 0
+ bgez a2, 1f
+ test_fail
+1:
+ movi a2, 0xffffffff
+ bgez a2, 1f
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_clamps.S b/tests/xtensa/test_clamps.S
new file mode 100644
index 0000000..c186cc9
--- /dev/null
+++ b/tests/xtensa/test_clamps.S
@@ -0,0 +1,42 @@
+.include "macros.inc"
+
+test_suite clamps
+
+test clamps
+ movi a2, 0
+ movi a3, 0
+ clamps a4, a2, 7
+ assert eq, a3, a4
+
+ movi a2, 0x7f
+ movi a3, 0x7f
+ clamps a4, a2, 7
+ assert eq, a3, a4
+
+ movi a2, 0xffffff80
+ movi a3, 0xffffff80
+ clamps a4, a2, 7
+ assert eq, a3, a4
+
+ movi a2, 0x80
+ movi a3, 0x7f
+ clamps a2, a2, 7
+ assert eq, a3, a2
+
+ movi a2, 0xffffff7f
+ movi a3, 0xffffff80
+ clamps a2, a2, 7
+ assert eq, a3, a2
+
+ movi a2, 0x7fffffff
+ movi a3, 0x7f
+ clamps a2, a2, 7
+ assert eq, a3, a2
+
+ movi a2, 0x80000000
+ movi a3, 0xffffff80
+ clamps a2, a2, 7
+ assert eq, a3, a2
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_fail.S b/tests/xtensa/test_fail.S
new file mode 100644
index 0000000..e8d1b42
--- /dev/null
+++ b/tests/xtensa/test_fail.S
@@ -0,0 +1,9 @@
+.include "macros.inc"
+
+test_suite fail
+
+test fail
+ test_fail
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_interrupt.S b/tests/xtensa/test_interrupt.S
new file mode 100644
index 0000000..68b3ee1
--- /dev/null
+++ b/tests/xtensa/test_interrupt.S
@@ -0,0 +1,194 @@
+.include "macros.inc"
+
+test_suite interrupt
+
+.macro clear_interrupts
+ movi a2, 0
+ wsr a2, intenable
+ wsr a2, ccompare0
+ wsr a2, ccompare1
+ wsr a2, ccompare2
+ esync
+ rsr a2, interrupt
+ wsr a2, intclear
+
+ esync
+ rsr a2, interrupt
+ assert eqi, a2, 0
+.endm
+
+.macro check_l1
+ rsr a2, ps
+ movi a3, 0x1f /* EXCM | INTMASK */
+ and a2, a2, a3
+ assert eqi, a2, 0x10 /* only EXCM is set for level-1 interrupt */
+ rsr a2, exccause
+ assert eqi, a2, 4
+.endm
+
+test rsil
+ clear_interrupts
+
+ rsr a2, ps
+ rsil a3, 7
+ rsr a4, ps
+ assert eq, a2, a3
+ movi a2, 0xf
+ and a2, a4, a2
+ assert eqi, a2, 7
+ xor a3, a3, a4
+ movi a2, 0xfffffff0
+ and a2, a3, a2
+ assert eqi, a2, 0
+test_end
+
+test soft_disabled
+ set_vector kernel, 1f
+ clear_interrupts
+
+ movi a2, 0x80
+ wsr a2, intset
+ esync
+ rsr a3, interrupt
+ assert eq, a2, a3
+ wsr a2, intclear
+ esync
+ rsr a3, interrupt
+ assert eqi, a3, 0
+ j 2f
+1:
+ test_fail
+2:
+test_end
+
+test soft_intenable
+ set_vector kernel, 1f
+ clear_interrupts
+
+ movi a2, 0x80
+ wsr a2, intset
+ esync
+ rsr a3, interrupt
+ assert eq, a2, a3
+ rsil a3, 0
+ wsr a2, intenable
+ esync
+ test_fail
+1:
+ check_l1
+test_end
+
+test soft_rsil
+ set_vector kernel, 1f
+ clear_interrupts
+
+ movi a2, 0x80
+ wsr a2, intset
+ esync
+ rsr a3, interrupt
+ assert eq, a2, a3
+ wsr a2, intenable
+ rsil a3, 0
+ esync
+ test_fail
+1:
+ check_l1
+test_end
+
+test soft_waiti
+ set_vector kernel, 1f
+ clear_interrupts
+
+ movi a2, 0x80
+ wsr a2, intset
+ esync
+ rsr a3, interrupt
+ assert eq, a2, a3
+ wsr a2, intenable
+ waiti 0
+ test_fail
+1:
+ check_l1
+test_end
+
+test soft_user
+ set_vector kernel, 1f
+ set_vector user, 2f
+ clear_interrupts
+
+ movi a2, 0x80
+ wsr a2, intset
+ esync
+ rsr a3, interrupt
+ assert eq, a2, a3
+ wsr a2, intenable
+
+ rsr a2, ps
+ movi a3, 0x20
+ or a2, a2, a3
+ wsr a2, ps
+ waiti 0
+1:
+ test_fail
+2:
+ check_l1
+test_end
+
+test soft_priority
+ set_vector kernel, 1f
+ set_vector level3, 2f
+ clear_interrupts
+
+ movi a2, 0x880
+ wsr a2, intenable
+ rsil a3, 0
+ esync
+ wsr a2, intset
+ esync
+1:
+ test_fail
+2:
+ rsr a2, ps
+ movi a3, 0x1f /* EXCM | INTMASK */
+ and a2, a2, a3
+ movi a3, 0x13
+ assert eq, a2, a3 /* EXCM and INTMASK are set
+ for high-priority interrupt */
+test_end
+
+test eps_epc_rfi
+ set_vector level3, 3f
+ clear_interrupts
+ reset_ps
+
+ movi a2, 0x880
+ wsr a2, intenable
+ rsil a3, 0
+ rsr a3, ps
+ esync
+ wsr a2, intset
+1:
+ esync
+2:
+ test_fail
+3:
+ rsr a2, eps3
+ assert eq, a2, a3
+ rsr a2, epc3
+ movi a3, 1b
+ assert ge, a2, a3
+ movi a3, 2b
+ assert ge, a3, a2
+ movi a2, 4f
+ wsr a2, epc3
+ movi a2, 0x40003
+ wsr a2, eps3
+ rfi 3
+ test_fail
+4:
+ rsr a2, ps
+ movi a3, 0x40003
+ assert eq, a2, a3
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_loop.S b/tests/xtensa/test_loop.S
new file mode 100644
index 0000000..a5ea933
--- /dev/null
+++ b/tests/xtensa/test_loop.S
@@ -0,0 +1,77 @@
+.include "macros.inc"
+
+test_suite loop
+
+test loop
+ movi a2, 0
+ movi a3, 5
+ loop a3, 1f
+ addi a2, a2, 1
+1:
+ assert eqi, a2, 5
+test_end
+
+test loop0
+ movi a2, 0
+ loop a2, 1f
+ rsr a2, lcount
+ assert eqi, a2, -1
+ j 1f
+1:
+test_end
+
+test loop_jump
+ movi a2, 0
+ movi a3, 5
+ loop a3, 1f
+ addi a2, a2, 1
+ j 1f
+1:
+ assert eqi, a2, 1
+test_end
+
+test loop_branch
+ movi a2, 0
+ movi a3, 5
+ loop a3, 1f
+ addi a2, a2, 1
+ beqi a2, 3, 1f
+1:
+ assert eqi, a2, 3
+test_end
+
+test loop_manual
+ movi a2, 0
+ movi a3, 5
+ movi a4, 1f
+ movi a5, 2f
+ wsr a3, lcount
+ wsr a4, lbeg
+ wsr a5, lend
+ isync
+ j 1f
+.align 4
+1:
+ addi a2, a2, 1
+2:
+ assert eqi, a2, 6
+test_end
+
+test loop_excm
+ movi a2, 0
+ movi a3, 5
+ rsr a4, ps
+ movi a5, 0x10
+ or a4, a4, a5
+ wsr a4, ps
+ isync
+ loop a3, 1f
+ addi a2, a2, 1
+1:
+ xor a4, a4, a5
+ isync
+ wsr a4, ps
+ assert eqi, a2, 1
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_max.S b/tests/xtensa/test_max.S
new file mode 100644
index 0000000..2534c9d
--- /dev/null
+++ b/tests/xtensa/test_max.S
@@ -0,0 +1,81 @@
+.include "macros.inc"
+
+test_suite max
+
+test max
+ movi a2, 0xffffffff
+ movi a3, 1
+ movi a4, 1
+ max a5, a2, a3
+ assert eq, a5, a4
+
+ movi a2, 1
+ movi a3, 0xffffffff
+ movi a4, 1
+ max a5, a2, a3
+ assert eq, a5, a4
+
+ movi a2, 0xffffffff
+ movi a3, 1
+ movi a4, 1
+ max a2, a2, a3
+ assert eq, a2, a4
+
+ movi a2, 0xffffffff
+ movi a3, 1
+ movi a4, 1
+ max a3, a2, a3
+ assert eq, a3, a4
+
+ movi a2, 1
+ movi a3, 0xffffffff
+ movi a4, 1
+ max a2, a2, a3
+ assert eq, a2, a4
+
+ movi a2, 1
+ movi a3, 0xffffffff
+ movi a4, 1
+ max a3, a2, a3
+ assert eq, a3, a4
+test_end
+
+test maxu
+ movi a2, 0xffffffff
+ movi a3, 1
+ movi a4, 0xffffffff
+ maxu a5, a2, a3
+ assert eq, a5, a4
+
+ movi a2, 1
+ movi a3, 0xffffffff
+ movi a4, 0xffffffff
+ maxu a5, a2, a3
+ assert eq, a5, a4
+
+ movi a2, 0xffffffff
+ movi a3, 1
+ movi a4, 0xffffffff
+ maxu a2, a2, a3
+ assert eq, a2, a4
+
+ movi a2, 0xffffffff
+ movi a3, 1
+ movi a4, 0xffffffff
+ maxu a3, a2, a3
+ assert eq, a3, a4
+
+ movi a2, 1
+ movi a3, 0xffffffff
+ movi a4, 0xffffffff
+ maxu a2, a2, a3
+ assert eq, a2, a4
+
+ movi a2, 1
+ movi a3, 0xffffffff
+ movi a4, 0xffffffff
+ maxu a3, a2, a3
+ assert eq, a3, a4
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_min.S b/tests/xtensa/test_min.S
new file mode 100644
index 0000000..6d9ddeb
--- /dev/null
+++ b/tests/xtensa/test_min.S
@@ -0,0 +1,81 @@
+.include "macros.inc"
+
+test_suite min
+
+test min
+ movi a2, 0xffffffff
+ movi a3, 1
+ movi a4, 0xffffffff
+ min a5, a2, a3
+ assert eq, a5, a4
+
+ movi a2, 1
+ movi a3, 0xffffffff
+ movi a4, 0xffffffff
+ min a5, a2, a3
+ assert eq, a5, a4
+
+ movi a2, 0xffffffff
+ movi a3, 1
+ movi a4, 0xffffffff
+ min a2, a2, a3
+ assert eq, a2, a4
+
+ movi a2, 0xffffffff
+ movi a3, 1
+ movi a4, 0xffffffff
+ min a3, a2, a3
+ assert eq, a3, a4
+
+ movi a2, 1
+ movi a3, 0xffffffff
+ movi a4, 0xffffffff
+ min a2, a2, a3
+ assert eq, a2, a4
+
+ movi a2, 1
+ movi a3, 0xffffffff
+ movi a4, 0xffffffff
+ min a3, a2, a3
+ assert eq, a3, a4
+test_end
+
+test minu
+ movi a2, 0xffffffff
+ movi a3, 1
+ movi a4, 1
+ minu a5, a2, a3
+ assert eq, a5, a4
+
+ movi a2, 1
+ movi a3, 0xffffffff
+ movi a4, 1
+ minu a5, a2, a3
+ assert eq, a5, a4
+
+ movi a2, 0xffffffff
+ movi a3, 1
+ movi a4, 1
+ minu a2, a2, a3
+ assert eq, a2, a4
+
+ movi a2, 0xffffffff
+ movi a3, 1
+ movi a4, 1
+ minu a3, a2, a3
+ assert eq, a3, a4
+
+ movi a2, 1
+ movi a3, 0xffffffff
+ movi a4, 1
+ minu a2, a2, a3
+ assert eq, a2, a4
+
+ movi a2, 1
+ movi a3, 0xffffffff
+ movi a4, 1
+ minu a3, a2, a3
+ assert eq, a3, a4
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_mmu.S b/tests/xtensa/test_mmu.S
new file mode 100644
index 0000000..52d5774
--- /dev/null
+++ b/tests/xtensa/test_mmu.S
@@ -0,0 +1,318 @@
+.include "macros.inc"
+
+test_suite mmu
+
+.purgem test
+
+.macro test name
+ movi a2, 0x00000004
+ idtlb a2
+ movi a2, 0x00100004
+ idtlb a2
+ movi a2, 0x00200004
+ idtlb a2
+ movi a2, 0x00300004
+ idtlb a2
+ movi a2, 0x00000007
+ idtlb a2
+.endm
+
+test tlb_group
+ movi a2, 0x04000002 /* PPN */
+ movi a3, 0x01200004 /* VPN */
+ wdtlb a2, a3
+ witlb a2, a3
+ movi a3, 0x00200004
+ rdtlb0 a1, a3
+ ritlb0 a2, a3
+ movi a3, 0x01000001
+ assert eq, a1, a3
+ assert eq, a2, a3
+ movi a3, 0x00200004
+ rdtlb1 a1, a3
+ ritlb1 a2, a3
+ movi a3, 0x04000002
+ assert eq, a1, a3
+ assert eq, a2, a3
+ movi a3, 0x01234567
+ pdtlb a1, a3
+ pitlb a2, a3
+ movi a3, 0x01234014
+ assert eq, a1, a3
+ movi a3, 0x0123400c
+ assert eq, a2, a3
+ movi a3, 0x00200004
+ idtlb a3
+ iitlb a3
+ movi a3, 0x01234567
+ pdtlb a1, a3
+ pitlb a2, a3
+ movi a3, 0x00000010
+ and a1, a1, a3
+ assert eqi, a1, 0
+ movi a3, 0x00000008
+ and a2, a2, a3
+ assert eqi, a2, 0
+test_end
+
+test itlb_miss
+ set_vector kernel, 1f
+
+ movi a3, 0x00100000
+ jx a3
+ test_fail
+1:
+ rsr a2, excvaddr
+ assert eq, a2, a3
+ rsr a2, exccause
+ movi a3, 16
+ assert eq, a2, a3
+test_end
+
+test dtlb_miss
+ set_vector kernel, 1f
+
+ movi a3, 0x00100000
+ l8ui a2, a3, 0
+ test_fail
+1:
+ rsr a2, excvaddr
+ assert eq, a2, a3
+ rsr a2, exccause
+ movi a3, 24
+ assert eq, a2, a3
+test_end
+
+test itlb_multi_hit
+ set_vector kernel, 1f
+
+ movi a2, 0x04000002 /* PPN */
+ movi a3, 0xf0000004 /* VPN */
+ witlb a2, a3
+ movi a3, 0xf0000000
+ pitlb a2, a3
+ test_fail
+1:
+ rsr a2, exccause
+ movi a3, 17
+ assert eq, a2, a3
+test_end
+
+test dtlb_multi_hit
+ set_vector kernel, 1f
+
+ movi a2, 0x04000002 /* PPN */
+ movi a3, 0x01200004 /* VPN */
+ wdtlb a2, a3
+ movi a3, 0x01200007 /* VPN */
+ wdtlb a2, a3
+ movi a3, 0x01200000
+ pdtlb a2, a3
+ test_fail
+1:
+ rsr a2, exccause
+ movi a3, 25
+ assert eq, a2, a3
+test_end
+
+test inst_fetch_privilege
+ set_vector kernel, 3f
+
+ movi a2, 0x4004f
+ wsr a2, ps
+1:
+ isync
+ nop
+2:
+ test_fail
+3:
+ movi a1, 1b
+ rsr a2, excvaddr
+ rsr a3, epc1
+ assert ge, a2, a1
+ assert ge, a3, a1
+ movi a1, 2b
+ assert lt, a2, a1
+ assert lt, a3, a1
+ rsr a2, exccause
+ movi a3, 18
+ assert eq, a2, a3
+ rsr a2, ps
+ movi a3, 0x4005f
+ assert eq, a2, a3
+test_end
+
+test load_store_privilege
+ set_vector kernel, 2f
+
+ movi a3, 10f
+ pitlb a3, a3
+ ritlb1 a2, a3
+ movi a1, 0x10
+ or a2, a2, a1
+ movi a1, 0x000ff000
+ and a3, a3, a1
+ movi a1, 4
+ or a3, a3, a1
+ witlb a2, a3
+ movi a3, 10f
+ movi a1, 0x000fffff
+ and a1, a3, a1
+
+ movi a2, 0x04000003 /* PPN */
+ movi a3, 0x01200004 /* VPN */
+ wdtlb a2, a3
+ movi a3, 0x01200001
+ movi a2, 0x4004f
+ jx a1
+10:
+ wsr a2, ps
+ isync
+1:
+ l8ui a2, a3, 0
+ test_fail
+2:
+ rsr a2, excvaddr
+ assert eq, a2, a3
+ rsr a2, epc1
+ movi a3, 1b
+ movi a1, 0x000fffff
+ and a3, a3, a1
+ assert eq, a2, a3
+ rsr a2, exccause
+ movi a3, 26
+ assert eq, a2, a3
+ rsr a2, ps
+ movi a3, 0x4005f
+ assert eq, a2, a3
+test_end
+
+test cring_load_store_privilege
+ set_vector kernel, 0
+ set_vector double, 2f
+
+ movi a2, 0x04000003 /* PPN */
+ movi a3, 0x01200004 /* VPN */
+ wdtlb a2, a3
+ movi a3, 0x01200004
+ movi a2, 0x4005f /* ring 1 + excm => cring == 0 */
+ wsr a2, ps
+ isync
+ l8ui a2, a3, 0 /* cring used */
+1:
+ l32e a2, a3, -4 /* ring used */
+ test_fail
+2:
+ rsr a2, excvaddr
+ addi a2, a2, 4
+ assert eq, a2, a3
+ rsr a2, depc
+ movi a3, 1b
+ assert eq, a2, a3
+ rsr a2, exccause
+ movi a3, 26
+ assert eq, a2, a3
+ rsr a2, ps
+ movi a3, 0x4005f
+ assert eq, a2, a3
+test_end
+
+test inst_fetch_prohibited
+ set_vector kernel, 2f
+
+ movi a3, 10f
+ pitlb a3, a3
+ ritlb1 a2, a3
+ movi a1, 0xfffff000
+ and a2, a2, a1
+ movi a1, 0x4
+ or a2, a2, a1
+ movi a1, 0x000ff000
+ and a3, a3, a1
+ movi a1, 4
+ or a3, a3, a1
+ witlb a2, a3
+ movi a3, 10f
+ movi a1, 0x000fffff
+ and a1, a3, a1
+ jx a1
+ .align 4
+10:
+ nop
+ test_fail
+2:
+ rsr a2, excvaddr
+ assert eq, a2, a1
+ rsr a2, epc1
+ assert eq, a2, a1
+ rsr a2, exccause
+ movi a3, 20
+ assert eq, a2, a3
+test_end
+
+test load_prohibited
+ set_vector kernel, 2f
+
+ movi a2, 0x0400000c /* PPN */
+ movi a3, 0x01200004 /* VPN */
+ wdtlb a2, a3
+ movi a3, 0x01200002
+1:
+ l8ui a2, a3, 0
+ test_fail
+2:
+ rsr a2, excvaddr
+ assert eq, a2, a3
+ rsr a2, epc1
+ movi a3, 1b
+ assert eq, a2, a3
+ rsr a2, exccause
+ movi a3, 28
+ assert eq, a2, a3
+test_end
+
+test store_prohibited
+ set_vector kernel, 2f
+
+ movi a2, 0x04000001 /* PPN */
+ movi a3, 0x01200004 /* VPN */
+ wdtlb a2, a3
+ movi a3, 0x01200003
+ l8ui a2, a3, 0
+1:
+ s8i a2, a3, 0
+ test_fail
+2:
+ rsr a2, excvaddr
+ assert eq, a2, a3
+ rsr a2, epc1
+ movi a3, 1b
+ assert eq, a2, a3
+ rsr a2, exccause
+ movi a3, 29
+ assert eq, a2, a3
+test_end
+
+test dtlb_autoload
+ set_vector kernel, 0
+
+ movi a2, 0xd4000000
+ wsr a2, ptevaddr
+ movi a3, 0x00001013
+ s32i a3, a2, 4
+ pdtlb a2, a3
+ movi a1, 0x10
+ and a1, a1, a2
+ assert eqi, a1, 0
+ l8ui a1, a3, 0
+ pdtlb a2, a3
+ movi a1, 0xfffff010
+ and a1, a1, a2
+ movi a3, 0x00001010
+ assert eq, a1, a3
+ movi a1, 0xf
+ and a1, a1, a2
+ assert lti, a1, 4
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_mul16.S b/tests/xtensa/test_mul16.S
new file mode 100644
index 0000000..bf94376
--- /dev/null
+++ b/tests/xtensa/test_mul16.S
@@ -0,0 +1,83 @@
+.include "macros.inc"
+
+test_suite mul16
+
+test mul16u_pp
+ movi a2, 0x137f5a5a
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0x06e180a6
+ mul16u a5, a2, a4
+ assert eq, a5, a6
+ mul16u a2, a2, a4
+ assert eq, a2, a6
+ mul16u a3, a4, a3
+ assert eq, a3, a6
+test_end
+
+test mul16u_np
+ movi a2, 0x137fa5a5
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0x0c9d6bdb
+ mul16u a5, a2, a4
+ assert eq, a5, a6
+ mul16u a2, a2, a4
+ assert eq, a2, a6
+ mul16u a3, a4, a3
+ assert eq, a3, a6
+test_end
+
+test mul16u_nn
+ movi a2, 0x137fa5a5
+ mov a3, a2
+ movi a4, 0xa5a5f731
+ movi a6, 0x9ff1e795
+ mul16u a5, a2, a4
+ assert eq, a5, a6
+ mul16u a2, a2, a4
+ assert eq, a2, a6
+ mul16u a3, a4, a3
+ assert eq, a3, a6
+test_end
+
+test mul16s_pp
+ movi a2, 0x137f5a5a
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0x06e180a6
+ mul16s a5, a2, a4
+ assert eq, a5, a6
+ mul16s a2, a2, a4
+ assert eq, a2, a6
+ mul16s a3, a4, a3
+ assert eq, a3, a6
+test_end
+
+test mul16s_np
+ movi a2, 0x137fa5a5
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0xf91e6bdb
+ mul16s a5, a2, a4
+ assert eq, a5, a6
+ mul16s a2, a2, a4
+ assert eq, a2, a6
+ mul16s a3, a4, a3
+ assert eq, a3, a6
+test_end
+
+test mul16s_nn
+ movi a2, 0x137fa5a5
+ mov a3, a2
+ movi a4, 0xa5a5f731
+ movi a6, 0x031be795
+ mul16s a5, a2, a4
+ assert eq, a5, a6
+ mul16s a2, a2, a4
+ assert eq, a2, a6
+ mul16s a3, a4, a3
+ assert eq, a3, a6
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_mul32.S b/tests/xtensa/test_mul32.S
new file mode 100644
index 0000000..fdaf573
--- /dev/null
+++ b/tests/xtensa/test_mul32.S
@@ -0,0 +1,20 @@
+.include "macros.inc"
+
+test_suite mul32
+
+test mull
+ movi a2, 0x137f5a5a
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0x5de480a6
+ mull a5, a2, a4
+ assert eq, a5, a6
+ mull a2, a2, a4
+ assert eq, a2, a6
+ mull a3, a4, a3
+ assert eq, a3, a6
+test_end
+
+/* unfortunately dc232b doesn't have muluh/mulsh*/
+
+test_suite_end
diff --git a/tests/xtensa/test_nsa.S b/tests/xtensa/test_nsa.S
new file mode 100644
index 0000000..a5fe5de
--- /dev/null
+++ b/tests/xtensa/test_nsa.S
@@ -0,0 +1,59 @@
+.include "macros.inc"
+
+test_suite nsa
+
+test nsa
+ movi a2, 0
+ movi a3, 31
+ nsa a4, a2
+ assert eq, a3, a4
+
+ movi a2, 0xffffffff
+ movi a3, 31
+ nsa a4, a2
+ assert eq, a3, a4
+
+ movi a2, 1
+ movi a3, 30
+ nsa a2, a2
+ assert eq, a3, a2
+
+ movi a2, 0xfffffffe
+ movi a3, 30
+ nsa a2, a2
+ assert eq, a3, a2
+
+ movi a2, 0x5a5a5a5a
+ movi a3, 0
+ nsa a4, a2
+ assert eq, a3, a4
+
+ movi a2, 0xa5a5a5a5
+ movi a3, 0
+ nsa a4, a2
+ assert eq, a3, a4
+test_end
+
+test nsau
+ movi a2, 0
+ movi a3, 32
+ nsau a4, a2
+ assert eq, a3, a4
+
+ movi a2, 0xffffffff
+ movi a3, 0
+ nsau a4, a2
+ assert eq, a3, a4
+
+ movi a2, 1
+ movi a3, 31
+ nsau a2, a2
+ assert eq, a3, a2
+
+ movi a2, 0x5a5a5a5a
+ movi a3, 1
+ nsau a2, a2
+ assert eq, a3, a2
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_pipeline.S b/tests/xtensa/test_pipeline.S
new file mode 100644
index 0000000..6be6085
--- /dev/null
+++ b/tests/xtensa/test_pipeline.S
@@ -0,0 +1,157 @@
+.include "macros.inc"
+
+.purgem test
+.macro test name
+ movi a2, 1f
+ movi a3, 99f
+0:
+ ipf a2, 0
+ ipf a2, 4
+ ipf a2, 8
+ ipf a2, 12
+ addi a2, a2, 16
+ blt a2, a3, 0b
+ j 1f
+ .align 4
+1:
+.endm
+
+test_suite pipeline
+
+test register_no_stall
+ rsr a3, ccount
+ add a5, a6, a6
+ add a6, a5, a5
+ rsr a4, ccount
+ sub a3, a4, a3
+ assert eqi, a3, 3
+test_end
+
+test register_stall
+ l32i a5, a1, 0 /* data cache preload */
+ nop
+ rsr a3, ccount
+ l32i a5, a1, 0
+ add a6, a5, a5 /* M-to-E interlock */
+ rsr a4, ccount
+ sub a3, a4, a3
+ assert eqi, a3, 4
+test_end
+
+test j0_stall
+ rsr a3, ccount
+ j 1f /* E + 2-cycle penalty */
+1:
+ rsr a4, ccount /* E */
+ sub a3, a4, a3
+ assert eqi, a3, 4
+test_end
+
+test j1_stall
+ rsr a3, ccount
+ j 1f
+ nop
+1:
+ rsr a4, ccount
+ sub a3, a4, a3
+ assert eqi, a3, 4
+test_end
+
+test j5_stall
+ rsr a3, ccount
+ j 1f
+ nop
+ nop
+ nop
+ nop
+ nop
+1:
+ rsr a4, ccount
+ sub a3, a4, a3
+ assert eqi, a3, 4
+test_end
+
+test b_no_stall
+ movi a5, 1
+ rsr a3, ccount
+ beqi a5, 2, 1f
+ rsr a4, ccount
+ sub a3, a4, a3
+ assert eqi, a3, 2
+1:
+test_end
+
+test b1_stall
+ movi a5, 1
+ rsr a3, ccount
+ beqi a5, 1, 1f
+ nop
+1:
+ rsr a4, ccount
+ sub a3, a4, a3
+ assert eqi, a3, 4
+test_end
+
+test b5_stall
+ movi a5, 1
+ rsr a3, ccount
+ beqi a5, 1, 1f
+ nop
+ nop
+ nop
+ nop
+ nop
+1:
+ rsr a4, ccount
+ sub a3, a4, a3
+ assert eqi, a3, 4
+test_end
+
+/* PS *SYNC */
+
+test ps_dsync
+ rsr a5, ps
+ isync
+ rsr a3, ccount
+ wsr a5, ps
+ dsync
+ rsr a4, ccount
+ sub a3, a4, a3
+ assert eqi, a3, 5
+test_end
+
+test ps_esync
+ rsr a5, ps
+ isync
+ rsr a3, ccount
+ wsr a5, ps
+ esync
+ rsr a4, ccount
+ sub a3, a4, a3
+ assert eqi, a3, 5
+test_end
+
+test ps_rsync
+ rsr a5, ps
+ isync
+ rsr a3, ccount
+ wsr a5, ps
+ rsync
+ rsr a4, ccount
+ sub a3, a4, a3
+ assert eqi, a3, 5
+test_end
+
+test ps_isync
+ rsr a5, ps
+ isync
+ rsr a3, ccount
+ wsr a5, ps
+ isync
+ rsr a4, ccount
+ sub a3, a4, a3
+ movi a4, 9
+ assert eq, a3, a4
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_quo.S b/tests/xtensa/test_quo.S
new file mode 100644
index 0000000..12debf1
--- /dev/null
+++ b/tests/xtensa/test_quo.S
@@ -0,0 +1,147 @@
+.include "macros.inc"
+
+test_suite quo
+
+test quou_pp
+ movi a2, 0x5a5a137f
+ mov a3, a2
+ movi a4, 0x137f5a5a
+ movi a6, 0x4
+ quou a5, a2, a4
+ assert eq, a5, a6
+ quou a2, a2, a4
+ assert eq, a2, a6
+ quou a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test quou_np
+ movi a2, 0xa5a5137f
+ mov a3, a2
+ movi a4, 0x137f5a5a
+ movi a6, 0x8
+ quou a5, a2, a4
+ assert eq, a5, a6
+ quou a2, a2, a4
+ assert eq, a2, a6
+ quou a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test quou_pn
+ movi a2, 0x5a5a137f
+ mov a3, a2
+ movi a4, 0xf7315a5a
+ movi a6, 0
+ quou a5, a2, a4
+ assert eq, a5, a6
+ quou a2, a2, a4
+ assert eq, a2, a6
+ quou a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test quou_nn
+ movi a2, 0xf7315a5a
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0x1
+ quou a5, a2, a4
+ assert eq, a5, a6
+ quou a2, a2, a4
+ assert eq, a2, a6
+ quou a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test quou_exc
+ set_vector kernel, 2f
+ movi a2, 0xf7315a5a
+ movi a4, 0x00000000
+1:
+ quou a5, a2, a4
+ test_fail
+2:
+ rsr a2, exccause
+ assert eqi, a2, 6 /* INTEGER_DIVIDE_BY_ZERO_CAUSE */
+ rsr a2, epc1
+ movi a3, 1b
+ assert eq, a2, a3
+test_end
+
+test quos_pp
+ movi a2, 0x5a5a137f
+ mov a3, a2
+ movi a4, 0x137f5a5a
+ movi a6, 0x4
+ quos a5, a2, a4
+ assert eq, a5, a6
+ quos a2, a2, a4
+ assert eq, a2, a6
+ quos a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test quos_np
+ movi a2, 0xa5a5137f
+ mov a3, a2
+ movi a4, 0x137f5a5a
+ movi a6, 0xfffffffc
+ quos a5, a2, a4
+ assert eq, a5, a6
+ quos a2, a2, a4
+ assert eq, a2, a6
+ quos a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test quos_pn
+ movi a2, 0x5a5a137f
+ mov a3, a2
+ movi a4, 0xf7315a5a
+ movi a6, 0xfffffff6
+ quos a5, a2, a4
+ assert eq, a5, a6
+ quos a2, a2, a4
+ assert eq, a2, a6
+ quos a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test quos_nn
+ movi a2, 0xf7315a5a
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0
+ quos a5, a2, a4
+ assert eq, a5, a6
+ quos a2, a2, a4
+ assert eq, a2, a6
+ quos a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test quos_over
+ movi a2, 0x80000000
+ movi a4, 0xffffffff
+ movi a6, 0x80000000
+ quos a5, a2, a4
+ assert eq, a5, a6
+test_end
+
+test quos_exc
+ set_vector kernel, 2f
+ movi a2, 0xf7315a5a
+ movi a4, 0x00000000
+1:
+ quos a5, a2, a4
+ test_fail
+2:
+ rsr a2, exccause
+ assert eqi, a2, 6 /* INTEGER_DIVIDE_BY_ZERO_CAUSE */
+ rsr a2, epc1
+ movi a3, 1b
+ assert eq, a2, a3
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_rem.S b/tests/xtensa/test_rem.S
new file mode 100644
index 0000000..bb0d5fe
--- /dev/null
+++ b/tests/xtensa/test_rem.S
@@ -0,0 +1,147 @@
+.include "macros.inc"
+
+test_suite rem
+
+test remu_pp
+ movi a2, 0x5a5a137f
+ mov a3, a2
+ movi a4, 0x137f5a5a
+ movi a6, 0x0c5caa17
+ remu a5, a2, a4
+ assert eq, a5, a6
+ remu a2, a2, a4
+ assert eq, a2, a6
+ remu a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test remu_np
+ movi a2, 0xa5a5137f
+ mov a3, a2
+ movi a4, 0x137f5a5a
+ movi a6, 0x9aa40af
+ remu a5, a2, a4
+ assert eq, a5, a6
+ remu a2, a2, a4
+ assert eq, a2, a6
+ remu a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test remu_pn
+ movi a2, 0x5a5a137f
+ mov a3, a2
+ movi a4, 0xf7315a5a
+ movi a6, 0x5a5a137f
+ remu a5, a2, a4
+ assert eq, a5, a6
+ remu a2, a2, a4
+ assert eq, a2, a6
+ remu a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test remu_nn
+ movi a2, 0xf7315a5a
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0x518c46db
+ remu a5, a2, a4
+ assert eq, a5, a6
+ remu a2, a2, a4
+ assert eq, a2, a6
+ remu a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test remu_exc
+ set_vector kernel, 2f
+ movi a2, 0xf7315a5a
+ movi a4, 0x00000000
+1:
+ remu a5, a2, a4
+ test_fail
+2:
+ rsr a2, exccause
+ assert eqi, a2, 6 /* INTEGER_DIVIDE_BY_ZERO_CAUSE */
+ rsr a2, epc1
+ movi a3, 1b
+ assert eq, a2, a3
+test_end
+
+test rems_pp
+ movi a2, 0x5a5a137f
+ mov a3, a2
+ movi a4, 0x137f5a5a
+ movi a6, 0x0c5caa17
+ rems a5, a2, a4
+ assert eq, a5, a6
+ rems a2, a2, a4
+ assert eq, a2, a6
+ rems a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test rems_np
+ movi a2, 0xa5a5137f
+ mov a3, a2
+ movi a4, 0x137f5a5a
+ movi a6, 0xf3a27ce7
+ rems a5, a2, a4
+ assert eq, a5, a6
+ rems a2, a2, a4
+ assert eq, a2, a6
+ rems a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test rems_pn
+ movi a2, 0x5a5a137f
+ mov a3, a2
+ movi a4, 0xf7315a5a
+ movi a6, 0x02479b03
+ rems a5, a2, a4
+ assert eq, a5, a6
+ rems a2, a2, a4
+ assert eq, a2, a6
+ rems a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test rems_nn
+ movi a2, 0xf7315a5a
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0xf7315a5a
+ rems a5, a2, a4
+ assert eq, a5, a6
+ rems a2, a2, a4
+ assert eq, a2, a6
+ rems a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test rems_over
+ movi a2, 0x80000000
+ movi a4, 0xffffffff
+ movi a6, 0
+ rems a5, a2, a4
+ assert eq, a5, a6
+test_end
+
+test rems_exc
+ set_vector kernel, 2f
+ movi a2, 0xf7315a5a
+ movi a4, 0x00000000
+1:
+ rems a5, a2, a4
+ test_fail
+2:
+ rsr a2, exccause
+ assert eqi, a2, 6 /* INTEGER_DIVIDE_BY_ZERO_CAUSE */
+ rsr a2, epc1
+ movi a3, 1b
+ assert eq, a2, a3
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_rst0.S b/tests/xtensa/test_rst0.S
new file mode 100644
index 0000000..3eda565
--- /dev/null
+++ b/tests/xtensa/test_rst0.S
@@ -0,0 +1,148 @@
+.include "macros.inc"
+
+test_suite rst0
+
+test and
+ movi a2, 0x137fa5a5
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0x01250125
+ and a5, a2, a4
+ assert eq, a5, a6
+ and a2, a2, a4
+ assert eq, a2, a6
+ and a3, a4, a3
+ assert eq, a3, a6
+test_end
+
+test or
+ movi a2, 0x137fa5a5
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0xb7ffb7ff
+ or a5, a2, a4
+ assert eq, a5, a6
+ or a2, a2, a4
+ assert eq, a2, a6
+ or a3, a4, a3
+ assert eq, a3, a6
+test_end
+
+test xor
+ movi a2, 0x137fa5a5
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0xb6dab6da
+ xor a5, a2, a4
+ assert eq, a5, a6
+ xor a2, a2, a4
+ assert eq, a2, a6
+ xor a3, a4, a3
+ assert eq, a3, a6
+test_end
+
+test add
+ movi a2, 0x137fa5a5
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0xb924b924
+ add a5, a2, a4
+ assert eq, a5, a6
+ add a2, a2, a4
+ assert eq, a2, a6
+ add a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test addx2
+ movi a2, 0x137fa5a5
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0xcca45ec9
+ addx2 a5, a2, a4
+ assert eq, a5, a6
+ addx2 a2, a2, a4
+ assert eq, a2, a6
+ addx2 a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test addx4
+ movi a2, 0x137fa5a5
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0xf3a3aa13
+ addx4 a5, a2, a4
+ assert eq, a5, a6
+ addx4 a2, a2, a4
+ assert eq, a2, a6
+ addx4 a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test addx8
+ movi a2, 0x137fa5a5
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0x41a240a7
+ addx8 a5, a2, a4
+ assert eq, a5, a6
+ addx8 a2, a2, a4
+ assert eq, a2, a6
+ addx8 a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test sub
+ movi a2, 0x137fa5a5
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0x6dda9226
+ sub a5, a2, a4
+ assert eq, a5, a6
+ sub a2, a2, a4
+ assert eq, a2, a6
+ sub a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test subx2
+ movi a2, 0x137fa5a5
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0x815a37cb
+ subx2 a5, a2, a4
+ assert eq, a5, a6
+ subx2 a2, a2, a4
+ assert eq, a2, a6
+ subx2 a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test subx4
+ movi a2, 0x137fa5a5
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0xa8598315
+ subx4 a5, a2, a4
+ assert eq, a5, a6
+ subx4 a2, a2, a4
+ assert eq, a2, a6
+ subx4 a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test subx8
+ movi a2, 0x137fa5a5
+ mov a3, a2
+ movi a4, 0xa5a5137f
+ movi a6, 0xf65819a9
+ subx8 a5, a2, a4
+ assert eq, a5, a6
+ subx8 a2, a2, a4
+ assert eq, a2, a6
+ subx8 a4, a3, a4
+ assert eq, a4, a6
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_sar.S b/tests/xtensa/test_sar.S
new file mode 100644
index 0000000..40c649f
--- /dev/null
+++ b/tests/xtensa/test_sar.S
@@ -0,0 +1,111 @@
+.include "macros.inc"
+
+test_suite sar
+
+.macro test_sar prefix, imm
+ \prefix\()_set \imm
+ \prefix\()_ver \imm
+.endm
+
+.macro tests_sar prefix
+ test_sar \prefix, 0
+ test_sar \prefix, 1
+ test_sar \prefix, 2
+ test_sar \prefix, 3
+ test_sar \prefix, 0x1f
+ test_sar \prefix, 0x20
+ test_sar \prefix, 0x3f
+ test_sar \prefix, 0x40
+ test_sar \prefix, 0xfffffffe
+.endm
+
+.macro sar_set imm
+ movi a2, \imm
+ wsr a2, sar
+.endm
+
+.macro sar_ver imm
+ rsr a3, sar
+ movi a2, \imm & 0x3f
+ assert eq, a2, a3
+.endm
+
+test sar
+ tests_sar sar
+test_end
+
+.macro ssr_set imm
+ movi a2, \imm
+ ssr a2
+.endm
+
+.macro ssr_ver imm
+ rsr a3, sar
+ movi a2, \imm & 0x1f
+ assert eq, a2, a3
+.endm
+
+test ssr
+ tests_sar ssr
+test_end
+
+.macro ssl_set imm
+ movi a2, \imm
+ ssl a2
+.endm
+
+.macro ssl_ver imm
+ rsr a3, sar
+ movi a2, 32 - (\imm & 0x1f)
+ assert eq, a2, a3
+.endm
+
+test ssl
+ tests_sar ssl
+test_end
+
+.macro ssa8l_set imm
+ movi a2, \imm
+ ssa8l a2
+.endm
+
+.macro ssa8l_ver imm
+ rsr a3, sar
+ movi a2, (\imm & 0x3) << 3
+ assert eq, a2, a3
+.endm
+
+test ssa8l
+ tests_sar ssa8l
+test_end
+
+.macro ssa8b_set imm
+ movi a2, \imm
+ ssa8b a2
+.endm
+
+.macro ssa8b_ver imm
+ rsr a3, sar
+ movi a2, 32 - ((\imm & 0x3) << 3)
+ assert eq, a2, a3
+.endm
+
+test ssa8b
+ tests_sar ssa8b
+test_end
+
+.macro ssai_set imm
+ ssai \imm & 0x1f
+.endm
+
+.macro ssai_ver imm
+ rsr a3, sar
+ movi a2, \imm & 0x1f
+ assert eq, a2, a3
+.endm
+
+test ssai
+ tests_sar ssai
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_sext.S b/tests/xtensa/test_sext.S
new file mode 100644
index 0000000..04dc650
--- /dev/null
+++ b/tests/xtensa/test_sext.S
@@ -0,0 +1,69 @@
+.include "macros.inc"
+
+test_suite sext
+
+test sext
+ movi a2, 0xffffff5a
+ movi a3, 0x0000005a
+ sext a4, a2, 7
+ assert eq, a3, a4
+
+ movi a2, 0x000000a5
+ movi a3, 0xffffffa5
+ sext a4, a2, 7
+ assert eq, a3, a4
+
+ movi a2, 0xfffffaa5
+ movi a3, 0x000000a5
+ sext a4, a2, 8
+ assert eq, a3, a4
+
+ movi a2, 0x0000055a
+ movi a3, 0xffffff5a
+ sext a4, a2, 8
+ assert eq, a3, a4
+
+ movi a2, 0xffff5a5a
+ movi a3, 0x00005a5a
+ sext a4, a2, 15
+ assert eq, a3, a4
+
+ movi a2, 0x0000a5a5
+ movi a3, 0xffffa5a5
+ sext a4, a2, 15
+ assert eq, a3, a4
+
+ movi a2, 0x00055a5a
+ movi a3, 0xffff5a5a
+ sext a4, a2, 16
+ assert eq, a3, a4
+
+ movi a2, 0x000aa5a5
+ movi a3, 0x0000a5a5
+ sext a4, a2, 16
+ assert eq, a3, a4
+
+ movi a2, 0x005a5a5a
+ movi a3, 0xffda5a5a
+ sext a4, a2, 22
+ assert eq, a3, a4
+
+ movi a2, 0xffa5a5a5
+ movi a3, 0x0025a5a5
+ sext a4, a2, 22
+ assert eq, a3, a4
+test_end
+
+test sext_same_rs
+ movi a2, 0xffffff5a
+ movi a3, 0x0000005a
+ sext a2, a2, 7
+ assert eq, a3, a2
+
+ movi a2, 0x000000a5
+ movi a3, 0xffffffa5
+ sext a2, a2, 7
+ assert eq, a3, a2
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_shift.S b/tests/xtensa/test_shift.S
new file mode 100644
index 0000000..a8e4364
--- /dev/null
+++ b/tests/xtensa/test_shift.S
@@ -0,0 +1,206 @@
+.include "macros.inc"
+
+test_suite shift
+
+.macro test_shift prefix, dst, src, v, imm
+ \prefix\()_set \dst, \src, \v, \imm
+ \prefix\()_ver \dst, \v, \imm
+.endm
+
+.macro test_shift_sd prefix, v, imm
+ test_shift \prefix, a3, a2, \v, \imm
+ test_shift \prefix, a2, a2, \v, \imm
+.endm
+
+.macro tests_imm_shift prefix, v
+ test_shift_sd \prefix, \v, 1
+ test_shift_sd \prefix, \v, 2
+ test_shift_sd \prefix, \v, 7
+ test_shift_sd \prefix, \v, 8
+ test_shift_sd \prefix, \v, 15
+ test_shift_sd \prefix, \v, 16
+ test_shift_sd \prefix, \v, 31
+.endm
+
+.macro tests_shift prefix, v
+ test_shift_sd \prefix, \v, 0
+ tests_imm_shift \prefix, \v
+ test_shift_sd \prefix, \v, 32
+.endm
+
+
+.macro slli_set dst, src, v, imm
+ movi \src, \v
+ slli \dst, \src, \imm
+.endm
+
+.macro slli_ver dst, v, imm
+ mov a2, \dst
+ movi a3, ((\v) << (\imm)) & 0xffffffff
+ assert eq, a2, a3
+.endm
+
+test slli
+ tests_imm_shift slli, 0xa3c51249
+test_end
+
+
+.macro srai_set dst, src, v, imm
+ movi \src, \v
+ srai \dst, \src, \imm
+.endm
+
+.macro srai_ver dst, v, imm
+ mov a2, \dst
+ .if (\imm)
+ movi a3, (((\v) >> (\imm)) & 0xffffffff) | \
+ ~((((\v) & 0x80000000) >> ((\imm) - 1)) - 1)
+ .else
+ movi a3, \v
+ .endif
+ assert eq, a2, a3
+.endm
+
+test srai
+ tests_imm_shift srai, 0x49a3c512
+ tests_imm_shift srai, 0xa3c51249
+test_end
+
+
+.macro srli_set dst, src, v, imm
+ movi \src, \v
+ srli \dst, \src, \imm
+.endm
+
+.macro srli_ver dst, v, imm
+ mov a2, \dst
+ movi a3, (((\v) >> (\imm)) & 0xffffffff)
+ assert eq, a2, a3
+.endm
+
+test srli
+ tests_imm_shift srli, 0x49a3c512
+ tests_imm_shift srli, 0xa3c51249
+test_end
+
+
+.macro sll_set dst, src, v, imm
+ movi a2, \imm
+ ssl a2
+ movi \src, \v
+ sll \dst, \src
+.endm
+
+.macro sll_sar_set dst, src, v, imm
+ movi a2, 32 - \imm
+ wsr a2, sar
+ movi \src, \v
+ sll \dst, \src
+.endm
+
+.macro sll_ver dst, v, imm
+ slli_ver \dst, \v, (\imm) & 0x1f
+.endm
+
+.macro sll_sar_ver dst, v, imm
+ slli_ver \dst, \v, \imm
+.endm
+
+test sll
+ tests_shift sll, 0xa3c51249
+ tests_shift sll_sar, 0xa3c51249
+test_end
+
+
+.macro srl_set dst, src, v, imm
+ movi a2, \imm
+ ssr a2
+ movi \src, \v
+ srl \dst, \src
+.endm
+
+.macro srl_sar_set dst, src, v, imm
+ movi a2, \imm
+ wsr a2, sar
+ movi \src, \v
+ srl \dst, \src
+.endm
+
+.macro srl_ver dst, v, imm
+ srli_ver \dst, \v, (\imm) & 0x1f
+.endm
+
+.macro srl_sar_ver dst, v, imm
+ srli_ver \dst, \v, \imm
+.endm
+
+test srl
+ tests_shift srl, 0xa3c51249
+ tests_shift srl_sar, 0xa3c51249
+ tests_shift srl, 0x49a3c512
+ tests_shift srl_sar, 0x49a3c512
+test_end
+
+
+.macro sra_set dst, src, v, imm
+ movi a2, \imm
+ ssr a2
+ movi \src, \v
+ sra \dst, \src
+.endm
+
+.macro sra_sar_set dst, src, v, imm
+ movi a2, \imm
+ wsr a2, sar
+ movi \src, \v
+ sra \dst, \src
+.endm
+
+.macro sra_ver dst, v, imm
+ srai_ver \dst, \v, (\imm) & 0x1f
+.endm
+
+.macro sra_sar_ver dst, v, imm
+ srai_ver \dst, \v, \imm
+.endm
+
+test sra
+ tests_shift sra, 0xa3c51249
+ tests_shift sra_sar, 0xa3c51249
+ tests_shift sra, 0x49a3c512
+ tests_shift sra_sar, 0x49a3c512
+test_end
+
+
+.macro src_set dst, src, v, imm
+ movi a2, \imm
+ ssr a2
+ movi \src, (\v) & 0xffffffff
+ movi a4, (\v) >> 32
+ src \dst, a4, \src
+.endm
+
+.macro src_sar_set dst, src, v, imm
+ movi a2, \imm
+ wsr a2, sar
+ movi \src, (\v) & 0xffffffff
+ movi a4, (\v) >> 32
+ src \dst, a4, \src
+.endm
+
+.macro src_ver dst, v, imm
+ src_sar_ver \dst, \v, (\imm) & 0x1f
+.endm
+
+.macro src_sar_ver dst, v, imm
+ mov a2, \dst
+ movi a3, ((\v) >> (\imm)) & 0xffffffff
+ assert eq, a2, a3
+.endm
+
+test src
+ tests_shift src, 0xa3c51249215c3a94
+ tests_shift src_sar, 0xa3c51249215c3a94
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_timer.S b/tests/xtensa/test_timer.S
new file mode 100644
index 0000000..ede6395
--- /dev/null
+++ b/tests/xtensa/test_timer.S
@@ -0,0 +1,115 @@
+.include "macros.inc"
+
+test_suite timer
+
+test ccount
+ rsr a3, ccount
+ rsr a4, ccount
+ sub a3, a4, a3
+ assert eqi, a3, 1
+test_end
+
+test ccompare
+ movi a2, 0
+ wsr a2, intenable
+ rsr a2, interrupt
+ wsr a2, intclear
+ wsr a2, ccompare1
+ wsr a2, ccompare2
+
+ movi a3, 20
+ rsr a2, ccount
+ addi a2, a2, 20
+ wsr a2, ccompare0
+ rsr a2, interrupt
+ assert eqi, a2, 0
+ loop a3, 1f
+ rsr a3, interrupt
+ bnez a3, 2f
+1:
+ test_fail
+2:
+test_end
+
+test ccompare0_interrupt
+ set_vector kernel, 2f
+ movi a2, 0
+ wsr a2, intenable
+ rsr a2, interrupt
+ wsr a2, intclear
+ wsr a2, ccompare1
+ wsr a2, ccompare2
+
+ movi a3, 20
+ rsr a2, ccount
+ addi a2, a2, 20
+ wsr a2, ccompare0
+ rsync
+ rsr a2, interrupt
+ assert eqi, a2, 0
+
+ movi a2, 0x40
+ wsr a2, intenable
+ rsil a2, 0
+ loop a3, 1f
+ nop
+1:
+ test_fail
+2:
+ rsr a2, exccause
+ assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
+test_end
+
+test ccompare1_interrupt
+ set_vector level3, 2f
+ movi a2, 0
+ wsr a2, intenable
+ rsr a2, interrupt
+ wsr a2, intclear
+ wsr a2, ccompare0
+ wsr a2, ccompare2
+
+ movi a3, 20
+ rsr a2, ccount
+ addi a2, a2, 20
+ wsr a2, ccompare1
+ rsync
+ rsr a2, interrupt
+ assert eqi, a2, 0
+ movi a2, 0x400
+ wsr a2, intenable
+ rsil a2, 2
+ loop a3, 1f
+ nop
+1:
+ test_fail
+2:
+test_end
+
+test ccompare2_interrupt
+ set_vector level5, 2f
+ movi a2, 0
+ wsr a2, intenable
+ rsr a2, interrupt
+ wsr a2, intclear
+ wsr a2, ccompare0
+ wsr a2, ccompare1
+
+ movi a3, 20
+ rsr a2, ccount
+ addi a2, a2, 20
+ wsr a2, ccompare2
+ rsync
+ rsr a2, interrupt
+ assert eqi, a2, 0
+ movi a2, 0x2000
+ wsr a2, intenable
+ rsil a2, 4
+ loop a3, 1f
+ nop
+1:
+ test_fail
+2:
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/test_windowed.S b/tests/xtensa/test_windowed.S
new file mode 100644
index 0000000..cb2d39e
--- /dev/null
+++ b/tests/xtensa/test_windowed.S
@@ -0,0 +1,302 @@
+.include "macros.inc"
+
+test_suite windowed
+
+.altmacro
+
+.macro reset_window start
+ movi a2, 0xff
+ wsr a2, windowstart
+ rsync
+ movi a2, 0
+ wsr a2, windowbase
+ rsync
+ movi a2, \start
+ wsr a2, windowstart
+ rsync
+.endm
+
+.macro overflow_test shift, window, probe_ok, probe_ex
+ set_vector window_overflow_4, 0
+ set_vector window_overflow_8, 0
+ set_vector window_overflow_12, 0
+
+ movi a2, 1 | (((1 << ((\window) / 4)) | 1) << ((\shift) / 4))
+ wsr a2, windowstart
+ reset_ps
+
+ mov a2, a\probe_ok
+ set_vector window_overflow_\window, 10f
+1:
+ mov a2, a\probe_ex
+ test_fail
+10:
+ rsr a2, epc1
+ movi a3, 1b
+ assert eq, a2, a3
+ movi a2, 2f
+ wsr a2, epc1
+
+ rsr a2, windowbase
+ movi a3, (\shift) / 4
+ assert eq, a2, a3
+ rsr a2, ps
+ movi a3, 0x4001f
+ assert eq, a2, a3
+ rfwo
+ test_fail
+2:
+ rsr a2, windowbase
+ assert eqi, a2, 0
+ rsr a2, windowstart
+ movi a3, 1 | ((1 << ((\window) / 4)) << ((\shift) / 4))
+ assert eq, a2, a3
+ rsr a2, ps
+ movi a3, 0x4000f
+ assert eq, a2, a3
+.endm
+
+.macro overflow_tests shift, window, probe
+ .if \probe < 15
+ overflow_test \shift, \window, %((\shift) - 1), \probe
+ overflow_tests \shift, \window, %((\probe) + 1)
+ .endif
+.endm
+
+.macro all_overflow_tests
+ .irp shift, 4, 8, 12
+ .irp window, 4, 8, 12
+ overflow_tests \shift, \window, \shift
+ .endr
+ .endr
+.endm
+
+test overflow
+ all_overflow_tests
+test_end
+
+
+.macro underflow_test window
+ set_vector window_underflow_4, 0
+ set_vector window_underflow_8, 0
+ set_vector window_underflow_12, 0
+
+ set_vector window_underflow_\window, 10f
+
+ reset_window 1
+ reset_ps
+
+ ssai 2
+ movi a2, 2f
+ slli a2, a2, 2
+ movi a3, (\window) / 4
+ src a0, a3, a2
+1:
+ retw
+ test_fail
+10:
+ rsr a2, epc1
+ movi a3, 1b
+ assert eq, a2, a3
+ movi a2, 2f
+ wsr a2, epc1
+
+ rsr a2, ps
+ movi a3, 0x4001f
+ assert eq, a2, a3
+ rsr a2, windowbase
+ assert eqi, a2, 8 - ((\window) / 4)
+ rsr a2, windowstart
+ assert eqi, a2, 1
+ rfwu
+2:
+ rsr a2, ps
+ movi a3, 0x4000f
+ assert eq, a2, a3
+ rsr a2, windowbase
+ assert eqi, a2, 0
+ rsr a2, windowstart
+ assert bsi, a2, 0
+ assert bsi, a2, 8 - ((\window) / 4)
+.endm
+
+test underflow
+ set_vector window_overflow_4, 0
+ set_vector window_overflow_8, 0
+ set_vector window_overflow_12, 0
+
+ underflow_test 4
+ underflow_test 8
+ underflow_test 12
+test_end
+
+
+.macro retw_test window
+ reset_window %(1 | (1 << (8 - (\window) / 4)))
+ reset_ps
+
+ ssai 2
+ movi a2, 1f
+ slli a2, a2, 2
+ movi a3, (\window) / 4
+ src a0, a3, a2
+ retw
+ test_fail
+1:
+ rsr a2, ps
+ movi a3, 0x4000f
+ assert eq, a2, a3
+ rsr a2, windowbase
+ assert eqi, a2, 8 - ((\window) / 4)
+ rsr a2, windowstart
+ assert bci, a2, 0
+ assert bsi, a2, 8 - ((\window) / 4)
+.endm
+
+test retw
+ set_vector window_underflow_4, 0
+ set_vector window_underflow_8, 0
+ set_vector window_underflow_12, 0
+
+ retw_test 4
+ retw_test 8
+ retw_test 12
+test_end
+
+test movsp
+ set_vector kernel, 2f
+
+ reset_window 1
+ reset_ps
+1:
+ movsp a2, a3
+ test_fail
+2:
+ rsr a2, exccause
+ assert eqi, a2, 5
+ rsr a2, epc1
+ movi a3, 1b
+ assert eq, a2, a3
+
+ set_vector kernel, 0
+
+ reset_window 0x81
+ reset_ps
+
+ movsp a2, a3
+test_end
+
+test rotw
+ reset_window 0x4b
+ reset_ps
+
+ movi a3, 0x10
+
+ rotw 1
+ rsr a2, windowbase
+ assert eqi, a2, 1
+ movi a3, 0x11
+ movi a7, 0x12
+
+ rotw 2
+ rsr a2, windowbase
+ assert eqi, a2, 3
+ movi a3, 0x13
+ movi a7, 0x14
+ movi a11, 0x15
+
+ rotw 3
+ rsr a2, windowbase
+ assert eqi, a2, 6
+ movi a3, 0x16
+ movi a7, 0x17
+
+ movi a2, 0x44
+ wsr a2, windowstart
+ rsync
+
+ movi a2, 0x10
+ assert eq, a2, a11
+ movi a11, 0x18
+ movi a2, 0x11
+ assert eq, a2, a15
+ movi a15, 0x19
+
+ rotw 4
+ movi a2, 0x12
+ assert eq, a2, a3
+ movi a2, 0x13
+ assert eq, a2, a7
+ movi a2, 0x14
+ assert eq, a2, a11
+ movi a2, 0x15
+ assert eq, a2, a15
+
+ movi a2, 0x5
+ wsr a2, windowstart
+ rsync
+
+ rotw -2
+ movi a2, 0x18
+ assert eq, a2, a3
+ movi a2, 0x19
+ assert eq, a2, a7
+test_end
+
+.macro callw_test window
+ call\window 2f
+1:
+ test_fail
+ .align 4
+2:
+ rsr a2, windowbase
+ assert eqi, a2, 0
+ rsr a2, ps
+ movi a3, 0x4000f | ((\window) << 14)
+ assert eq, a2, a3
+ movi a2, 1b
+ slli a2, a2, 2
+ ssai 2
+ movi a3, (\window) / 4
+ src a2, a3, a2
+ assert eq, a2, a\window
+.endm
+
+test callw
+ reset_window 0x1
+ reset_ps
+
+ callw_test 4
+ callw_test 8
+ callw_test 12
+test_end
+
+
+.macro entry_test window
+ reset_window 0x1
+ reset_ps
+ movi a2, 0x4000f | ((\window) << 14)
+ wsr a2, ps
+ isync
+ movi a3, 0x12345678
+ j 1f
+ .align 4
+1:
+ entry a3, 0x5678
+ movi a2, 0x12340000
+ assert eq, a2, a3
+ rsr a2, windowbase
+ assert eqi, a2, (\window) / 4
+ rsr a2, windowstart
+ movi a3, 1 | (1 << ((\window) / 4))
+ assert eq, a2, a3
+ rotw -(\window) / 4
+.endm
+
+test entry
+ entry_test 4
+ entry_test 8
+ entry_test 12
+test_end
+
+test_suite_end
diff --git a/tests/xtensa/vectors.S b/tests/xtensa/vectors.S
new file mode 100644
index 0000000..265a181
--- /dev/null
+++ b/tests/xtensa/vectors.S
@@ -0,0 +1,39 @@
+.macro vector name
+
+.section .vector.\name
+ j 1f
+.section .vector.\name\().text
+1:
+ wsr a2, excsave1
+ movi a2, handler_\name
+ l32i a2, a2, 0
+ beqz a2, 1f
+ jx a2
+1:
+ movi a3, 1b
+ movi a2, 1
+ simcall
+
+.align 4
+.global handler_\name
+handler_\name\(): .word 0
+
+.endm
+
+vector window_overflow_4
+vector window_overflow_8
+vector window_overflow_12
+vector window_underflow_4
+vector window_underflow_8
+vector window_underflow_12
+
+vector level2
+vector level3
+vector level4
+vector level5
+vector level6
+vector level7
+
+vector kernel
+vector user
+vector double
