)]}'
{
  "commit": "7ce9760d64e8a884f044f95a1f32f96c2e0fafa0",
  "tree": "70d5d523103919afac5341adc8c63e1792e587da",
  "parents": [
    "453ba4f675f751fe4dceaff57ac1ebf72f28f6d0"
  ],
  "author": {
    "name": "Philippe Mathieu-Daudé",
    "email": "philmd@linaro.org",
    "time": "Tue Aug 13 12:05:42 2024 +0200"
  },
  "committer": {
    "name": "Philippe Mathieu-Daudé",
    "email": "philmd@linaro.org",
    "time": "Tue Aug 20 00:38:48 2024 +0200"
  },
  "message": "target/mips: Use correct MMU index in get_pte()\n\nWhen refactoring page_table_walk_refill() in commit 4e999bf419\nwe missed the indirect call to cpu_mmu_index() in get_pte():\n\n  page_table_walk_refill()\n  -\u003e get_pte()\n     -\u003e cpu_ld[lq]_code()\n        -\u003e cpu_mmu_index()\n\nSince we don\u0027t mask anymore the modes in hflags, cpu_mmu_index()\ncan return UM or SM, while we only expect KM or ERL.\n\nFix by propagating ptw_mmu_idx to get_pte(), and use the\ncpu_ld/st_code_mmu() API with the correct MemOpIdx.\n\nReported-by: Thomas Petazzoni \u003cthomas.petazzoni@bootlin.com\u003e\nReported-by: Waldemar Brodkorb \u003cwbx@uclibc-ng.org\u003e\nResolves: https://gitlab.com/qemu-project/qemu/-/issues/2470\nFixes: 4e999bf419 (\"target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill\")\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-ID: \u003c20240814090452.2591-3-philmd@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "60147ba0afddc8c51fcfa234ec01e50ef4249e88",
      "old_mode": 33188,
      "old_path": "target/mips/tcg/sysemu/tlb_helper.c",
      "new_id": "0e94e00a5f5a20abdf292585f432c915f2db85f9",
      "new_mode": 33188,
      "new_path": "target/mips/tcg/sysemu/tlb_helper.c"
    }
  ]
}