)]}'
{
  "commit": "7c96dbdda8faf3a8318bd4e7898aa71a1c8a07b2",
  "tree": "11e3f46eb6f8d5b210180dd6838cfa022ee29385",
  "parents": [
    "cfc96df65e01b339fc8b544ad56863279c80decb"
  ],
  "author": {
    "name": "Nikita Novikov",
    "email": "n.novikov@syntacore.com",
    "time": "Wed Oct 29 10:17:12 2025 +0300"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Fri Jan 09 15:01:10 2026 +1000"
  },
  "message": "hw/intc/riscv_aplic: Expand inactive source handling for AIA target[i]\n\nAccording to the RISC-V AIA v1.0, section 4.5.2 (\"Source configurations\"),\nregister target[i] shall be read-only zero when interrupt source i is inactive\nin this domain. A source is inactive if it is delegated to a child domain or\nits source mode is INACTIVE.\n\nThe previous implementation only checked SM \u003d\u003d INACTIVE. This patch adds\nfull compliance:\n- Return zero on read if D \u003d\u003d 1 or SM \u003d\u003d INACTIVE\n- Ignore writes in both cases\n\nFixes: b6f1244678 (\"intc/riscv_aplic: Fix target register read when source is inactive\")\nSigned-off-by: Nikita Novikov \u003cn.novikov@syntacore.com\u003e\nAcked-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nReviewed-by: Daniel Henrique Barboza \u003cdbarboza@ventanamicro.com\u003e\nMessage-ID: \u003c20251029-n-novikov-aplic_aia_ro-v1-1-39fec74c918a@syntacore.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "92ff0ecaa74f550640a4c056124c44fe344cb93f",
      "old_mode": 33188,
      "old_path": "hw/intc/riscv_aplic.c",
      "new_id": "cf6c4148a3d89209f45d201c9223ce76e3945f1f",
      "new_mode": 33188,
      "new_path": "hw/intc/riscv_aplic.c"
    }
  ]
}