)]}'
{
  "commit": "7c228c5f3301113ffd7cfee7f982e7ae04c8ffda",
  "tree": "6aed69b52bc5f58b3b0ce51128dd5ff756929430",
  "parents": [
    "445416e3010a2525c577d692921979a64d88a998"
  ],
  "author": {
    "name": "Akihiko Odaki",
    "email": "akihiko.odaki@daynix.com",
    "time": "Tue Jul 11 00:38:36 2023 +0900"
  },
  "committer": {
    "name": "Michael S. Tsirkin",
    "email": "mst@redhat.com",
    "time": "Mon Jul 10 18:59:32 2023 -0400"
  },
  "message": "pcie: Specify 0 for ARI next function numbers\n\nThe current implementers of ARI are all SR-IOV devices. The ARI next\nfunction number field is undefined for VF according to PCI Express Base\nSpecification Revision 5.0 Version 1.0 section 9.3.7.7. The PF still\nrequires some defined value so end the linked list formed with the field\nby specifying 0 as required for any ARI implementation according to\nsection 7.8.7.2.\n\nFor migration, the field will keep having 1 as its value on the old\nQEMU machine versions.\n\nFixes: 2503461691 (\"pcie: Add some SR/IOV API documentation in docs/pcie_sriov.txt\")\nFixes: 44c2c09488 (\"hw/nvme: Add support for SR-IOV\")\nFixes: 3a977deebe (\"Intrdocue igb device emulation\")\nSigned-off-by: Akihiko Odaki \u003cakihiko.odaki@daynix.com\u003e\nReviewed-by: Ani Sinha \u003canisinha@redhat.com\u003e\nMessage-Id: \u003c20230710153838.33917-3-akihiko.odaki@daynix.com\u003e\nReviewed-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nSigned-off-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\n",
  "tree_diff": [
    {
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      "old_mode": 33188,
      "old_path": "hw/core/machine.c",
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      "new_mode": 33188,
      "new_path": "hw/core/machine.c"
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      "new_mode": 33188,
      "new_path": "hw/pci/pci.c"
    },
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      "old_path": "hw/pci/pcie.c",
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      "new_mode": 33188,
      "new_path": "hw/pci/pcie.c"
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      "new_path": "include/hw/pci/pci.h"
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}