commit 7bd0eaec311d188412123a034abb44595deb7dae
author Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Fri Apr 03 14:29:22 2015 +0200
committer Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Mon May 11 14:15:46 2015 +0200
tree d964cfff24f44532537efaf0e6b004ed58ee4b87
parent 250ef8c76861c756354ed1c67f0a4524e5339369

target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory access insted of 4

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

target-tricore/translate.c

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index d2cd640..663b2a0 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3745,10 +3745,10 @@
         tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
         break;
     case OPC1_16_SLR_LD_W:
-        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
+        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
         break;
     case OPC1_16_SLR_LD_W_POSTINC:
-        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
+        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
         tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
         break;
     }