)]}'
{
  "commit": "790fd433eb04beb410a16f8c6b2ffa4ae1fe8c54",
  "tree": "7e48bbe6332704680fb9d1611878ed27b660ebd2",
  "parents": [
    "77e349e482441bef6b7587e57031642270d6e10a"
  ],
  "author": {
    "name": "Jonathan Gilbert",
    "email": "logic@deltaq.org",
    "time": "Fri Sep 25 05:07:26 2026 -0500"
  },
  "committer": {
    "name": "Philippe Mathieu-Daudé",
    "email": "philmd@oss.qualcomm.com",
    "time": "Sun Sep 27 09:30:12 2026 +0200"
  },
  "message": "hw/misc/bcm2835_cprman: correct register index in test for mux update\n\nAfter each register write handled by cprman_write, function update_mux\nchecks each of the clocks to see whether the supplied register index\napplies to it, calling clock_mux_update if so. Each clock has two\nregisters, so it needs to check the base cm_offset for CM_CTL and then\nthe next slot for CM_DIV. But, it was checking for cm_offset plus 4, as\nthough it were a byte offset when it\u0027s a logical index.\n\nSigned-off-by: Jonathan Gilbert \u003clogic@deltaq.org\u003e\nFixes: 7281362484a (\"hw/misc/bcm2835_cprman: clock mux skeleton  implementation\")\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@oss.qualcomm.com\u003e\nMessage-ID: \u003c20260925100726.1546566-1-logic@deltaq.org\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@oss.qualcomm.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8220f7a6b4b1df3474d3e7e5dfb8e0ad6560cf15",
      "old_mode": 33188,
      "old_path": "hw/misc/bcm2835_cprman.c",
      "new_id": "f9a77ff9bb04ec7d047dcfb818c07f0d96ce99b2",
      "new_mode": 33188,
      "new_path": "hw/misc/bcm2835_cprman.c"
    }
  ]
}