)]}'
{
  "commit": "77cfbf5d08f8fbcc721b6309c560e4f48bdda8fd",
  "tree": "34b8a9f46608aa2e62578945332978bcbf8c3072",
  "parents": [
    "d4f7804bac1bc67d49c78477baae36d070cd85d1"
  ],
  "author": {
    "name": "Daniel Henrique Barboza",
    "email": "dbarboza@ventanamicro.com",
    "time": "Wed Oct 16 17:40:36 2024 -0300"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Thu Oct 31 13:51:24 2024 +1000"
  },
  "message": "docs/specs: add riscv-iommu\n\nAdd a simple guideline to use the existing RISC-V IOMMU support we just\nadded.\n\nThis doc will be updated once we add the riscv-iommu-sys device.\n\nSigned-off-by: Daniel Henrique Barboza \u003cdbarboza@ventanamicro.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nMessage-ID: \u003c20241016204038.649340-13-dbarboza@ventanamicro.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
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