target/microblaze: Split out PC from env->sregs
Begin eliminating the sregs array in favor of individual members.
Does not correct the width of pc, yet.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 51e5c85..bde9992 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -79,7 +79,7 @@
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
- cpu->env.sregs[SR_PC] = value;
+ cpu->env.pc = value;
}
static bool mb_cpu_has_work(CPUState *cs)
@@ -117,7 +117,7 @@
/* Disable stack protector. */
env->shr = ~0;
- env->sregs[SR_PC] = cpu->cfg.base_vectors;
+ env->pc = cpu->cfg.base_vectors;
#if defined(CONFIG_USER_ONLY)
/* start in user mode with interrupts enabled. */
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index a31134b..d1f91bb 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -236,6 +236,7 @@
uint32_t imm;
uint32_t regs[32];
+ uint64_t pc;
uint64_t sregs[14];
float_status fp_status;
/* Stack protectors. Yes, it's a hw feature. */
@@ -351,7 +352,7 @@
static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
{
- *pc = env->sregs[SR_PC];
+ *pc = env->pc;
*cs_base = 0;
*flags = (env->iflags & IFLAGS_TB_MASK) |
(env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
index e65ec05..9ea31f8 100644
--- a/target/microblaze/gdbstub.c
+++ b/target/microblaze/gdbstub.c
@@ -59,7 +59,7 @@
val = env->regs[n];
break;
case GDB_PC:
- val = env->sregs[SR_PC];
+ val = env->pc;
break;
case GDB_MSR:
val = env->sregs[SR_MSR];
@@ -115,7 +115,7 @@
env->regs[n] = tmp;
break;
case GDB_PC:
- env->sregs[SR_PC] = tmp;
+ env->pc = tmp;
break;
case GDB_MSR:
env->sregs[SR_MSR] = tmp;
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index ab2ceeb..5c392de 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -35,7 +35,7 @@
cs->exception_index = -1;
env->res_addr = RES_ADDR_NONE;
- env->regs[14] = env->sregs[SR_PC];
+ env->regs[14] = env->pc;
}
bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
@@ -126,7 +126,7 @@
return;
}
- env->regs[17] = env->sregs[SR_PC] + 4;
+ env->regs[17] = env->pc + 4;
env->sregs[SR_ESR] &= ~(1 << 12);
/* Exception breaks branch + dslot sequence? */
@@ -145,15 +145,15 @@
qemu_log_mask(CPU_LOG_INT,
"hw exception at pc=%" PRIx64 " ear=%" PRIx64 " "
"esr=%" PRIx64 " iflags=%x\n",
- env->sregs[SR_PC], env->sregs[SR_EAR],
+ env->pc, env->sregs[SR_EAR],
env->sregs[SR_ESR], env->iflags);
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG);
- env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
+ env->pc = cpu->cfg.base_vectors + 0x20;
break;
case EXCP_MMU:
- env->regs[17] = env->sregs[SR_PC];
+ env->regs[17] = env->pc;
env->sregs[SR_ESR] &= ~(1 << 12);
/* Exception breaks branch + dslot sequence? */
@@ -169,7 +169,7 @@
qemu_log_mask(CPU_LOG_INT,
"bimm exception at pc=%" PRIx64 " "
"iflags=%x\n",
- env->sregs[SR_PC], env->iflags);
+ env->pc, env->iflags);
env->regs[17] -= 4;
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
}
@@ -188,10 +188,10 @@
qemu_log_mask(CPU_LOG_INT,
"exception at pc=%" PRIx64 " ear=%" PRIx64 " "
"iflags=%x\n",
- env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
+ env->pc, env->sregs[SR_EAR], env->iflags);
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG);
- env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
+ env->pc = cpu->cfg.base_vectors + 0x20;
break;
case EXCP_IRQ:
@@ -209,14 +209,14 @@
{
const char *sym;
- sym = lookup_symbol(env->sregs[SR_PC]);
+ sym = lookup_symbol(env->pc);
if (sym
&& (!strcmp("netif_rx", sym)
|| !strcmp("process_backlog", sym))) {
qemu_log(
"interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
- env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
+ env->pc, env->sregs[SR_MSR], t, env->iflags,
sym);
log_cpu_state(cs, 0);
@@ -226,14 +226,14 @@
qemu_log_mask(CPU_LOG_INT,
"interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x "
"iflags=%x\n",
- env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
+ env->pc, env->sregs[SR_MSR], t, env->iflags);
env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
| MSR_UM | MSR_IE);
env->sregs[SR_MSR] |= t;
- env->regs[14] = env->sregs[SR_PC];
- env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x10;
+ env->regs[14] = env->pc;
+ env->pc = cpu->cfg.base_vectors + 0x10;
//log_cpu_state_mask(CPU_LOG_INT, cs, 0);
break;
@@ -245,17 +245,17 @@
qemu_log_mask(CPU_LOG_INT,
"break at pc=%" PRIx64 " msr=%" PRIx64 " %x "
"iflags=%x\n",
- env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
+ env->pc, env->sregs[SR_MSR], t, env->iflags);
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
env->sregs[SR_MSR] |= t;
env->sregs[SR_MSR] |= MSR_BIP;
if (cs->exception_index == EXCP_HW_BREAK) {
- env->regs[16] = env->sregs[SR_PC];
+ env->regs[16] = env->pc;
env->sregs[SR_MSR] |= MSR_BIP;
- env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x18;
+ env->pc = cpu->cfg.base_vectors + 0x18;
} else
- env->sregs[SR_PC] = env->btarget;
+ env->pc = env->btarget;
break;
default:
cpu_abort(cs, "unhandled exception type=%d\n",
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 6763421..3f403b5 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -251,7 +251,7 @@
if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
qemu_log_mask(LOG_GUEST_ERROR,
"invalidating index %x at pc=%" PRIx64 "\n",
- i, env->sregs[SR_PC]);
+ i, env->pc);
env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
mmu_flush_idx(env, i);
}
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index f3b17a9..2deef32 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -75,7 +75,7 @@
{
int i;
- qemu_log("PC=%" PRIx64 "\n", env->sregs[SR_PC]);
+ qemu_log("PC=%" PRIx64 "\n", env->pc);
qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "
"debug[%x] imm=%x iflags=%x\n",
env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index a96cb21..9f6815c 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1805,7 +1805,7 @@
}
qemu_fprintf(f, "IN: PC=%" PRIx64 " %s\n",
- env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
+ env->pc, lookup_symbol(env->pc));
qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "
"debug=%x imm=%x iflags=%x fsr=%" PRIx64 " "
"rbtr=%" PRIx64 "\n",
@@ -1868,7 +1868,11 @@
offsetof(CPUMBState, regs[i]),
regnames[i]);
}
- for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
+
+ cpu_SR[SR_PC] =
+ tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc");
+
+ for (i = 1; i < ARRAY_SIZE(cpu_SR); i++) {
cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUMBState, sregs[i]),
special_regnames[i]);
@@ -1878,5 +1882,5 @@
void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb,
target_ulong *data)
{
- env->sregs[SR_PC] = data[0];
+ env->pc = data[0];
}