Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* Some hw/isa cleanups
* Fixes for x86 CPUID
* Cleanups for configure, hw/isa and x86
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# gpg: Signature made Fri 16 Feb 2024 12:56:59 GMT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
ci: Fix again build-previous-qemu
usb: inline device creation functions
target/i386: Generate an illegal opcode exception on cmp instructions with lock prefix
i386: xen: fix compilation --without-default-devices
configure: put all symlink creation together
configure: do not create legacy symlinks
smc37c669: remove useless is_enabled functions
isa-superio: validate floppy.count value
mips: remove unnecessary "select PTIMER"
i386/cpuid: Move leaf 7 to correct group
i386/cpuid: Remove subleaf constraint on CPUID leaf 1F
i386/cpuid: Decrease cpuid_i when skipping CPUID leaf 1F
physmem: replace function name with __func__ in ram_block_discard_range()
i386/pc: Drop pc_machine_kvm_type()
target/i386: Add support of KVM_FEATURE_ASYNC_PF_VMEXIT for guest
i386/cpu: Mask with XCR0/XSS mask for FEAT_XSAVE_XCR0_HI and FEAT_XSAVE_XSS_HI leafs
i386/cpu: Clear FEAT_XSAVE_XSS_LO/HI leafs when CPUID_EXT_XSAVE is not available
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/.gitlab-ci.d/windows.yml b/.gitlab-ci.d/windows.yml
index f7645f7..5c1e385 100644
--- a/.gitlab-ci.d/windows.yml
+++ b/.gitlab-ci.d/windows.yml
@@ -88,7 +88,6 @@
$MINGW_TARGET-libpng
$MINGW_TARGET-libssh
$MINGW_TARGET-libtasn1
- $MINGW_TARGET-libusb
$MINGW_TARGET-lzo2
$MINGW_TARGET-nettle
$MINGW_TARGET-ninja
@@ -98,9 +97,8 @@
$MINGW_TARGET-SDL2
$MINGW_TARGET-SDL2_image
$MINGW_TARGET-snappy
- $MINGW_TARGET-spice
- $MINGW_TARGET-usbredir
- $MINGW_TARGET-zstd "
+ $MINGW_TARGET-zstd
+ $EXTRA_PACKAGES "
- Write-Output "Running build at $(Get-Date -Format u)"
- $env:CHERE_INVOKING = 'yes' # Preserve the current working directory
- $env:MSYS = 'winsymlinks:native' # Enable native Windows symlink
@@ -123,6 +121,8 @@
variables:
MINGW_TARGET: mingw-w64-x86_64
MSYSTEM: MINGW64
+ # msys2 only ship these packages for 64-bit, not 32-bit
+ EXTRA_PACKAGES: $MINGW_TARGET-libusb $MINGW_TARGET-usbredir $MINGW_TARGET-spice
# do not remove "--without-default-devices"!
# commit 9f8e6cad65a6 ("gitlab-ci: Speed up the msys2-64bit job by using --without-default-devices"
# changed to compile QEMU with the --without-default-devices switch
@@ -137,5 +137,6 @@
variables:
MINGW_TARGET: mingw-w64-i686
MSYSTEM: MINGW32
+ EXTRA_PACKAGES:
CONFIGURE_ARGS: --target-list=ppc64-softmmu -Ddebug=false -Doptimization=0
TEST_ARGS: --no-suite qtest
diff --git a/MAINTAINERS b/MAINTAINERS
index 48be2ff..7d61fb9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1358,6 +1358,7 @@
R: Aurelien Jarno <aurelien@aurel32.net>
S: Odd Fixes
F: hw/isa/piix.c
+F: hw/isa/fdc37m81x-superio.c
F: hw/acpi/piix4.c
F: hw/mips/malta.c
F: hw/pci-host/gt64120.c
@@ -1709,7 +1710,7 @@
F: include/hw/rtc/sun4v-rtc.h
Leon3
-M: Fabien Chouteau <chouteau@adacore.com>
+M: Clément Chigot <chigot@adacore.com>
M: Frederic Konrad <konrad.frederic@yahoo.fr>
S: Maintained
F: hw/sparc/leon3.c
@@ -3706,6 +3707,7 @@
M: Alex Bennée <alex.bennee@linaro.org>
R: Alexandre Iooss <erdnaxe@crans.org>
R: Mahmoud Mandour <ma.mandourr@gmail.com>
+R: Pierrick Bouvier <pierrick.bouvier@linaro.org>
S: Maintained
F: docs/devel/tcg-plugins.rst
F: plugins/
diff --git a/audio/meson.build b/audio/meson.build
index c8f6586..608f35e 100644
--- a/audio/meson.build
+++ b/audio/meson.build
@@ -30,7 +30,8 @@
if dbus_display
module_ss = ss.source_set()
- module_ss.add(when: [gio, pixman], if_true: files('dbusaudio.c'))
+ module_ss.add(when: [gio, dbus_display1_dep, pixman],
+ if_true: files('dbusaudio.c'))
audio_modules += {'dbus': module_ss}
endif
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index 9fdac1c..c71b1a8 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -30,7 +30,7 @@
#include "hw/boards.h"
#include "qemu/error-report.h"
#include "hw/char/pl011.h"
-#include "hw/ide/ahci.h"
+#include "hw/ide/ahci-sysbus.h"
#include "hw/cpu/a9mpcore.h"
#include "hw/cpu/a15mpcore.h"
#include "qemu/log.h"
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index f2adf30..5d3a574 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -38,6 +38,7 @@
#include "hw/boards.h"
#include "hw/ide/internal.h"
#include "hw/ide/ahci_internal.h"
+#include "hw/ide/ahci-sysbus.h"
#include "hw/intc/arm_gicv3_common.h"
#include "hw/intc/arm_gicv3_its_common.h"
#include "hw/loader.h"
diff --git a/hw/char/grlib_apbuart.c b/hw/char/grlib_apbuart.c
index 82ff40a..515b65b 100644
--- a/hw/char/grlib_apbuart.c
+++ b/hw/char/grlib_apbuart.c
@@ -1,7 +1,9 @@
/*
* QEMU GRLIB APB UART Emulator
*
- * Copyright (c) 2010-2019 AdaCore
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright (c) 2010-2024 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -26,7 +28,7 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
-#include "hw/sparc/grlib.h"
+#include "hw/char/grlib_uart.h"
#include "hw/sysbus.h"
#include "qemu/module.h"
#include "chardev/char-fe.h"
diff --git a/hw/dma/i82374.c b/hw/dma/i82374.c
index f6ddfc5..e72aa2e 100644
--- a/hw/dma/i82374.c
+++ b/hw/dma/i82374.c
@@ -129,7 +129,7 @@
error_setg(errp, "DMA already initialized on ISA bus");
return;
}
- i8257_dma_init(isa_bus, true);
+ i8257_dma_init(OBJECT(dev), isa_bus, true);
portio_list_init(&s->port_list, OBJECT(s), i82374_portio_list, s,
"i82374");
diff --git a/hw/dma/i8257.c b/hw/dma/i8257.c
index de1d5b1..24a54ca 100644
--- a/hw/dma/i8257.c
+++ b/hw/dma/i8257.c
@@ -632,12 +632,13 @@
type_init(i8257_register_types)
-void i8257_dma_init(ISABus *bus, bool high_page_enable)
+void i8257_dma_init(Object *parent, ISABus *bus, bool high_page_enable)
{
ISADevice *isa1, *isa2;
DeviceState *d;
isa1 = isa_new(TYPE_I8257);
+ object_property_add_child(parent, "dma[*]", OBJECT(isa1));
d = DEVICE(isa1);
qdev_prop_set_int32(d, "base", 0x00);
qdev_prop_set_int32(d, "page-base", 0x80);
@@ -646,6 +647,7 @@
isa_realize_and_unref(isa1, bus, &error_fatal);
isa2 = isa_new(TYPE_I8257);
+ object_property_add_child(parent, "dma[*]", OBJECT(isa2));
d = DEVICE(isa2);
qdev_prop_set_int32(d, "base", 0xc0);
qdev_prop_set_int32(d, "page-base", 0x88);
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 70d12bb..999b7b8 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -310,7 +310,7 @@
qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000);
isa_realize_and_unref(rtc_state, isa_bus, &error_fatal);
- i8257_dma_init(isa_bus, 0);
+ i8257_dma_init(OBJECT(machine), isa_bus, 0);
pcms->hpet_enabled = false;
idebus[0] = NULL;
idebus[1] = NULL;
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 7ca3f46..d346fa3 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -47,7 +47,7 @@
#include "hw/display/ramfb.h"
#include "hw/firmware/smbios.h"
#include "hw/ide/pci.h"
-#include "hw/ide/ahci.h"
+#include "hw/ide/ahci-pci.h"
#include "hw/intc/ioapic.h"
#include "hw/southbridge/ich9.h"
#include "hw/usb.h"
@@ -130,12 +130,10 @@
ISADevice *rtc_state;
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *system_io = get_system_io();
- MemoryRegion *pci_memory;
- MemoryRegion *rom_memory;
+ MemoryRegion *pci_memory = g_new(MemoryRegion, 1);
GSIState *gsi_state;
ISABus *isa_bus;
int i;
- PCIDevice *ahci;
ram_addr_t lowmem;
DriveInfo *hd[MAX_SATA_PORTS];
MachineClass *mc = MACHINE_GET_CLASS(machine);
@@ -143,6 +141,8 @@
bool keep_pci_slot_hpc;
uint64_t pci_hole64_size = 0;
+ assert(pcmc->pci_enabled);
+
/* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
* and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
* also known as MMCFG).
@@ -189,16 +189,6 @@
kvmclock_create(pcmc->kvmclock_create_always);
}
- /* pci enabled */
- if (pcmc->pci_enabled) {
- pci_memory = g_new(MemoryRegion, 1);
- memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
- rom_memory = pci_memory;
- } else {
- pci_memory = NULL;
- rom_memory = system_memory;
- }
-
pc_guest_info_init(pcms);
if (pcmc->smbios_defaults) {
@@ -212,14 +202,13 @@
/* create pci host bus */
phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE));
- if (pcmc->pci_enabled) {
- pci_hole64_size = object_property_get_uint(phb,
- PCI_HOST_PROP_PCI_HOLE64_SIZE,
- &error_abort);
- }
+ pci_hole64_size = object_property_get_uint(phb,
+ PCI_HOST_PROP_PCI_HOLE64_SIZE,
+ &error_abort);
/* allocate ram and load rom/bios */
- pc_memory_init(pcms, system_memory, rom_memory, pci_hole64_size);
+ memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
+ pc_memory_init(pcms, system_memory, pci_memory, pci_hole64_size);
object_property_add_child(OBJECT(machine), "q35", phb);
object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM,
@@ -243,18 +232,18 @@
pcms->bus = host_bus;
/* irq lines */
- gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
+ gsi_state = pc_gsi_create(&x86ms->gsi, true);
/* create ISA bus */
lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC),
TYPE_ICH9_LPC_DEVICE);
- qdev_prop_set_bit(DEVICE(lpc), "smm-enabled",
- x86_machine_is_smm_enabled(x86ms));
lpc_dev = DEVICE(lpc);
+ qdev_prop_set_bit(lpc_dev, "smm-enabled",
+ x86_machine_is_smm_enabled(x86ms));
+ pci_realize_and_unref(lpc, host_bus, &error_fatal);
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
}
- pci_realize_and_unref(lpc, host_bus, &error_fatal);
rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc"));
@@ -286,9 +275,7 @@
pc_i8259_create(isa_bus, gsi_state->i8259_irq);
}
- if (pcmc->pci_enabled) {
- ioapic_init_gsi(gsi_state, "q35");
- }
+ ioapic_init_gsi(gsi_state, "q35");
if (tcg_enabled()) {
x86_register_ferr_irq(x86ms->gsi[13]);
@@ -304,16 +291,20 @@
0xff0104);
if (pcms->sata_enabled) {
+ PCIDevice *pdev;
+ AHCIPCIState *ich9;
+
/* ahci and SATA device, for q35 1 ahci controller is built-in */
- ahci = pci_create_simple_multifunction(host_bus,
+ pdev = pci_create_simple_multifunction(host_bus,
PCI_DEVFN(ICH9_SATA1_DEV,
ICH9_SATA1_FUNC),
"ich9-ahci");
- idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
- idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
- g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
- ide_drive_get(hd, ahci_get_num_ports(ahci));
- ahci_ide_create_devs(ahci, hd);
+ ich9 = ICH9_AHCI(pdev);
+ idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0");
+ idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1");
+ g_assert(MAX_SATA_PORTS == ich9->ahci.ports);
+ ide_drive_get(hd, ich9->ahci.ports);
+ ahci_ide_create_devs(&ich9->ahci, hd);
} else {
idebus[0] = idebus[1] = NULL;
}
diff --git a/hw/ide/ahci-allwinner.c b/hw/ide/ahci-allwinner.c
index b173121..9620de8 100644
--- a/hw/ide/ahci-allwinner.c
+++ b/hw/ide/ahci-allwinner.c
@@ -19,9 +19,8 @@
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "sysemu/dma.h"
-#include "hw/ide/internal.h"
#include "migration/vmstate.h"
-#include "ahci_internal.h"
+#include "hw/ide/ahci-sysbus.h"
#include "trace.h"
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 0eb83a6..54c9685 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -36,6 +36,8 @@
#include "sysemu/dma.h"
#include "hw/ide/internal.h"
#include "hw/ide/pci.h"
+#include "hw/ide/ahci-pci.h"
+#include "hw/ide/ahci-sysbus.h"
#include "ahci_internal.h"
#include "trace.h"
@@ -1613,14 +1615,14 @@
"ahci-idp", 32);
}
-void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
+void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as)
{
qemu_irq *irqs;
int i;
s->as = as;
- s->ports = ports;
- s->dev = g_new0(AHCIDevice, ports);
+ assert(s->ports > 0);
+ s->dev = g_new0(AHCIDevice, s->ports);
ahci_reg_init(s);
irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);
for (i = 0; i < s->ports; i++) {
@@ -1818,7 +1820,7 @@
.version_id = 1,
.post_load = ahci_state_post_load,
.fields = (const VMStateField[]) {
- VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports,
+ VMSTATE_STRUCT_VARRAY_POINTER_UINT32(dev, AHCIState, ports,
vmstate_ahci_device, AHCIDevice),
VMSTATE_UINT32(control_regs.cap, AHCIState),
VMSTATE_UINT32(control_regs.ghc, AHCIState),
@@ -1826,7 +1828,7 @@
VMSTATE_UINT32(control_regs.impl, AHCIState),
VMSTATE_UINT32(control_regs.version, AHCIState),
VMSTATE_UINT32(idp_index, AHCIState),
- VMSTATE_INT32_EQUAL(ports, AHCIState, NULL),
+ VMSTATE_UINT32_EQUAL(ports, AHCIState, NULL),
VMSTATE_END_OF_LIST()
},
};
@@ -1861,11 +1863,11 @@
{
SysbusAHCIState *s = SYSBUS_AHCI(dev);
- ahci_realize(&s->ahci, dev, &address_space_memory, s->num_ports);
+ ahci_realize(&s->ahci, dev, &address_space_memory);
}
static Property sysbus_ahci_properties[] = {
- DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1),
+ DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, ahci.ports, 1),
DEFINE_PROP_END_OF_LIST(),
};
@@ -1895,18 +1897,8 @@
type_init(sysbus_ahci_register_types)
-int32_t ahci_get_num_ports(PCIDevice *dev)
+void ahci_ide_create_devs(AHCIState *ahci, DriveInfo **hd)
{
- AHCIPCIState *d = ICH9_AHCI(dev);
- AHCIState *ahci = &d->ahci;
-
- return ahci->ports;
-}
-
-void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd)
-{
- AHCIPCIState *d = ICH9_AHCI(dev);
- AHCIState *ahci = &d->ahci;
int i;
for (i = 0; i < ahci->ports; i++) {
@@ -1915,5 +1907,4 @@
}
ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]);
}
-
}
diff --git a/hw/ide/ahci_internal.h b/hw/ide/ahci_internal.h
index c244bbd..4e13329 100644
--- a/hw/ide/ahci_internal.h
+++ b/hw/ide/ahci_internal.h
@@ -324,14 +324,6 @@
MemReentrancyGuard mem_reentrancy_guard;
};
-struct AHCIPCIState {
- /*< private >*/
- PCIDevice parent_obj;
- /*< public >*/
-
- AHCIState ahci;
-};
-
extern const VMStateDescription vmstate_ahci;
#define VMSTATE_AHCI(_field, _state) { \
@@ -385,7 +377,7 @@
uint32_t payload;
} QEMU_PACKED SDBFIS;
-void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports);
+void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as);
void ahci_init(AHCIState *s, DeviceState *qdev);
void ahci_uninit(AHCIState *s);
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index 49f8eb8..3ea793d 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -69,6 +69,7 @@
#include "hw/isa/isa.h"
#include "sysemu/dma.h"
#include "hw/ide/pci.h"
+#include "hw/ide/ahci-pci.h"
#include "ahci_internal.h"
#define ICH9_MSI_CAP_OFFSET 0x80
@@ -99,20 +100,21 @@
static void pci_ich9_ahci_init(Object *obj)
{
- struct AHCIPCIState *d = ICH9_AHCI(obj);
+ AHCIPCIState *d = ICH9_AHCI(obj);
ahci_init(&d->ahci, DEVICE(obj));
}
static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
{
- struct AHCIPCIState *d;
+ AHCIPCIState *d;
int sata_cap_offset;
uint8_t *sata_cap;
d = ICH9_AHCI(dev);
int ret;
- ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
+ d->ahci.ports = 6;
+ ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev));
pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
@@ -154,7 +156,7 @@
static void pci_ich9_uninit(PCIDevice *dev)
{
- struct AHCIPCIState *d;
+ AHCIPCIState *d;
d = ICH9_AHCI(dev);
msi_uninit(dev);
diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c
index 3bfe254..144b121 100644
--- a/hw/intc/grlib_irqmp.c
+++ b/hw/intc/grlib_irqmp.c
@@ -1,9 +1,11 @@
/*
* QEMU GRLIB IRQMP Emulator
*
- * (Multiprocessor and extended interrupt not supported)
+ * (Extended interrupt not supported)
*
- * Copyright (c) 2010-2019 AdaCore
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright (c) 2010-2024 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -29,7 +31,7 @@
#include "hw/sysbus.h"
#include "hw/qdev-properties.h"
-#include "hw/sparc/grlib.h"
+#include "hw/intc/grlib_irqmp.h"
#include "trace.h"
#include "qapi/error.h"
@@ -50,6 +52,10 @@
#define FORCE_OFFSET 0x80
#define EXTENDED_OFFSET 0xC0
+/* Multiprocessor Status Register */
+#define MP_STATUS_CPU_STATUS_MASK ((1 << IRQMP_MAX_CPU)-2)
+#define MP_STATUS_NCPU_SHIFT 28
+
#define MAX_PILS 16
OBJECT_DECLARE_SIMPLE_TYPE(IRQMP, GRLIB_IRQMP)
@@ -61,14 +67,17 @@
MemoryRegion iomem;
+ unsigned int ncpus;
IRQMPState *state;
- qemu_irq irq;
+ qemu_irq start_signal[IRQMP_MAX_CPU];
+ qemu_irq irq[IRQMP_MAX_CPU];
};
struct IRQMPState {
uint32_t level;
uint32_t pending;
uint32_t clear;
+ uint32_t mpstatus;
uint32_t broadcast;
uint32_t mask[IRQMP_MAX_CPU];
@@ -80,37 +89,35 @@
static void grlib_irqmp_check_irqs(IRQMPState *state)
{
- uint32_t pend = 0;
- uint32_t level0 = 0;
- uint32_t level1 = 0;
+ int i;
assert(state != NULL);
assert(state->parent != NULL);
- /* IRQ for CPU 0 (no SMP support) */
- pend = (state->pending | state->force[0])
- & state->mask[0];
+ for (i = 0; i < state->parent->ncpus; i++) {
+ uint32_t pend = (state->pending | state->force[i]) & state->mask[i];
+ uint32_t level0 = pend & ~state->level;
+ uint32_t level1 = pend & state->level;
- level0 = pend & ~state->level;
- level1 = pend & state->level;
+ trace_grlib_irqmp_check_irqs(state->pending, state->force[i],
+ state->mask[i], level1, level0);
- trace_grlib_irqmp_check_irqs(state->pending, state->force[0],
- state->mask[0], level1, level0);
-
- /* Trigger level1 interrupt first and level0 if there is no level1 */
- qemu_set_irq(state->parent->irq, level1 ?: level0);
+ /* Trigger level1 interrupt first and level0 if there is no level1 */
+ qemu_set_irq(state->parent->irq[i], level1 ?: level0);
+ }
}
-static void grlib_irqmp_ack_mask(IRQMPState *state, uint32_t mask)
+static void grlib_irqmp_ack_mask(IRQMPState *state, unsigned int cpu,
+ uint32_t mask)
{
/* Clear registers */
state->pending &= ~mask;
- state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */
+ state->force[cpu] &= ~mask;
grlib_irqmp_check_irqs(state);
}
-void grlib_irqmp_ack(DeviceState *dev, int intno)
+void grlib_irqmp_ack(DeviceState *dev, unsigned int cpu, int intno)
{
IRQMP *irqmp = GRLIB_IRQMP(dev);
IRQMPState *state;
@@ -124,7 +131,7 @@
trace_grlib_irqmp_ack(intno);
- grlib_irqmp_ack_mask(state, mask);
+ grlib_irqmp_ack_mask(state, cpu, mask);
}
static void grlib_irqmp_set_irq(void *opaque, int irq, int level)
@@ -150,7 +157,6 @@
s->pending |= 1 << irq;
}
grlib_irqmp_check_irqs(s);
-
}
}
@@ -179,10 +185,12 @@
return state->force[0];
case CLEAR_OFFSET:
- case MP_STATUS_OFFSET:
/* Always read as 0 */
return 0;
+ case MP_STATUS_OFFSET:
+ return state->mpstatus;
+
case BROADCAST_OFFSET:
return state->broadcast;
@@ -221,8 +229,9 @@
static void grlib_irqmp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- IRQMP *irqmp = opaque;
+ IRQMP *irqmp = opaque;
IRQMPState *state;
+ int i;
assert(irqmp != NULL);
state = irqmp->state;
@@ -251,11 +260,24 @@
case CLEAR_OFFSET:
value &= ~1; /* clean up the value */
- grlib_irqmp_ack_mask(state, value);
+ for (i = 0; i < irqmp->ncpus; i++) {
+ grlib_irqmp_ack_mask(state, i, value);
+ }
return;
case MP_STATUS_OFFSET:
- /* Read Only (no SMP support) */
+ /*
+ * Writing and reading operations are reversed for the CPU status.
+ * Writing "1" will start the CPU, but reading "1" means that the CPU
+ * is power-down.
+ */
+ value &= MP_STATUS_CPU_STATUS_MASK;
+ for (i = 0; i < irqmp->ncpus; i++) {
+ if ((value >> i) & 1) {
+ qemu_set_irq(irqmp->start_signal[i], 1);
+ state->mpstatus &= ~(1 << i);
+ }
+ }
return;
case BROADCAST_OFFSET:
@@ -322,35 +344,55 @@
memset(irqmp->state, 0, sizeof *irqmp->state);
irqmp->state->parent = irqmp;
+ irqmp->state->mpstatus = ((irqmp->ncpus - 1) << MP_STATUS_NCPU_SHIFT) |
+ ((1 << irqmp->ncpus) - 2);
}
-static void grlib_irqmp_init(Object *obj)
+static void grlib_irqmp_realize(DeviceState *dev, Error **errp)
{
- IRQMP *irqmp = GRLIB_IRQMP(obj);
- SysBusDevice *dev = SYS_BUS_DEVICE(obj);
+ IRQMP *irqmp = GRLIB_IRQMP(dev);
- qdev_init_gpio_in(DEVICE(obj), grlib_irqmp_set_irq, MAX_PILS);
- qdev_init_gpio_out_named(DEVICE(obj), &irqmp->irq, "grlib-irq", 1);
- memory_region_init_io(&irqmp->iomem, obj, &grlib_irqmp_ops, irqmp,
+ if ((!irqmp->ncpus) || (irqmp->ncpus > IRQMP_MAX_CPU)) {
+ error_setg(errp, "Invalid ncpus properties: "
+ "%u, must be 0 < ncpus =< %u.", irqmp->ncpus,
+ IRQMP_MAX_CPU);
+ }
+
+ qdev_init_gpio_in(dev, grlib_irqmp_set_irq, MAX_PILS);
+
+ /*
+ * Transitionning from 0 to 1 starts the CPUs. The opposite can't
+ * happen.
+ */
+ qdev_init_gpio_out_named(dev, irqmp->start_signal, "grlib-start-cpu",
+ IRQMP_MAX_CPU);
+ qdev_init_gpio_out_named(dev, irqmp->irq, "grlib-irq", irqmp->ncpus);
+ memory_region_init_io(&irqmp->iomem, OBJECT(dev), &grlib_irqmp_ops, irqmp,
"irqmp", IRQMP_REG_SIZE);
irqmp->state = g_malloc0(sizeof *irqmp->state);
- sysbus_init_mmio(dev, &irqmp->iomem);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &irqmp->iomem);
}
+static Property grlib_irqmp_properties[] = {
+ DEFINE_PROP_UINT32("ncpus", IRQMP, ncpus, 1),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void grlib_irqmp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->realize = grlib_irqmp_realize;
dc->reset = grlib_irqmp_reset;
+ device_class_set_props(dc, grlib_irqmp_properties);
}
static const TypeInfo grlib_irqmp_info = {
.name = TYPE_GRLIB_IRQMP,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IRQMP),
- .instance_init = grlib_irqmp_init,
.class_init = grlib_irqmp_class_init,
};
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 040a18c..73c6470 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -15,9 +15,17 @@
config ISA_SUPERIO
bool
- select ISA_BUS
+ depends on ISA_BUS
select PCKBD
+ select PARALLEL
+ select SERIAL_ISA
select FDC_ISA
+ # Some users of ISA_SUPERIO do not use it
+ #select IDE_ISA
+
+config FDC37M81X
+ bool
+ select ISA_SUPERIO
config PC87312
bool
@@ -26,9 +34,6 @@
select I8254
select I8257
select MC146818RTC
- select SERIAL_ISA
- select PARALLEL
- select FDC_ISA
select IDE_ISA
config PIIX
@@ -46,11 +51,10 @@
config VT82C686
bool
+ select ISA_BUS
select ISA_SUPERIO
select ACPI
select ACPI_SMBUS
- select SERIAL_ISA
- select FDC_ISA
select USB_UHCI
select APM
select I8254
@@ -58,14 +62,10 @@
select I8259
select IDE_VIA
select MC146818RTC
- select PARALLEL
config SMC37C669
bool
select ISA_SUPERIO
- select SERIAL_ISA
- select PARALLEL
- select FDC_ISA
config LPC_ICH9
bool
diff --git a/hw/isa/fdc37m81x-superio.c b/hw/isa/fdc37m81x-superio.c
new file mode 100644
index 0000000..55e91fb
--- /dev/null
+++ b/hw/isa/fdc37m81x-superio.c
@@ -0,0 +1,32 @@
+/*
+ * SMS FDC37M817 Super I/O
+ *
+ * Copyright (c) 2018 Philippe Mathieu-Daudé
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/isa/superio.h"
+
+static void fdc37m81x_class_init(ObjectClass *klass, void *data)
+{
+ ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
+
+ sc->serial.count = 2; /* NS16C550A */
+ sc->parallel.count = 1;
+ sc->floppy.count = 1; /* SMSC 82077AA Compatible */
+ sc->ide.count = 0;
+}
+
+static const TypeInfo types[] = {
+ {
+ .name = TYPE_FDC37M81X_SUPERIO,
+ .parent = TYPE_ISA_SUPERIO,
+ .class_init = fdc37m81x_class_init,
+ },
+};
+
+DEFINE_TYPES(types)
diff --git a/hw/isa/isa-superio.c b/hw/isa/isa-superio.c
index e06a548..a8c8c58 100644
--- a/hw/isa/isa-superio.c
+++ b/hw/isa/isa-superio.c
@@ -187,30 +187,12 @@
.abstract = true,
.class_size = sizeof(ISASuperIOClass),
.class_init = isa_superio_class_init,
-};
-
-/* SMS FDC37M817 Super I/O */
-static void fdc37m81x_class_init(ObjectClass *klass, void *data)
-{
- ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
-
- sc->serial.count = 2; /* NS16C550A */
- sc->parallel.count = 1;
- sc->floppy.count = 1; /* SMSC 82077AA Compatible */
- sc->ide.count = 0;
-}
-
-static const TypeInfo fdc37m81x_type_info = {
- .name = TYPE_FDC37M81X_SUPERIO,
- .parent = TYPE_ISA_SUPERIO,
.instance_size = sizeof(ISASuperIODevice),
- .class_init = fdc37m81x_class_init,
};
static void isa_superio_register_types(void)
{
type_register_static(&isa_superio_type_info);
- type_register_static(&fdc37m81x_type_info);
}
type_init(isa_superio_register_types)
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 3924eec..70c6e8a 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -739,7 +739,7 @@
isa_bus_register_input_irqs(isa_bus, lpc->gsi);
- i8257_dma_init(isa_bus, 0);
+ i8257_dma_init(OBJECT(d), isa_bus, 0);
/* RTC */
qdev_prop_set_int32(DEVICE(&lpc->rtc), "base_year", 2000);
diff --git a/hw/isa/meson.build b/hw/isa/meson.build
index 2ab99ce..f650b39 100644
--- a/hw/isa/meson.build
+++ b/hw/isa/meson.build
@@ -4,6 +4,7 @@
system_ss.add(when: 'CONFIG_ISA_SUPERIO', if_true: files('isa-superio.c'))
system_ss.add(when: 'CONFIG_PC87312', if_true: files('pc87312.c'))
system_ss.add(when: 'CONFIG_PIIX', if_true: files('piix.c'))
+system_ss.add(when: 'CONFIG_FDC37M81X', if_true: files('fdc37m81x-superio.c'))
system_ss.add(when: 'CONFIG_SMC37C669', if_true: files('smc37c669-superio.c'))
system_ss.add(when: 'CONFIG_VT82C686', if_true: files('vt82c686.c'))
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index 344bf32..2d30711 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -336,7 +336,7 @@
i8254_pit_init(isa_bus, 0x40, 0, NULL);
}
- i8257_dma_init(isa_bus, 0);
+ i8257_dma_init(OBJECT(dev), isa_bus, 0);
/* RTC */
qdev_prop_set_int32(DEVICE(&d->rtc), "base_year", 2000);
diff --git a/hw/isa/smc37c669-superio.c b/hw/isa/smc37c669-superio.c
index 388e2ed..d2e58c9 100644
--- a/hw/isa/smc37c669-superio.c
+++ b/hw/isa/smc37c669-superio.c
@@ -85,7 +85,6 @@
static const TypeInfo smc37c669_type_info = {
.name = TYPE_SMC37C669_SUPERIO,
.parent = TYPE_ISA_SUPERIO,
- .instance_size = sizeof(ISASuperIODevice),
.class_size = sizeof(ISASuperIOClass),
.class_init = smc37c669_class_init,
};
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 0c504de..aa91942 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -731,7 +731,7 @@
s->isa_irqs_in = i8259_init(isa_bus, *isa_irq);
isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in);
i8254_pit_init(isa_bus, 0x40, 0, NULL);
- i8257_dma_init(isa_bus, 0);
+ i8257_dma_init(OBJECT(d), isa_bus, 0);
/* RTC */
qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig
index ab61af2..e57db4f 100644
--- a/hw/mips/Kconfig
+++ b/hw/mips/Kconfig
@@ -1,13 +1,12 @@
config MALTA
bool
+ select FDC37M81X
select GT64120
- select ISA_SUPERIO
select PIIX
config MIPSSIM
bool
- select ISA_BUS
- select SERIAL_ISA
+ select SERIAL
select MIPSNET
config JAZZ
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 4e11ff6..1b44fb3 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -24,7 +24,7 @@
#include "hw/boards.h"
#include "hw/char/serial.h"
#include "hw/ide/pci.h"
-#include "hw/ide/ahci.h"
+#include "hw/ide/ahci-pci.h"
#include "hw/loader.h"
#include "hw/loader-fit.h"
#include "hw/mips/bootloader.h"
@@ -677,7 +677,8 @@
MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg;
MemoryRegion *sys_mem = get_system_memory();
XilinxPCIEHost *pcie2;
- PCIDevice *ahci;
+ PCIDevice *pdev;
+ AHCIPCIState *ich9;
DriveInfo *hd[6];
Chardev *chr;
int fw_size, fit_err;
@@ -769,11 +770,12 @@
qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL,
boston_lcd_event, NULL, s, NULL, true);
- ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus,
+ pdev = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus,
PCI_DEVFN(0, 0), TYPE_ICH9_AHCI);
- g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(ahci));
- ide_drive_get(hd, ahci_get_num_ports(ahci));
- ahci_ide_create_devs(ahci, hd);
+ ich9 = ICH9_AHCI(pdev);
+ g_assert(ARRAY_SIZE(hd) == ich9->ahci.ports);
+ ide_drive_get(hd, ich9->ahci.ports);
+ ahci_ide_create_devs(&ich9->ahci, hd);
if (machine->firmware) {
fw_size = load_image_targphys(machine->firmware,
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 4f12e23..07b73b0 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -96,7 +96,6 @@
itu_present = true;
/* Attach ITC Tag to the VP */
env->itc_tag = mips_itu_get_tag_region(&s->itu);
- env->itu = &s->itu;
}
qemu_register_reset(main_cpu_reset, cpu);
}
@@ -104,8 +103,6 @@
/* Inter-Thread Communication Unit */
if (itu_present) {
object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU);
- object_property_set_link(OBJECT(&s->itu), "cpu[0]",
- OBJECT(first_cpu), &error_abort);
object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16,
&error_abort);
object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16,
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index 5bf3e32..1bc17e6 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -289,7 +289,7 @@
/* ISA devices */
i8259 = i8259_init(isa_bus, env->irq[4]);
isa_bus_register_input_irqs(isa_bus, i8259);
- i8257_dma_init(isa_bus, 0);
+ i8257_dma_init(OBJECT(rc4030), isa_bus, 0);
pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
pcspk = isa_new(TYPE_PC_SPEAKER);
object_property_set_link(OBJECT(pcspk), "pit", OBJECT(pit), &error_fatal);
diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c
index 16af316..a12427b 100644
--- a/hw/mips/mipssim.c
+++ b/hw/mips/mipssim.c
@@ -31,7 +31,6 @@
#include "hw/clock.h"
#include "hw/mips/mips.h"
#include "hw/char/serial.h"
-#include "hw/isa/isa.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
@@ -206,7 +205,11 @@
cpu_mips_irq_init_cpu(cpu);
cpu_mips_clock_init(cpu);
- /* Register 64 KB of ISA IO space at 0x1fd00000. */
+ /*
+ * Register 64 KB of ISA IO space at 0x1fd00000. But without interrupts
+ * (except for the hardcoded serial port interrupt) -device cannot work,
+ * so do not expose the ISA bus to the user.
+ */
memory_region_init_alias(isa, NULL, "isa_mmio",
get_system_io(), 0, 0x00010000);
memory_region_add_subregion(get_system_memory(), 0x1fd00000, isa);
diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c
index c9f22f8..3f449f9 100644
--- a/hw/misc/macio/macio.c
+++ b/hw/misc/macio/macio.c
@@ -123,14 +123,17 @@
{
SysBusDevice *sbd = SYS_BUS_DEVICE(ide);
- sysbus_connect_irq(sbd, 0, irq0);
- sysbus_connect_irq(sbd, 1, irq1);
qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid);
object_property_set_link(OBJECT(ide), "dbdma", OBJECT(&s->dbdma),
&error_abort);
macio_ide_register_dma(ide);
+ if (!qdev_realize(DEVICE(ide), BUS(&s->macio_bus), errp)) {
+ return false;
+ }
+ sysbus_connect_irq(sbd, 0, irq0);
+ sysbus_connect_irq(sbd, 1, irq1);
- return qdev_realize(DEVICE(ide), BUS(&s->macio_bus), errp);
+ return true;
}
static void macio_oldworld_realize(PCIDevice *d, Error **errp)
diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
index 37aea0e..f8acfb3 100644
--- a/hw/misc/mips_itu.c
+++ b/hw/misc/mips_itu.c
@@ -86,7 +86,7 @@
return tag->ITCAddressMap[index];
}
-void itc_reconfigure(MIPSITUState *tag)
+static void itc_reconfigure(MIPSITUState *tag)
{
uint64_t *am = &tag->ITCAddressMap[0];
MemoryRegion *mr = &tag->storage_io;
@@ -94,12 +94,6 @@
uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
- if (tag->saar) {
- address = (tag->saar[0] & 0xFFFFFFFFE000ULL) << 4;
- size = 1ULL << ((tag->saar[0] >> 1) & 0x1f);
- is_enabled = tag->saar[0] & 1;
- }
-
memory_region_transaction_begin();
if (!(size & (size - 1))) {
memory_region_set_size(mr, size);
@@ -158,12 +152,7 @@
static inline int get_cell_stride_shift(const MIPSITUState *s)
{
/* Minimum interval (for EntryGain = 0) is 128 B */
- if (s->saar) {
- return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) &
- ITC_ICR0_BLK_GRAIN_MASK);
- } else {
- return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
- }
+ return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
}
static inline ITCStorageCell *get_cell(MIPSITUState *s,
@@ -516,7 +505,6 @@
static void mips_itu_realize(DeviceState *dev, Error **errp)
{
MIPSITUState *s = MIPS_ITU(dev);
- CPUMIPSState *env;
if (s->num_fifo > ITC_FIFO_NUM_MAX) {
error_setg(errp, "Exceed maximum number of FIFO cells: %d",
@@ -528,15 +516,6 @@
s->num_semaphores);
return;
}
- if (!s->cpu0) {
- error_setg(errp, "Missing 'cpu[0]' property");
- return;
- }
-
- env = &MIPS_CPU(s->cpu0)->env;
- if (env->saarp) {
- s->saar = env->CP0_SAAR;
- }
s->cell = g_new(ITCStorageCell, get_num_cells(s));
}
@@ -545,15 +524,10 @@
{
MIPSITUState *s = MIPS_ITU(dev);
- if (s->saar) {
- s->saar[0] = 0x11 << 1;
- s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM;
- } else {
- s->ITCAddressMap[0] = 0;
- s->ITCAddressMap[1] =
+ s->ITCAddressMap[0] = 0;
+ s->ITCAddressMap[1] =
((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
(get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
- }
itc_reconfigure(s);
itc_reset_cells(s);
@@ -564,7 +538,6 @@
ITC_FIFO_NUM_MAX),
DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores,
ITC_SEMAPH_NUM_MAX),
- DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, ArchCPU *),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 1a6cd05..4eb5477 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -278,9 +278,9 @@
/* PCI -> ISA bridge */
i82378_dev = DEVICE(pci_new(PCI_DEVFN(11, 0), "i82378"));
+ qdev_realize_and_unref(i82378_dev, BUS(pci_bus), &error_fatal);
qdev_connect_gpio_out(i82378_dev, 0,
qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT));
- qdev_realize_and_unref(i82378_dev, BUS(pci_bus), &error_fatal);
sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15));
isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c
index 47c1702..bb4746c 100644
--- a/hw/rx/rx-gdbsim.c
+++ b/hw/rx/rx-gdbsim.c
@@ -20,6 +20,7 @@
#include "qemu/cutils.h"
#include "qemu/error-report.h"
#include "qemu/guest-random.h"
+#include "qemu/units.h"
#include "qapi/error.h"
#include "hw/loader.h"
#include "hw/rx/rx62n.h"
diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c
index 4dc44af..560f53a 100644
--- a/hw/rx/rx62n.c
+++ b/hw/rx/rx62n.c
@@ -23,6 +23,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
+#include "qemu/units.h"
#include "hw/rx/rx62n.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
@@ -147,14 +148,11 @@
qlist_append_int(trigger_level, levelirq[i]);
}
qdev_prop_set_array(DEVICE(icu), "trigger-level", trigger_level);
-
- for (i = 0; i < NR_IRQS; i++) {
- s->irq[i] = qdev_get_gpio_in(DEVICE(icu), i);
- }
sysbus_realize(icu, &error_abort);
+
sysbus_connect_irq(icu, 0, qdev_get_gpio_in(DEVICE(&s->cpu), RX_CPU_IRQ));
sysbus_connect_irq(icu, 1, qdev_get_gpio_in(DEVICE(&s->cpu), RX_CPU_FIR));
- sysbus_connect_irq(icu, 2, s->irq[SWI]);
+ sysbus_connect_irq(icu, 2, qdev_get_gpio_in(DEVICE(&s->icu), SWI));
sysbus_mmio_map(icu, 0, RX62N_ICU_BASE);
}
@@ -171,7 +169,8 @@
irqbase = RX62N_TMR_IRQ + TMR_NR_IRQ * unit;
for (i = 0; i < TMR_NR_IRQ; i++) {
- sysbus_connect_irq(tmr, i, s->irq[irqbase + i]);
+ sysbus_connect_irq(tmr, i,
+ qdev_get_gpio_in(DEVICE(&s->icu), irqbase + i));
}
sysbus_mmio_map(tmr, 0, RX62N_TMR_BASE + unit * 0x10);
}
@@ -189,7 +188,8 @@
irqbase = RX62N_CMT_IRQ + CMT_NR_IRQ * unit;
for (i = 0; i < CMT_NR_IRQ; i++) {
- sysbus_connect_irq(cmt, i, s->irq[irqbase + i]);
+ sysbus_connect_irq(cmt, i,
+ qdev_get_gpio_in(DEVICE(&s->icu), irqbase + i));
}
sysbus_mmio_map(cmt, 0, RX62N_CMT_BASE + unit * 0x10);
}
@@ -208,7 +208,8 @@
irqbase = RX62N_SCI_IRQ + SCI_NR_IRQ * unit;
for (i = 0; i < SCI_NR_IRQ; i++) {
- sysbus_connect_irq(sci, i, s->irq[irqbase + i]);
+ sysbus_connect_irq(sci, i,
+ qdev_get_gpio_in(DEVICE(&s->icu), irqbase + i));
}
sysbus_mmio_map(sci, 0, RX62N_SCI_BASE + unit * 0x08);
}
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index e9f316a..c73e8f4 100644
--- a/hw/sh4/r2d.c
+++ b/hw/sh4/r2d.c
@@ -285,9 +285,9 @@
dinfo = drive_get(IF_IDE, 0, 0);
dev = qdev_new("mmio-ide");
busdev = SYS_BUS_DEVICE(dev);
- sysbus_connect_irq(busdev, 0, irq[CF_IDE]);
qdev_prop_set_uint32(dev, "shift", 1);
sysbus_realize_and_unref(busdev, &error_fatal);
+ sysbus_connect_irq(busdev, 0, irq[CF_IDE]);
sysbus_mmio_map(busdev, 0, 0x14001000);
sysbus_mmio_map(busdev, 1, 0x1400080c);
mmio_ide_init_drives(dev, dinfo, NULL);
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index 2dfb742..4873b59 100644
--- a/hw/sparc/leon3.c
+++ b/hw/sparc/leon3.c
@@ -1,7 +1,9 @@
/*
* QEMU Leon3 System Emulator
*
- * Copyright (c) 2010-2019 AdaCore
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright (c) 2010-2024 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -40,7 +42,9 @@
#include "elf.h"
#include "trace.h"
-#include "hw/sparc/grlib.h"
+#include "hw/timer/grlib_gptimer.h"
+#include "hw/char/grlib_uart.h"
+#include "hw/intc/grlib_irqmp.h"
#include "hw/misc/grlib_ahb_apb_pnp.h"
/* Default system clock. */
@@ -50,6 +54,8 @@
#define LEON3_PROM_OFFSET (0x00000000)
#define LEON3_RAM_OFFSET (0x40000000)
+#define MAX_CPUS 4
+
#define LEON3_UART_OFFSET (0x80000100)
#define LEON3_UART_IRQ (3)
@@ -63,9 +69,11 @@
#define LEON3_AHB_PNP_OFFSET (0xFFFFF000)
typedef struct ResetData {
- SPARCCPU *cpu;
- uint32_t entry; /* save kernel entry in case of reset */
- target_ulong sp; /* initial stack pointer */
+ struct CPUResetData {
+ int id;
+ SPARCCPU *cpu;
+ } info[MAX_CPUS];
+ uint32_t entry; /* save kernel entry in case of reset */
} ResetData;
static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val)
@@ -91,13 +99,26 @@
/*
* When loading a kernel in RAM the machine is expected to be in a different
- * state (eg: initialized by the bootloader). This little code reproduces
- * this behavior.
+ * state (eg: initialized by the bootloader). This little code reproduces
+ * this behavior. Also this code can be executed by the secondary cpus as
+ * well since it looks at the %asr17 register before doing any
+ * initialization, it allows to use the same reset address for all the
+ * cpus.
*/
-static void write_bootloader(CPUSPARCState *env, uint8_t *base,
- hwaddr kernel_addr)
+static void write_bootloader(void *ptr, hwaddr kernel_addr)
{
- uint32_t *p = (uint32_t *) base;
+ uint32_t *p = ptr;
+ uint32_t *sec_cpu_branch_p = NULL;
+
+ /* If we are running on a secondary CPU, jump directly to the kernel. */
+
+ stl_p(p++, 0x85444000); /* rd %asr17, %g2 */
+ stl_p(p++, 0x8530a01c); /* srl %g2, 0x1c, %g2 */
+ stl_p(p++, 0x80908000); /* tst %g2 */
+ /* Filled below. */
+ sec_cpu_branch_p = p;
+ stl_p(p++, 0x0BADC0DE); /* bne xxx */
+ stl_p(p++, 0x01000000); /* nop */
/* Initialize the UARTs */
/* *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE; */
@@ -111,6 +132,10 @@
/* *GPTIMER0_CONFIG = GPTIMER_ENABLE | GPTIMER_RESTART; */
p = gen_store_u32(p, 0x80000318, 3);
+ /* Now, the relative branch above can be computed. */
+ stl_p(sec_cpu_branch_p, 0x12800000
+ + (p - sec_cpu_branch_p));
+
/* JUMP to the entry point */
stl_p(p++, 0x82100000); /* mov %g0, %g1 */
stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22));
@@ -121,18 +146,19 @@
stl_p(p++, 0x01000000); /* nop */
}
-static void main_cpu_reset(void *opaque)
+static void leon3_cpu_reset(void *opaque)
{
- ResetData *s = (ResetData *)opaque;
- CPUState *cpu = CPU(s->cpu);
- CPUSPARCState *env = &s->cpu->env;
+ struct CPUResetData *info = (struct CPUResetData *) opaque;
+ int id = info->id;
+ ResetData *s = (ResetData *)DO_UPCAST(ResetData, info[id], info);
+ CPUState *cpu = CPU(s->info[id].cpu);
+ CPUSPARCState *env = cpu_env(cpu);
cpu_reset(cpu);
- cpu->halted = 0;
- env->pc = s->entry;
- env->npc = s->entry + 4;
- env->regbase[6] = s->sp;
+ cpu->halted = cpu->cpu_index != 0;
+ env->pc = s->entry;
+ env->npc = s->entry + 4;
}
static void leon3_cache_control_int(CPUSPARCState *env)
@@ -166,7 +192,8 @@
static void leon3_irq_ack(CPUSPARCState *env, int intno)
{
- grlib_irqmp_ack(env->irq_manager, intno);
+ CPUState *cpu = CPU(env_cpu(env));
+ grlib_irqmp_ack(env->irq_manager, cpu->cpu_index, intno);
}
/*
@@ -175,9 +202,10 @@
*/
static void leon3_set_pil_in(void *opaque, int n, int level)
{
- CPUSPARCState *env = opaque;
+ DeviceState *cpu = opaque;
+ CPUState *cs = CPU(cpu);
+ CPUSPARCState *env = cpu_env(cs);
uint32_t pil_in = level;
- CPUState *cs;
assert(env != NULL);
@@ -193,7 +221,6 @@
env->interrupt_index = TT_EXTINT | i;
if (old_interrupt != env->interrupt_index) {
- cs = env_cpu(env);
trace_leon3_set_irq(i);
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
}
@@ -201,13 +228,26 @@
}
}
} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
- cs = env_cpu(env);
trace_leon3_reset_irq(env->interrupt_index & 15);
env->interrupt_index = 0;
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
+static void leon3_start_cpu_async_work(CPUState *cpu, run_on_cpu_data data)
+{
+ cpu->halted = 0;
+}
+
+static void leon3_start_cpu(void *opaque, int n, int level)
+{
+ DeviceState *cpu = opaque;
+ CPUState *cs = CPU(cpu);
+
+ assert(level == 1);
+ async_run_on_cpu(cs, leon3_start_cpu_async_work, RUN_ON_CPU_NULL);
+}
+
static void leon3_irq_manager(CPUSPARCState *env, int intno)
{
leon3_irq_ack(env, intno);
@@ -233,17 +273,23 @@
AHBPnp *ahb_pnp;
APBPnp *apb_pnp;
- /* Init CPU */
- cpu = SPARC_CPU(cpu_create(machine->cpu_type));
- env = &cpu->env;
+ reset_info = g_malloc0(sizeof(ResetData));
- cpu_sparc_set_id(env, 0);
+ for (i = 0; i < machine->smp.cpus; i++) {
+ /* Init CPU */
+ cpu = SPARC_CPU(object_new(machine->cpu_type));
+ qdev_init_gpio_in_named(DEVICE(cpu), leon3_start_cpu, "start_cpu", 1);
+ qdev_init_gpio_in_named(DEVICE(cpu), leon3_set_pil_in, "pil", 1);
+ qdev_realize(DEVICE(cpu), NULL, &error_fatal);
+ env = &cpu->env;
- /* Reset data */
- reset_info = g_new0(ResetData, 1);
- reset_info->cpu = cpu;
- reset_info->sp = LEON3_RAM_OFFSET + ram_size;
- qemu_register_reset(main_cpu_reset, reset_info);
+ cpu_sparc_set_id(env, i);
+
+ /* Reset data */
+ reset_info->info[i].id = i;
+ reset_info->info[i].cpu = cpu;
+ qemu_register_reset(leon3_cpu_reset, &reset_info->info[i]);
+ }
ahb_pnp = GRLIB_AHB_PNP(qdev_new(TYPE_GRLIB_AHB_PNP));
sysbus_realize_and_unref(SYS_BUS_DEVICE(ahb_pnp), &error_fatal);
@@ -261,14 +307,24 @@
/* Allocate IRQ manager */
irqmpdev = qdev_new(TYPE_GRLIB_IRQMP);
- qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in,
- env, "pil", 1);
- qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", 0,
- qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0));
+ object_property_set_int(OBJECT(irqmpdev), "ncpus", machine->smp.cpus,
+ &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(irqmpdev), &error_fatal);
+
+ for (i = 0; i < machine->smp.cpus; i++) {
+ cpu = reset_info->info[i].cpu;
+ env = &cpu->env;
+ qdev_connect_gpio_out_named(irqmpdev, "grlib-start-cpu", i,
+ qdev_get_gpio_in_named(DEVICE(cpu),
+ "start_cpu", 0));
+ qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", i,
+ qdev_get_gpio_in_named(DEVICE(cpu),
+ "pil", 0));
+ env->irq_manager = irqmpdev;
+ env->qemu_irq_ack = leon3_irq_manager;
+ }
+
sysbus_mmio_map(SYS_BUS_DEVICE(irqmpdev), 0, LEON3_IRQMP_OFFSET);
- env->irq_manager = irqmpdev;
- env->qemu_irq_ack = leon3_irq_manager;
grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF,
GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV,
2, 0, GRLIB_APBIO_AREA);
@@ -339,13 +395,12 @@
* the machine in an initialized state through a little
* bootloader.
*/
- uint8_t *bootloader_entry;
-
- bootloader_entry = memory_region_get_ram_ptr(prom);
- write_bootloader(env, bootloader_entry, entry);
- env->pc = LEON3_PROM_OFFSET;
- env->npc = LEON3_PROM_OFFSET + 4;
+ write_bootloader(memory_region_get_ram_ptr(prom), entry);
reset_info->entry = LEON3_PROM_OFFSET;
+ for (i = 0; i < machine->smp.cpus; i++) {
+ reset_info->info[i].cpu->env.pc = LEON3_PROM_OFFSET;
+ reset_info->info[i].cpu->env.npc = LEON3_PROM_OFFSET + 4;
+ }
}
}
@@ -384,6 +439,7 @@
mc->init = leon3_generic_hw_init;
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("LEON3");
mc->default_ram_id = "leon3.ram";
+ mc->max_cpus = MAX_CPUS;
}
DEFINE_MACHINE("leon3_generic", leon3_generic_machine_init)
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index e782c8e..d52e6a7 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -312,13 +312,11 @@
dma = qdev_new(TYPE_SPARC32_DMA);
espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
OBJECT(dma), "espdma"));
- sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
esp = SYSBUS_ESP(object_resolve_path_component(OBJECT(espdma), "esp"));
ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
OBJECT(dma), "ledma"));
- sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
lance = SYSBUS_PCNET(object_resolve_path_component(
OBJECT(ledma), "lance"));
@@ -332,6 +330,11 @@
}
sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
+
sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
index 72f0849..3091cde 100644
--- a/hw/sparc64/sparc64.c
+++ b/hw/sparc64/sparc64.c
@@ -24,6 +24,7 @@
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "cpu.h"
#include "hw/boards.h"
#include "hw/sparc/sparc64.h"
@@ -271,9 +272,10 @@
uint32_t stick_frequency = 100 * 1000000;
uint32_t hstick_frequency = 100 * 1000000;
- cpu = SPARC_CPU(cpu_create(cpu_type));
+ cpu = SPARC_CPU(object_new(cpu_type));
qdev_init_gpio_in_named(DEVICE(cpu), sparc64_cpu_set_ivec_irq,
"ivec-irq", IVEC_MAX);
+ qdev_realize(DEVICE(cpu), NULL, &error_fatal);
env = &cpu->env;
env->tick = cpu_timer_create("tick", cpu, tick_irq,
diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c
index 5c4923c..4990885 100644
--- a/hw/timer/grlib_gptimer.c
+++ b/hw/timer/grlib_gptimer.c
@@ -1,7 +1,9 @@
/*
* QEMU GRLIB GPTimer Emulator
*
- * Copyright (c) 2010-2019 AdaCore
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright (c) 2010-2024 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -23,7 +25,7 @@
*/
#include "qemu/osdep.h"
-#include "hw/sparc/grlib.h"
+#include "hw/timer/grlib_gptimer.h"
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "hw/irq.h"
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index 2eb83a1..67a9a17 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -5,7 +5,7 @@
#include "hw/intc/allwinner-a10-pic.h"
#include "hw/net/allwinner_emac.h"
#include "hw/sd/allwinner-sdhost.h"
-#include "hw/ide/ahci.h"
+#include "hw/ide/ahci-sysbus.h"
#include "hw/usb/hcd-ohci.h"
#include "hw/usb/hcd-ehci.h"
#include "hw/rtc/allwinner-rtc.h"
diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h
index 66c38e7..614e74b 100644
--- a/include/hw/arm/allwinner-r40.h
+++ b/include/hw/arm/allwinner-r40.h
@@ -22,7 +22,7 @@
#include "qom/object.h"
#include "hw/timer/allwinner-a10-pit.h"
-#include "hw/ide/ahci.h"
+#include "hw/ide/ahci-sysbus.h"
#include "hw/intc/arm_gic.h"
#include "hw/sd/allwinner-sdhost.h"
#include "hw/misc/allwinner-r40-ccu.h"
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 96358d5..48f7948 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -22,7 +22,7 @@
#include "hw/net/cadence_gem.h"
#include "hw/char/cadence_uart.h"
#include "hw/net/xlnx-zynqmp-can.h"
-#include "hw/ide/ahci.h"
+#include "hw/ide/ahci-sysbus.h"
#include "hw/sd/sdhci.h"
#include "hw/ssi/xilinx_spips.h"
#include "hw/dma/xlnx_dpdma.h"
diff --git a/include/hw/sparc/grlib.h b/include/hw/char/grlib_uart.h
similarity index 71%
copy from include/hw/sparc/grlib.h
copy to include/hw/char/grlib_uart.h
index ef1946c..7496f8f 100644
--- a/include/hw/sparc/grlib.h
+++ b/include/hw/char/grlib_uart.h
@@ -1,7 +1,9 @@
/*
- * QEMU GRLIB Components
+ * QEMU GRLIB UART
*
- * Copyright (c) 2010-2019 AdaCore
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright (c) 2024 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -22,24 +24,9 @@
* THE SOFTWARE.
*/
-#ifndef GRLIB_H
-#define GRLIB_H
+#ifndef GRLIB_UART_H
+#define GRLIB_UART_H
-#include "hw/sysbus.h"
-
-/* Emulation of GrLib device is base on the GRLIB IP Core User's Manual:
- * http://www.gaisler.com/products/grlib/grip.pdf
- */
-
-/* IRQMP */
-#define TYPE_GRLIB_IRQMP "grlib-irqmp"
-
-void grlib_irqmp_ack(DeviceState *dev, int intno);
-
-/* GPTimer */
-#define TYPE_GRLIB_GPTIMER "grlib-gptimer"
-
-/* APB UART */
#define TYPE_GRLIB_APB_UART "grlib-apbuart"
-#endif /* GRLIB_H */
+#endif
diff --git a/include/hw/dma/i8257.h b/include/hw/dma/i8257.h
index f652345..4342e4a 100644
--- a/include/hw/dma/i8257.h
+++ b/include/hw/dma/i8257.h
@@ -45,6 +45,6 @@
PortioList portio_pageh;
};
-void i8257_dma_init(ISABus *bus, bool high_page_enable);
+void i8257_dma_init(Object *parent, ISABus *bus, bool high_page_enable);
#endif
diff --git a/include/hw/ide/ahci-pci.h b/include/hw/ide/ahci-pci.h
new file mode 100644
index 0000000..c2ee616
--- /dev/null
+++ b/include/hw/ide/ahci-pci.h
@@ -0,0 +1,22 @@
+/*
+ * QEMU AHCI Emulation (PCI devices)
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef HW_IDE_AHCI_PCI_H
+#define HW_IDE_AHCI_PCI_H
+
+#include "qom/object.h"
+#include "hw/ide/ahci.h"
+#include "hw/pci/pci_device.h"
+
+#define TYPE_ICH9_AHCI "ich9-ahci"
+OBJECT_DECLARE_SIMPLE_TYPE(AHCIPCIState, ICH9_AHCI)
+
+struct AHCIPCIState {
+ PCIDevice parent_obj;
+
+ AHCIState ahci;
+};
+
+#endif
diff --git a/include/hw/ide/ahci-sysbus.h b/include/hw/ide/ahci-sysbus.h
new file mode 100644
index 0000000..06eaac8
--- /dev/null
+++ b/include/hw/ide/ahci-sysbus.h
@@ -0,0 +1,35 @@
+/*
+ * QEMU AHCI Emulation (MMIO-mapped devices)
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef HW_IDE_AHCI_SYSBUS_H
+#define HW_IDE_AHCI_SYSBUS_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+#include "hw/ide/ahci.h"
+
+#define TYPE_SYSBUS_AHCI "sysbus-ahci"
+OBJECT_DECLARE_SIMPLE_TYPE(SysbusAHCIState, SYSBUS_AHCI)
+
+struct SysbusAHCIState {
+ SysBusDevice parent_obj;
+
+ AHCIState ahci;
+};
+
+#define TYPE_ALLWINNER_AHCI "allwinner-ahci"
+OBJECT_DECLARE_SIMPLE_TYPE(AllwinnerAHCIState, ALLWINNER_AHCI)
+
+#define ALLWINNER_AHCI_MMIO_OFF 0x80
+#define ALLWINNER_AHCI_MMIO_SIZE 0x80
+
+struct AllwinnerAHCIState {
+ SysbusAHCIState parent_obj;
+
+ MemoryRegion mmio;
+ uint32_t regs[ALLWINNER_AHCI_MMIO_SIZE / 4];
+};
+
+#endif
diff --git a/include/hw/ide/ahci.h b/include/hw/ide/ahci.h
index 210e5e7..ba31e75 100644
--- a/include/hw/ide/ahci.h
+++ b/include/hw/ide/ahci.h
@@ -24,8 +24,7 @@
#ifndef HW_IDE_AHCI_H
#define HW_IDE_AHCI_H
-#include "hw/sysbus.h"
-#include "qom/object.h"
+#include "exec/memory.h"
typedef struct AHCIDevice AHCIDevice;
@@ -46,43 +45,12 @@
MemoryRegion idp; /* Index-Data Pair I/O port space */
unsigned idp_offset; /* Offset of index in I/O port space */
uint32_t idp_index; /* Current IDP index */
- int32_t ports;
+ uint32_t ports;
qemu_irq irq;
AddressSpace *as;
} AHCIState;
-#define TYPE_ICH9_AHCI "ich9-ahci"
-OBJECT_DECLARE_SIMPLE_TYPE(AHCIPCIState, ICH9_AHCI)
-
-int32_t ahci_get_num_ports(PCIDevice *dev);
-void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
-
-#define TYPE_SYSBUS_AHCI "sysbus-ahci"
-OBJECT_DECLARE_SIMPLE_TYPE(SysbusAHCIState, SYSBUS_AHCI)
-
-struct SysbusAHCIState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- AHCIState ahci;
- uint32_t num_ports;
-};
-
-#define TYPE_ALLWINNER_AHCI "allwinner-ahci"
-OBJECT_DECLARE_SIMPLE_TYPE(AllwinnerAHCIState, ALLWINNER_AHCI)
-
-#define ALLWINNER_AHCI_MMIO_OFF 0x80
-#define ALLWINNER_AHCI_MMIO_SIZE 0x80
-
-struct AllwinnerAHCIState {
- /*< private >*/
- SysbusAHCIState parent_obj;
- /*< public >*/
-
- MemoryRegion mmio;
- uint32_t regs[ALLWINNER_AHCI_MMIO_SIZE/4];
-};
+void ahci_ide_create_devs(AHCIState *ahci, DriveInfo **hd);
#endif /* HW_IDE_AHCI_H */
diff --git a/include/hw/sparc/grlib.h b/include/hw/intc/grlib_irqmp.h
similarity index 83%
rename from include/hw/sparc/grlib.h
rename to include/hw/intc/grlib_irqmp.h
index ef1946c..a76acbf 100644
--- a/include/hw/sparc/grlib.h
+++ b/include/hw/intc/grlib_irqmp.h
@@ -1,7 +1,9 @@
/*
* QEMU GRLIB Components
*
- * Copyright (c) 2010-2019 AdaCore
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright (c) 2010-2024 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -22,8 +24,8 @@
* THE SOFTWARE.
*/
-#ifndef GRLIB_H
-#define GRLIB_H
+#ifndef GRLIB_IRQMP_H
+#define GRLIB_IRQMP_H
#include "hw/sysbus.h"
@@ -34,12 +36,6 @@
/* IRQMP */
#define TYPE_GRLIB_IRQMP "grlib-irqmp"
-void grlib_irqmp_ack(DeviceState *dev, int intno);
+void grlib_irqmp_ack(DeviceState *dev, unsigned int cpu, int intno);
-/* GPTimer */
-#define TYPE_GRLIB_GPTIMER "grlib-gptimer"
-
-/* APB UART */
-#define TYPE_GRLIB_APB_UART "grlib-apbuart"
-
-#endif /* GRLIB_H */
+#endif /* GRLIB_IRQMP_H */
diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h
index 5caed6c..27c9a10 100644
--- a/include/hw/misc/mips_itu.h
+++ b/include/hw/misc/mips_itu.h
@@ -70,15 +70,9 @@
/* ITU Control Register */
uint64_t icr0;
-
- /* SAAR */
- uint64_t *saar;
- ArchCPU *cpu0;
};
/* Get ITC Configuration Tag memory region. */
MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu);
-void itc_reconfigure(struct MIPSITUState *tag);
-
#endif /* MIPS_ITU_H */
diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h
index 73ceeb5..766fe0e 100644
--- a/include/hw/rx/rx62n.h
+++ b/include/hw/rx/rx62n.h
@@ -29,7 +29,6 @@
#include "hw/timer/renesas_tmr.h"
#include "hw/timer/renesas_cmt.h"
#include "hw/char/renesas_sci.h"
-#include "qemu/units.h"
#include "qom/object.h"
#define TYPE_RX62N_MCU "rx62n-mcu"
@@ -68,7 +67,6 @@
MemoryRegion iomem2;
MemoryRegion iomem3;
MemoryRegion c_flash;
- qemu_irq irq[NR_IRQS];
/* Input Clock (XTAL) frequency */
uint32_t xtal_freq_hz;
diff --git a/include/hw/sparc/grlib.h b/include/hw/timer/grlib_gptimer.h
similarity index 71%
copy from include/hw/sparc/grlib.h
copy to include/hw/timer/grlib_gptimer.h
index ef1946c..e56f1b8 100644
--- a/include/hw/sparc/grlib.h
+++ b/include/hw/timer/grlib_gptimer.h
@@ -1,7 +1,9 @@
/*
- * QEMU GRLIB Components
+ * QEMU GRLIB GPTimer
*
- * Copyright (c) 2010-2019 AdaCore
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright (c) 2024 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -22,24 +24,9 @@
* THE SOFTWARE.
*/
-#ifndef GRLIB_H
-#define GRLIB_H
+#ifndef GRLIB_GPTIMER_H
+#define GRLIB_GPTIMER_H
-#include "hw/sysbus.h"
-
-/* Emulation of GrLib device is base on the GRLIB IP Core User's Manual:
- * http://www.gaisler.com/products/grlib/grip.pdf
- */
-
-/* IRQMP */
-#define TYPE_GRLIB_IRQMP "grlib-irqmp"
-
-void grlib_irqmp_ack(DeviceState *dev, int intno);
-
-/* GPTimer */
#define TYPE_GRLIB_GPTIMER "grlib-gptimer"
-/* APB UART */
-#define TYPE_GRLIB_APB_UART "grlib-apbuart"
-
-#endif /* GRLIB_H */
+#endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index ef26fe0..7329226 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -747,9 +747,7 @@
* CP0 Register 9
*/
int32_t CP0_Count;
- uint32_t CP0_SAARI;
#define CP0SAARI_TARGET 0 /* 5..0 */
- uint64_t CP0_SAAR[2];
#define CP0SAAR_BASE 12 /* 43..12 */
#define CP0SAAR_SIZE 1 /* 5..1 */
#define CP0SAAR_EN 0
@@ -1174,7 +1172,6 @@
uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
uint64_t insn_flags; /* Supported instruction set */
- int saarp;
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
@@ -1183,8 +1180,7 @@
CPUMIPSMVPContext *mvp;
#if !defined(CONFIG_USER_ONLY)
CPUMIPSTLBContext *tlb;
- void *irq[8];
- struct MIPSITUState *itu;
+ qemu_irq irq[8];
MemoryRegion *itc_tag; /* ITC Configuration Tags */
/* Loongson IOCSR memory */
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 1d0c026..a9a22ea 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -83,7 +83,6 @@
uint32_t lcsr_cpucfg2;
uint64_t insn_flags;
enum mips_mmu_types mmu_type;
- int32_t SAARP;
};
extern const char regnames[32][3];
diff --git a/target/mips/sysemu/machine.c b/target/mips/sysemu/machine.c
index 218f4c3..213fd63 100644
--- a/target/mips/sysemu/machine.c
+++ b/target/mips/sysemu/machine.c
@@ -281,8 +281,8 @@
VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
VMSTATE_INT32(env.CP0_Count, MIPSCPU),
- VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
- VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
+ VMSTATE_UNUSED(sizeof(uint32_t)), /* was CP0_SAARI */
+ VMSTATE_UNUSED(2 * sizeof(uint64_t)), /* was CP0_SAAR[2] */
VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
VMSTATE_INT32(env.CP0_Status, MIPSCPU),
diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c
index 62f6fb4..ded6c78 100644
--- a/target/mips/tcg/sysemu/cp0_helper.c
+++ b/target/mips/tcg/sysemu/cp0_helper.c
@@ -371,22 +371,6 @@
return (int32_t)cpu_mips_get_count(env);
}
-target_ulong helper_mfc0_saar(CPUMIPSState *env)
-{
- if ((env->CP0_SAARI & 0x3f) < 2) {
- return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f];
- }
- return 0;
-}
-
-target_ulong helper_mfhc0_saar(CPUMIPSState *env)
-{
- if ((env->CP0_SAARI & 0x3f) < 2) {
- return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32;
- }
- return 0;
-}
-
target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
@@ -514,13 +498,6 @@
return env->CP0_WatchHi[sel];
}
-target_ulong helper_dmfc0_saar(CPUMIPSState *env)
-{
- if ((env->CP0_SAARI & 0x3f) < 2) {
- return env->CP0_SAAR[env->CP0_SAARI & 0x3f];
- }
- return 0;
-}
#endif /* TARGET_MIPS64 */
void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
@@ -1100,46 +1077,6 @@
cpu_mips_store_count(env, arg1);
}
-void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1)
-{
- uint32_t target = arg1 & 0x3f;
- if (target <= 1) {
- env->CP0_SAARI = target;
- }
-}
-
-void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
-{
- uint32_t target = env->CP0_SAARI & 0x3f;
- if (target < 2) {
- env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL;
- switch (target) {
- case 0:
- if (env->itu) {
- itc_reconfigure(env->itu);
- }
- break;
- }
- }
-}
-
-void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
-{
- uint32_t target = env->CP0_SAARI & 0x3f;
- if (target < 2) {
- env->CP0_SAAR[target] =
- (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) |
- (env->CP0_SAAR[target] & 0x00000000ffffffffULL);
- switch (target) {
- case 0:
- if (env->itu) {
- itc_reconfigure(env->itu);
- }
- break;
- }
- }
-}
-
void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
{
target_ulong old, val, mask;
diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_helper.h.inc
index f163af1..1861d53 100644
--- a/target/mips/tcg/sysemu_helper.h.inc
+++ b/target/mips/tcg/sysemu_helper.h.inc
@@ -31,8 +31,6 @@
DEF_HELPER_1(mfc0_tcschefback, tl, env)
DEF_HELPER_1(mftc0_tcschefback, tl, env)
DEF_HELPER_1(mfc0_count, tl, env)
-DEF_HELPER_1(mfc0_saar, tl, env)
-DEF_HELPER_1(mfhc0_saar, tl, env)
DEF_HELPER_1(mftc0_entryhi, tl, env)
DEF_HELPER_1(mftc0_status, tl, env)
DEF_HELPER_1(mftc0_cause, tl, env)
@@ -57,7 +55,6 @@
DEF_HELPER_1(dmfc0_maar, tl, env)
DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)
DEF_HELPER_2(dmfc0_watchhi, tl, env, i32)
-DEF_HELPER_1(dmfc0_saar, tl, env)
#endif /* TARGET_MIPS64 */
DEF_HELPER_2(mtc0_index, void, env, tl)
@@ -103,9 +100,6 @@
DEF_HELPER_2(mtc0_hwrena, void, env, tl)
DEF_HELPER_2(mtc0_pwctl, void, env, tl)
DEF_HELPER_2(mtc0_count, void, env, tl)
-DEF_HELPER_2(mtc0_saari, void, env, tl)
-DEF_HELPER_2(mtc0_saar, void, env, tl)
-DEF_HELPER_2(mthc0_saar, void, env, tl)
DEF_HELPER_2(mtc0_entryhi, void, env, tl)
DEF_HELPER_2(mttc0_entryhi, void, env, tl)
DEF_HELPER_2(mtc0_compare, void, env, tl)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 12094cc..3ba2101 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -5151,17 +5151,6 @@
goto cp0_unimplemented;
}
break;
- case CP0_REGISTER_09:
- switch (sel) {
- case CP0_REG09__SAAR:
- CP0_CHECK(ctx->saar);
- gen_helper_mfhc0_saar(arg, tcg_env);
- register_name = "SAAR";
- break;
- default:
- goto cp0_unimplemented;
- }
- break;
case CP0_REGISTER_17:
switch (sel) {
case CP0_REG17__LLADDR:
@@ -5252,17 +5241,6 @@
goto cp0_unimplemented;
}
break;
- case CP0_REGISTER_09:
- switch (sel) {
- case CP0_REG09__SAAR:
- CP0_CHECK(ctx->saar);
- gen_helper_mthc0_saar(tcg_env, arg);
- register_name = "SAAR";
- break;
- default:
- goto cp0_unimplemented;
- }
- break;
case CP0_REGISTER_17:
switch (sel) {
case CP0_REG17__LLADDR:
@@ -5675,16 +5653,6 @@
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Count";
break;
- case CP0_REG09__SAARI:
- CP0_CHECK(ctx->saar);
- gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
- register_name = "SAARI";
- break;
- case CP0_REG09__SAAR:
- CP0_CHECK(ctx->saar);
- gen_helper_mfc0_saar(arg, tcg_env);
- register_name = "SAAR";
- break;
default:
goto cp0_unimplemented;
}
@@ -6401,16 +6369,6 @@
gen_helper_mtc0_count(tcg_env, arg);
register_name = "Count";
break;
- case CP0_REG09__SAARI:
- CP0_CHECK(ctx->saar);
- gen_helper_mtc0_saari(tcg_env, arg);
- register_name = "SAARI";
- break;
- case CP0_REG09__SAAR:
- CP0_CHECK(ctx->saar);
- gen_helper_mtc0_saar(tcg_env, arg);
- register_name = "SAAR";
- break;
default:
goto cp0_unimplemented;
}
@@ -7175,16 +7133,6 @@
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Count";
break;
- case CP0_REG09__SAARI:
- CP0_CHECK(ctx->saar);
- gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
- register_name = "SAARI";
- break;
- case CP0_REG09__SAAR:
- CP0_CHECK(ctx->saar);
- gen_helper_dmfc0_saar(arg, tcg_env);
- register_name = "SAAR";
- break;
default:
goto cp0_unimplemented;
}
@@ -7887,16 +7835,6 @@
gen_helper_mtc0_count(tcg_env, arg);
register_name = "Count";
break;
- case CP0_REG09__SAARI:
- CP0_CHECK(ctx->saar);
- gen_helper_mtc0_saari(tcg_env, arg);
- register_name = "SAARI";
- break;
- case CP0_REG09__SAAR:
- CP0_CHECK(ctx->saar);
- gen_helper_mtc0_saar(tcg_env, arg);
- register_name = "SAAR";
- break;
default:
goto cp0_unimplemented;
}
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 93a78b8..2b6646b 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -49,7 +49,6 @@
bool mrp;
bool nan2008;
bool abs2008;
- bool saar;
bool mi;
int gi;
} DisasContext;
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index edf46b3..f3cdd17 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -545,10 +545,9 @@
#endif
sparc_def_t def;
- void *irq_manager;
+ /* Leon3 */
+ DeviceState *irq_manager;
void (*qemu_irq_ack)(CPUSPARCState *env, int intno);
-
- /* Leon3 cache control */
uint32_t cache_control;
};
diff --git a/target/sparc/helper.c b/target/sparc/helper.c
index bd10b60..2247e24 100644
--- a/target/sparc/helper.c
+++ b/target/sparc/helper.c
@@ -212,4 +212,20 @@
env->npc = env->pc + 4;
cpu_loop_exit(cs);
}
+
+target_ulong helper_rdasr17(CPUSPARCState *env)
+{
+ CPUState *cs = env_cpu(env);
+ target_ulong val;
+
+ /*
+ * TODO: There are many more fields to be filled,
+ * some of which are writable.
+ */
+ val = env->def.nwindows - 1; /* [4:0] NWIN */
+ val |= 1 << 8; /* [8] V8 */
+ val |= (cs->cpu_index) << 28; /* [31:28] INDEX */
+
+ return val;
+}
#endif
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index 6a42ba4..e55fad5 100644
--- a/target/sparc/helper.h
+++ b/target/sparc/helper.h
@@ -2,6 +2,7 @@
DEF_HELPER_1(rett, void, env)
DEF_HELPER_2(wrpsr, void, env, tl)
DEF_HELPER_1(rdpsr, tl, env)
+DEF_HELPER_1(rdasr17, tl, env)
DEF_HELPER_1(power_down, void, env)
#else
DEF_HELPER_FLAGS_2(wrpil, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index d9304a5..692ce0b 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -37,6 +37,7 @@
#ifdef TARGET_SPARC64
# define gen_helper_rdpsr(D, E) qemu_build_not_reached()
+# define gen_helper_rdasr17(D, E) qemu_build_not_reached()
# define gen_helper_rett(E) qemu_build_not_reached()
# define gen_helper_power_down(E) qemu_build_not_reached()
# define gen_helper_wrpsr(E, S) qemu_build_not_reached()
@@ -2382,16 +2383,8 @@
static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst)
{
- uint32_t val;
-
- /*
- * TODO: There are many more fields to be filled,
- * some of which are writable.
- */
- val = dc->def->nwindows - 1; /* [4:0] NWIN */
- val |= 1 << 8; /* [8] V8 */
-
- return tcg_constant_tl(val);
+ gen_helper_rdasr17(dst, tcg_env);
+ return dst;
}
TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 2b89e86..430d49b 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -344,7 +344,7 @@
endif
if dbus_display
- qtests += {'dbus-display-test': [dbus_display1, gio]}
+ qtests += {'dbus-display-test': [dbus_display1_dep, gio]}
endif
qtest_executables = {}
diff --git a/ui/clipboard.c b/ui/clipboard.c
index 3d14bff..4264884 100644
--- a/ui/clipboard.c
+++ b/ui/clipboard.c
@@ -65,12 +65,24 @@
void qemu_clipboard_update(QemuClipboardInfo *info)
{
+ uint32_t type;
QemuClipboardNotify notify = {
.type = QEMU_CLIPBOARD_UPDATE_INFO,
.info = info,
};
assert(info->selection < QEMU_CLIPBOARD_SELECTION__COUNT);
+ for (type = 0; type < QEMU_CLIPBOARD_TYPE__COUNT; type++) {
+ /*
+ * If data is missing, the clipboard owner's 'request' callback needs to
+ * be set. Otherwise, there is no way to get the clipboard data and
+ * qemu_clipboard_request() cannot be called.
+ */
+ if (info->types[type].available && !info->types[type].data) {
+ assert(info->owner && info->owner->request);
+ }
+ }
+
notifier_list_notify(&clipboard_notifiers, ¬ify);
if (cbinfo[info->selection] != info) {
@@ -132,6 +144,8 @@
!info->owner)
return;
+ assert(info->owner->request);
+
info->types[type].requested = true;
info->owner->request(info, type);
}
@@ -163,9 +177,15 @@
}
g_free(info->types[type].data);
- info->types[type].data = g_memdup(data, size);
- info->types[type].size = size;
- info->types[type].available = true;
+ if (size) {
+ info->types[type].data = g_memdup2(data, size);
+ info->types[type].size = size;
+ info->types[type].available = true;
+ } else {
+ info->types[type].data = NULL;
+ info->types[type].size = 0;
+ info->types[type].available = false;
+ }
if (update) {
qemu_clipboard_update(info);
diff --git a/ui/console.c b/ui/console.c
index 7db921e..83205567 100644
--- a/ui/console.c
+++ b/ui/console.c
@@ -1577,7 +1577,7 @@
assert(QEMU_IS_GRAPHIC_CONSOLE(s));
if ((s->scanout.kind != SCANOUT_SURFACE ||
- (surface && surface->flags & QEMU_ALLOCATED_FLAG)) &&
+ (surface && !is_buffer_shared(surface) && !is_placeholder(surface))) &&
qemu_console_get_width(s, -1) == width &&
qemu_console_get_height(s, -1) == height) {
return;
diff --git a/ui/meson.build b/ui/meson.build
index 376e0d7..0b7e2b6 100644
--- a/ui/meson.build
+++ b/ui/meson.build
@@ -91,7 +91,7 @@
'--c-namespace', 'QemuDBus',
'--generate-c-code', '@BASENAME@'])
dbus_display1_lib = static_library('dbus-display1', dbus_display1, dependencies: gio)
- dbus_display1_dep = declare_dependency(link_with: dbus_display1_lib, include_directories: include_directories('.'))
+ dbus_display1_dep = declare_dependency(link_with: dbus_display1_lib, sources: dbus_display1[0])
dbus_ss.add(when: [gio, dbus_display1_dep],
if_true: [files(
'dbus-chardev.c',
diff --git a/ui/vnc.c b/ui/vnc.c
index 3db87fd..af20d24 100644
--- a/ui/vnc.c
+++ b/ui/vnc.c
@@ -2445,6 +2445,11 @@
}
if (read_s32(data, 4) < 0) {
+ if (!vnc_has_feature(vs, VNC_FEATURE_CLIPBOARD_EXT)) {
+ error_report("vnc: extended clipboard message while disabled");
+ vnc_client_error(vs);
+ break;
+ }
if (dlen < 4) {
error_report("vnc: malformed payload (header less than 4 bytes)"
" in extended clipboard pseudo-encoding.");
