commit 75eed0e5f74a05ade59b874aff3b652b5ee2e47e
author Max Filippov <jcmvbkbc@gmail.com> Sun Apr 14 14:02:17 2019 -0700
committer Max Filippov <jcmvbkbc@gmail.com> Tue May 14 13:19:35 2019 -0700
tree 6fadd58727fe9a6351811bfda471c655337d6e59
parent 4d04ea35b30f9ba4097b746622eea07be3f2c363

target/xtensa: implement DIWBUI.P opcode

This is a recent addition to the set of data cache opcodes.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

target/xtensa/cpu.h

diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index d6e6bf6..ba4ef2b 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -466,6 +466,7 @@
 
     unsigned icache_ways;
     unsigned dcache_ways;
+    unsigned dcache_line_bytes;
     uint32_t memctl_mask;
 
     XtensaMemory instrom;

target/xtensa/overlay_tool.h

diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h
index b61c925..4925b21 100644
--- a/target/xtensa/overlay_tool.h
+++ b/target/xtensa/overlay_tool.h
@@ -425,6 +425,7 @@
 #define CACHE_SECTION \
     .icache_ways = XCHAL_ICACHE_WAYS, \
     .dcache_ways = XCHAL_DCACHE_WAYS, \
+    .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \
     .memctl_mask = \
         (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \
         (XCHAL_DCACHE_SIZE ? \

target/xtensa/translate.c

diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 782f2ec..24eb70d 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1620,6 +1620,12 @@
                         arg[2].imm, arg[3].imm);
 }
 
+static void translate_diwbuip(DisasContext *dc, const OpcodeArg arg[],
+                              const uint32_t par[])
+{
+    tcg_gen_addi_i32(arg[0].out, arg[0].in, dc->config->dcache_line_bytes);
+}
+
 static bool test_ill_entry(DisasContext *dc, const OpcodeArg arg[],
                            const uint32_t par[])
 {
@@ -3098,6 +3104,10 @@
         .translate = translate_nop,
         .op_flags = XTENSA_OP_PRIVILEGED,
     }, {
+        .name = "diwbui.p",
+        .translate = translate_diwbuip,
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
         .name = "dpfl",
         .translate = translate_dcache,
         .op_flags = XTENSA_OP_PRIVILEGED,