commit 729d45a6af06753d3e330f589c248fe9687c5cd5
author Li Zhijian <lizhijian@fujitsu.com> Fri Jan 26 12:01:27 2024 +0000
committer Michael S. Tsirkin <mst@redhat.com> Wed Feb 14 06:09:32 2024 -0500
tree b2a37a1e9a2f7afb0692f29de70f6df9981e46d3
parent f7509f462c788a347521f90f19d623908c4fbcc5

hw/cxl: Pass CXLComponentState to cache_mem_ops

cache_mem_ops.{read,write}() interprets opaque as
CXLComponentState(cxl_cstate) instead of ComponentRegisters(cregs).

Fortunately, cregs is the first member of cxl_cstate, so their values are
the same.

Fixes: 9e58f52d3f8 ("hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)")
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Li Zhijian <lizhijian@fujitsu.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126120132.24248-8-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>