qemu /
qemu /
553cf5d7c47bee05a3dec9461c1f8430316d516b Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging
target-arm queue:
* hw/arm/aspeed: improve QOM usage
* hw/misc/pca9552: trace GPIO change events
* target/arm: Implement ARMv8.5-MemTag for system emulation
# gpg: Signature made Fri 26 Jun 2020 16:13:27 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20200626: (57 commits)
target/arm: Enable MTE
target/arm: Add allocation tag storage for system mode
target/arm: Create tagged ram when MTE is enabled
target/arm: Cache the Tagged bit for a page in MemTxAttrs
target/arm: Always pass cacheattr to get_phys_addr
target/arm: Set PSTATE.TCO on exception entry
target/arm: Implement data cache set allocation tags
target/arm: Complete TBI clearing for user-only for SVE
target/arm: Add mte helpers for sve scatter/gather memory ops
target/arm: Handle TBI for sve scalar + int memory ops
target/arm: Add mte helpers for sve scalar + int ff/nf loads
target/arm: Add mte helpers for sve scalar + int stores
target/arm: Add mte helpers for sve scalar + int loads
target/arm: Add arm_tlb_bti_gp
target/arm: Tidy trans_LD1R_zpri
target/arm: Use mte_check1 for sve LD1R
target/arm: Use mte_checkN for sve unpredicated stores
target/arm: Use mte_checkN for sve unpredicated loads
target/arm: Add helper_mte_check_zva
target/arm: Implement helper_mte_checkN
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
