Merge tag 'pull-request-2023-01-18' of https://gitlab.com/thuth/qemu into staging
* Fix the FreeBSD CI jobs in Gitlab by upgrading the packages in the beginning
* Fix the Haiku VM test by updating it to r1beta4
* Allow "make uninstall"
* Rename TARGET_FMT_plx to HWADDR_FMT_plx
* Some small qtest fixes/improvements
* Check for valid amount of CPUs before starting a secure execution s390x guest
# -----BEGIN PGP SIGNATURE-----
#
# iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmPH2JIRHHRodXRoQHJl
# ZGhhdC5jb20ACgkQLtnXdP5wLbUSWRAAk7C6vcVeDL066ftV75qErGcY1lpTF5GA
# 6rn1EO8wxGUxdjwi5koqqcn7m4LGWJKNnbZkp+7u5h4ni1G6Wu5v5Lnemtb0I5qI
# M7fTr9QUErK39eV5bPNrZ/Zr4bXRnM6BdYGrTh5d4FZoeIwhjBG/zofWNw/4p11L
# HLxeG3z3xns5DHQFeMn2v8oapRVWq9h5dIFhWwmEoc0+UBT5cboDM0UnJ8iiZ0Q+
# 5AvZVn01iQK/UXGj1iT3JK47jE0P5dregm+h4sd0MUYU1/8LaOIy93YvWk1qI7ID
# WPJoo9EwqYOYf2lmEfbitgxW5tlp5l/1SGtDXuvkisXmQeMMRB3Dv48nta80sFow
# PVSwwXqkqbazocsBdFP1tF2cBR/mvRPpVKa+VtF2pu9szCREdfbbt6ERJ2sePUyG
# MpKhqFV/dPLgcbNgvtUQbyzGBxlieoIRgndYmZwxMIb6uJKmlcJkQg2SYfRAVrri
# Bdbo0/HdW0IBTn7zFmpVUgEtkpxxpiz1zjPKBA4o/vaTDh44HT1EcFCTZ1HKaUbp
# iLABMtz5DRS+HJbeIsI8IiCAsIG0r8JRukRrde3k4iEzLq4gt+Df7NIXJtlSIJ+H
# 8M+JO7c2N4meWuHV7x3xUFGVQxYQQG93m8bWbhgyBtdtoayaN9Fb8XpXXShblXxc
# ozHrBQe3ciI=
# =zfXp
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 18 Jan 2023 11:31:30 GMT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2023-01-18' of https://gitlab.com/thuth/qemu:
s390x/pv: Implement a CGS check helper
tests/vm/haiku.x86_64: Update the Haiku VM to Beta 4
tests/qtest/libqos/e1000e: Remove duplicate register definitions
tests/qtest/e1000e-test: Fix the code style
tests/qtest: Restrict bcm2835-dma-test to CONFIG_RASPI
MAINTAINERS: Remove bouncing mail address from Kamil Rytarowski
bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx
Makefile: allow 'make uninstall'
Upgrade all packages in the FreeBSD VMs to ensure the freshness
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/.gitlab-ci.d/cirrus.yml b/.gitlab-ci.d/cirrus.yml
index 785b163..502dfd6 100644
--- a/.gitlab-ci.d/cirrus.yml
+++ b/.gitlab-ci.d/cirrus.yml
@@ -53,7 +53,7 @@
CIRRUS_VM_IMAGE_NAME: freebsd-12-4
CIRRUS_VM_CPUS: 8
CIRRUS_VM_RAM: 8G
- UPDATE_COMMAND: pkg update
+ UPDATE_COMMAND: pkg update; pkg upgrade -y
INSTALL_COMMAND: pkg install -y
TEST_TARGETS: check
@@ -66,7 +66,7 @@
CIRRUS_VM_IMAGE_NAME: freebsd-13-1
CIRRUS_VM_CPUS: 8
CIRRUS_VM_RAM: 8G
- UPDATE_COMMAND: pkg update
+ UPDATE_COMMAND: pkg update; pkg upgrade -y
INSTALL_COMMAND: pkg install -y
TEST_TARGETS: check
diff --git a/MAINTAINERS b/MAINTAINERS
index 0fe50d0..08ad1e5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -511,7 +511,6 @@
Guest CPU Cores (NVMM)
----------------------
NetBSD Virtual Machine Monitor (NVMM) CPU support
-M: Kamil Rytarowski <kamil@netbsd.org>
M: Reinoud Zandijk <reinoud@netbsd.org>
S: Maintained
F: include/sysemu/nvmm.h
@@ -536,7 +535,6 @@
F: include/qemu/*posix*.h
NETBSD
-M: Kamil Rytarowski <kamil@netbsd.org>
M: Reinoud Zandijk <reinoud@netbsd.org>
M: Ryo ONODERA <ryoon@netbsd.org>
S: Maintained
diff --git a/Makefile b/Makefile
index a48103c..ce2f83a 100644
--- a/Makefile
+++ b/Makefile
@@ -150,7 +150,7 @@
ninja-cmd-goals = $(or $(MAKECMDGOALS), all)
ninja-cmd-goals += $(foreach g, $(MAKECMDGOALS), $(.ninja-goals.$g))
-makefile-targets := build.ninja ctags TAGS cscope dist clean uninstall
+makefile-targets := build.ninja ctags TAGS cscope dist clean
# "ninja -t targets" also lists all prerequisites. If build system
# files are marked as PHONY, however, Make will always try to execute
# "ninja build.ninja".
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 4948729..4e040a1 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1142,7 +1142,7 @@
&xlat, &sz, full->attrs, &prot);
assert(sz >= TARGET_PAGE_SIZE);
- tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
+ tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" HWADDR_FMT_plx
" prot=%x idx=%d\n",
vaddr, full->phys_addr, prot, mmu_idx);
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
index 39b8f01..cc73145 100644
--- a/hw/arm/strongarm.c
+++ b/hw/arm/strongarm.c
@@ -151,7 +151,7 @@
case ICPR:
return s->pending;
default:
- printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
+ printf("%s: Bad register offset 0x" HWADDR_FMT_plx "\n",
__func__, offset);
return 0;
}
@@ -173,7 +173,7 @@
s->int_idle = (value & 1) ? 0 : ~0;
break;
default:
- printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
+ printf("%s: Bad register offset 0x" HWADDR_FMT_plx "\n",
__func__, offset);
break;
}
@@ -333,7 +333,7 @@
((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1));
default:
- printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
+ printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr);
return 0;
}
}
@@ -375,7 +375,7 @@
break;
default:
- printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
+ printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr);
}
}
@@ -581,7 +581,7 @@
return s->status;
default:
- printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
+ printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset);
}
return 0;
@@ -626,7 +626,7 @@
break;
default:
- printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
+ printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset);
}
}
@@ -782,7 +782,7 @@
return s->ppfr | ~0x7f001;
default:
- printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
+ printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset);
}
return 0;
@@ -817,7 +817,7 @@
break;
default:
- printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
+ printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset);
}
}
@@ -1164,7 +1164,7 @@
return s->utsr1;
default:
- printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
+ printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr);
return 0;
}
}
@@ -1221,7 +1221,7 @@
break;
default:
- printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
+ printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr);
}
}
@@ -1443,7 +1443,7 @@
strongarm_ssp_fifo_update(s);
return retval;
default:
- printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
+ printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr);
break;
}
return 0;
@@ -1509,7 +1509,7 @@
break;
default:
- printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
+ printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr);
break;
}
}
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
index 0cbc2fb..36d68c7 100644
--- a/hw/block/pflash_cfi01.c
+++ b/hw/block/pflash_cfi01.c
@@ -645,7 +645,7 @@
error_flash:
qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence "
- "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)"
+ "(offset " HWADDR_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)"
"\n", __func__, offset, pfl->wcycle, pfl->cmd, value);
mode_read_array:
diff --git a/hw/char/digic-uart.c b/hw/char/digic-uart.c
index 00e5df5..51d4e7d 100644
--- a/hw/char/digic-uart.c
+++ b/hw/char/digic-uart.c
@@ -63,7 +63,7 @@
default:
qemu_log_mask(LOG_UNIMP,
"digic-uart: read access to unknown register 0x"
- TARGET_FMT_plx "\n", addr << 2);
+ HWADDR_FMT_plx "\n", addr << 2);
}
return ret;
@@ -101,7 +101,7 @@
default:
qemu_log_mask(LOG_UNIMP,
"digic-uart: write access to unknown register 0x"
- TARGET_FMT_plx "\n", addr << 2);
+ HWADDR_FMT_plx "\n", addr << 2);
}
}
diff --git a/hw/char/etraxfs_ser.c b/hw/char/etraxfs_ser.c
index e8c3017..8d6422d 100644
--- a/hw/char/etraxfs_ser.c
+++ b/hw/char/etraxfs_ser.c
@@ -113,7 +113,7 @@
break;
default:
r = s->regs[addr];
- D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r));
+ D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr, r));
break;
}
return r;
@@ -127,7 +127,7 @@
uint32_t value = val64;
unsigned char ch = val64;
- D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value));
+ D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr, value));
addr >>= 2;
switch (addr)
{
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 55dbe2e..173f8f6 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -1059,7 +1059,7 @@
rom->mr = mr;
snprintf(devpath, sizeof(devpath), "/rom@%s", file);
} else {
- snprintf(devpath, sizeof(devpath), "/rom@" TARGET_FMT_plx, addr);
+ snprintf(devpath, sizeof(devpath), "/rom@" HWADDR_FMT_plx, addr);
}
}
@@ -1243,10 +1243,10 @@
"\nThe following two regions overlap (in the %s address space):\n",
rom_as_name(rom));
error_printf(
- " %s (addresses 0x" TARGET_FMT_plx " - 0x" TARGET_FMT_plx ")\n",
+ " %s (addresses 0x" HWADDR_FMT_plx " - 0x" HWADDR_FMT_plx ")\n",
last_rom->name, last_rom->addr, last_rom->addr + last_rom->romsize);
error_printf(
- " %s (addresses 0x" TARGET_FMT_plx " - 0x" TARGET_FMT_plx ")\n",
+ " %s (addresses 0x" HWADDR_FMT_plx " - 0x" HWADDR_FMT_plx ")\n",
rom->name, rom->addr, rom->addr + rom->romsize);
}
@@ -1600,7 +1600,7 @@
rom->romsize,
rom->name);
} else if (!rom->fw_file) {
- g_string_append_printf(buf, "addr=" TARGET_FMT_plx
+ g_string_append_printf(buf, "addr=" HWADDR_FMT_plx
" size=0x%06zx mem=%s name=\"%s\"\n",
rom->addr, rom->romsize,
rom->isrom ? "rom" : "ram",
diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c
index 05c1da3..35f902b 100644
--- a/hw/core/sysbus.c
+++ b/hw/core/sysbus.c
@@ -269,7 +269,7 @@
for (i = 0; i < s->num_mmio; i++) {
size = memory_region_size(s->mmio[i].memory);
- monitor_printf(mon, "%*smmio " TARGET_FMT_plx "/" TARGET_FMT_plx "\n",
+ monitor_printf(mon, "%*smmio " HWADDR_FMT_plx "/" HWADDR_FMT_plx "\n",
indent, "", s->mmio[i].addr, size);
}
}
@@ -289,7 +289,7 @@
}
}
if (s->num_mmio) {
- return g_strdup_printf("%s@" TARGET_FMT_plx, qdev_fw_name(dev),
+ return g_strdup_printf("%s@" HWADDR_FMT_plx, qdev_fw_name(dev),
s->mmio[0].addr);
}
if (s->num_pio) {
diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c
index 55c32e3..b80f98b 100644
--- a/hw/display/cirrus_vga.c
+++ b/hw/display/cirrus_vga.c
@@ -2041,7 +2041,7 @@
} else {
val = 0xff;
qemu_log_mask(LOG_GUEST_ERROR,
- "cirrus: mem_readb 0x" TARGET_FMT_plx "\n", addr);
+ "cirrus: mem_readb 0x" HWADDR_FMT_plx "\n", addr);
}
return val;
}
@@ -2105,7 +2105,7 @@
}
} else {
qemu_log_mask(LOG_GUEST_ERROR,
- "cirrus: mem_writeb 0x" TARGET_FMT_plx " "
+ "cirrus: mem_writeb 0x" HWADDR_FMT_plx " "
"value 0x%02" PRIx64 "\n", addr, mem_value);
}
}
diff --git a/hw/display/g364fb.c b/hw/display/g364fb.c
index caca86d..2903cab 100644
--- a/hw/display/g364fb.c
+++ b/hw/display/g364fb.c
@@ -320,7 +320,7 @@
break;
default:
{
- error_report("g364: invalid read at [" TARGET_FMT_plx "]",
+ error_report("g364: invalid read at [" HWADDR_FMT_plx "]",
addr);
val = 0;
break;
@@ -424,7 +424,7 @@
break;
default:
error_report("g364: invalid write of 0x%" PRIx64
- " at [" TARGET_FMT_plx "]", val, addr);
+ " at [" HWADDR_FMT_plx "]", val, addr);
break;
}
}
diff --git a/hw/display/vga.c b/hw/display/vga.c
index 0cb26a7..7a5fdff 100644
--- a/hw/display/vga.c
+++ b/hw/display/vga.c
@@ -875,7 +875,7 @@
uint32_t write_mask, bit_mask, set_mask;
#ifdef DEBUG_VGA_MEM
- printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
+ printf("vga: [0x" HWADDR_FMT_plx "] = 0x%02x\n", addr, val);
#endif
/* convert to VGA memory offset */
memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
@@ -909,7 +909,7 @@
assert(addr < s->vram_size);
s->vram_ptr[addr] = val;
#ifdef DEBUG_VGA_MEM
- printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
+ printf("vga: chain4: [0x" HWADDR_FMT_plx "]\n", addr);
#endif
s->plane_updated |= mask; /* only used to detect font change */
memory_region_set_dirty(&s->vram, addr, 1);
@@ -925,7 +925,7 @@
}
s->vram_ptr[addr] = val;
#ifdef DEBUG_VGA_MEM
- printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
+ printf("vga: odd/even: [0x" HWADDR_FMT_plx "]\n", addr);
#endif
s->plane_updated |= mask; /* only used to detect font change */
memory_region_set_dirty(&s->vram, addr, 1);
@@ -1003,7 +1003,7 @@
(((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
(val & write_mask);
#ifdef DEBUG_VGA_MEM
- printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
+ printf("vga: latch: [0x" HWADDR_FMT_plx "] mask=0x%08x val=0x%08x\n",
addr * 4, write_mask, val);
#endif
memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
diff --git a/hw/dma/etraxfs_dma.c b/hw/dma/etraxfs_dma.c
index c4334e8..0fef00c 100644
--- a/hw/dma/etraxfs_dma.c
+++ b/hw/dma/etraxfs_dma.c
@@ -269,34 +269,34 @@
static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
{
- hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
+ hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
- /* Load and decode. FIXME: handle endianness. */
- D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
+ /* Load and decode. FIXME: handle endianness. */
+ D(printf("%s ch=%d addr=" HWADDR_FMT_plx "\n", __func__, c, addr));
cpu_physical_memory_read(addr, &ctrl->channels[c].current_d,
sizeof(ctrl->channels[c].current_d));
- D(dump_d(c, &ctrl->channels[c].current_d));
- ctrl->channels[c].regs[RW_DATA] = addr;
+ D(dump_d(c, &ctrl->channels[c].current_d));
+ ctrl->channels[c].regs[RW_DATA] = addr;
}
static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
{
- hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
+ hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
- /* Encode and store. FIXME: handle endianness. */
- D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
- D(dump_d(c, &ctrl->channels[c].current_d));
+ /* Encode and store. FIXME: handle endianness. */
+ D(printf("%s ch=%d addr=" HWADDR_FMT_plx "\n", __func__, c, addr));
+ D(dump_d(c, &ctrl->channels[c].current_d));
cpu_physical_memory_write(addr, &ctrl->channels[c].current_c,
sizeof(ctrl->channels[c].current_c));
}
static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
{
- hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
+ hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
- /* Encode and store. FIXME: handle endianness. */
- D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
+ /* Encode and store. FIXME: handle endianness. */
+ D(printf("%s ch=%d addr=" HWADDR_FMT_plx "\n", __func__, c, addr));
cpu_physical_memory_write(addr, &ctrl->channels[c].current_d,
sizeof(ctrl->channels[c].current_d));
}
@@ -574,8 +574,8 @@
static uint32_t dma_rinvalid (void *opaque, hwaddr addr)
{
- hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
- return 0;
+ hw_error("Unsupported short raccess. reg=" HWADDR_FMT_plx "\n", addr);
+ return 0;
}
static uint64_t
@@ -603,7 +603,7 @@
default:
r = ctrl->channels[c].regs[addr];
- D(printf ("%s c=%d addr=" TARGET_FMT_plx "\n",
+ D(printf("%s c=%d addr=" HWADDR_FMT_plx "\n",
__func__, c, addr));
break;
}
@@ -613,7 +613,7 @@
static void
dma_winvalid (void *opaque, hwaddr addr, uint32_t value)
{
- hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
+ hw_error("Unsupported short waccess. reg=" HWADDR_FMT_plx "\n", addr);
}
static void
@@ -686,7 +686,7 @@
break;
default:
- D(printf ("%s c=%d " TARGET_FMT_plx "\n",
+ D(printf("%s c=%d " HWADDR_FMT_plx "\n",
__func__, c, addr));
break;
}
diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c
index e5d521c..e7e67dd 100644
--- a/hw/dma/pl330.c
+++ b/hw/dma/pl330.c
@@ -1373,7 +1373,7 @@
pl330_exec(s);
} else {
qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u "
- "for offset " TARGET_FMT_plx "\n", (unsigned)value,
+ "for offset " HWADDR_FMT_plx "\n", (unsigned)value,
offset);
}
break;
@@ -1384,7 +1384,7 @@
s->dbg[1] = value;
break;
default:
- qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " TARGET_FMT_plx
+ qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " HWADDR_FMT_plx
"\n", offset);
break;
}
@@ -1409,7 +1409,7 @@
chan_id = offset >> 5;
if (chan_id >= s->num_chnls) {
qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
return 0;
}
switch (offset & 0x1f) {
@@ -1425,7 +1425,7 @@
return s->chan[chan_id].lc[1];
default:
qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
return 0;
}
}
@@ -1434,7 +1434,7 @@
chan_id = offset >> 3;
if (chan_id >= s->num_chnls) {
qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
return 0;
}
switch ((offset >> 2) & 1) {
@@ -1456,7 +1456,7 @@
chan_id = offset >> 2;
if (chan_id >= s->num_chnls) {
qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
return 0;
}
return s->chan[chan_id].fault_type;
@@ -1495,7 +1495,7 @@
return s->debug_status;
default:
qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
}
return 0;
}
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
index cbb8f0f..6030c76 100644
--- a/hw/dma/xilinx_axidma.c
+++ b/hw/dma/xilinx_axidma.c
@@ -456,7 +456,7 @@
break;
default:
r = s->regs[addr];
- D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx " v=%x\n",
+ D(qemu_log("%s ch=%d addr=" HWADDR_FMT_plx " v=%x\n",
__func__, sid, addr * 4, r));
break;
}
@@ -509,7 +509,7 @@
}
break;
default:
- D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n",
+ D(qemu_log("%s: ch=%d addr=" HWADDR_FMT_plx " v=%x\n",
__func__, sid, addr * 4, (unsigned)value));
s->regs[addr] = value;
break;
diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c
index 1ce52ea..8800269 100644
--- a/hw/dma/xlnx_csu_dma.c
+++ b/hw/dma/xlnx_csu_dma.c
@@ -211,7 +211,7 @@
if (result == MEMTX_OK) {
xlnx_csu_dma_data_process(s, buf, len);
} else {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address " TARGET_FMT_plx
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address " HWADDR_FMT_plx
" for mem read", __func__, addr);
s->regs[R_INT_STATUS] |= R_INT_STATUS_AXI_BRESP_ERR_MASK;
xlnx_csu_dma_update_irq(s);
@@ -241,7 +241,7 @@
}
if (result != MEMTX_OK) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address " TARGET_FMT_plx
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address " HWADDR_FMT_plx
" for mem write", __func__, addr);
s->regs[R_INT_STATUS] |= R_INT_STATUS_AXI_BRESP_ERR_MASK;
xlnx_csu_dma_update_irq(s);
diff --git a/hw/i2c/mpc_i2c.c b/hw/i2c/mpc_i2c.c
index 8453925..219c548 100644
--- a/hw/i2c/mpc_i2c.c
+++ b/hw/i2c/mpc_i2c.c
@@ -224,7 +224,7 @@
break;
}
- DPRINTF("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__,
+ DPRINTF("%s: addr " HWADDR_FMT_plx " %02" PRIx32 "\n", __func__,
addr, value);
return (uint64_t)value;
}
@@ -234,7 +234,7 @@
{
MPCI2CState *s = opaque;
- DPRINTF("%s: addr " TARGET_FMT_plx " val %08" PRIx64 "\n", __func__,
+ DPRINTF("%s: addr " HWADDR_FMT_plx " val %08" PRIx64 "\n", __func__,
addr, value);
switch (addr) {
case MPC_I2C_ADR:
diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c
index 963e293..3332712 100644
--- a/hw/i386/multiboot.c
+++ b/hw/i386/multiboot.c
@@ -137,7 +137,7 @@
stl_p(p + MB_MOD_END, end);
stl_p(p + MB_MOD_CMDLINE, cmdline_phys);
- mb_debug("mod%02d: "TARGET_FMT_plx" - "TARGET_FMT_plx,
+ mb_debug("mod%02d: "HWADDR_FMT_plx" - "HWADDR_FMT_plx,
s->mb_mods_count, start, end);
s->mb_mods_count++;
@@ -353,7 +353,7 @@
mb_add_mod(&mbs, mbs.mb_buf_phys + offs,
mbs.mb_buf_phys + offs + mb_mod_length, c);
- mb_debug("mod_start: %p\nmod_end: %p\n cmdline: "TARGET_FMT_plx,
+ mb_debug("mod_start: %p\nmod_end: %p\n cmdline: "HWADDR_FMT_plx,
(char *)mbs.mb_buf + offs,
(char *)mbs.mb_buf + offs + mb_mod_length, c);
g_free(one_file);
@@ -382,8 +382,8 @@
stl_p(bootinfo + MBI_MMAP_ADDR, ADDR_E820_MAP);
mb_debug("multiboot: entry_addr = %#x", mh_entry_addr);
- mb_debug(" mb_buf_phys = "TARGET_FMT_plx, mbs.mb_buf_phys);
- mb_debug(" mod_start = "TARGET_FMT_plx,
+ mb_debug(" mb_buf_phys = "HWADDR_FMT_plx, mbs.mb_buf_phys);
+ mb_debug(" mod_start = "HWADDR_FMT_plx,
mbs.mb_buf_phys + mbs.offset_mods);
mb_debug(" mb_mods_count = %d", mbs.mb_mods_count);
diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
index e4293d6..b9a6f7f 100644
--- a/hw/i386/xen/xen-hvm.c
+++ b/hw/i386/xen/xen-hvm.c
@@ -516,13 +516,13 @@
if (xen_set_mem_type(xen_domid, mem_type,
start_addr >> TARGET_PAGE_BITS,
size >> TARGET_PAGE_BITS)) {
- DPRINTF("xen_set_mem_type error, addr: "TARGET_FMT_plx"\n",
+ DPRINTF("xen_set_mem_type error, addr: "HWADDR_FMT_plx"\n",
start_addr);
}
}
} else {
if (xen_remove_from_physmap(state, start_addr, size) < 0) {
- DPRINTF("physmapping does not exist at "TARGET_FMT_plx"\n", start_addr);
+ DPRINTF("physmapping does not exist at "HWADDR_FMT_plx"\n", start_addr);
}
}
}
@@ -642,8 +642,8 @@
#endif
if (errno == ENODATA) {
memory_region_set_dirty(framebuffer, 0, size);
- DPRINTF("xen: track_dirty_vram failed (0x" TARGET_FMT_plx
- ", 0x" TARGET_FMT_plx "): %s\n",
+ DPRINTF("xen: track_dirty_vram failed (0x" HWADDR_FMT_plx
+ ", 0x" HWADDR_FMT_plx "): %s\n",
start_addr, start_addr + size, strerror(errno));
}
return;
diff --git a/hw/i386/xen/xen-mapcache.c b/hw/i386/xen/xen-mapcache.c
index a2f9309..1d0879d 100644
--- a/hw/i386/xen/xen-mapcache.c
+++ b/hw/i386/xen/xen-mapcache.c
@@ -357,7 +357,7 @@
entry->lock++;
if (entry->lock == 0) {
fprintf(stderr,
- "mapcache entry lock overflow: "TARGET_FMT_plx" -> %p\n",
+ "mapcache entry lock overflow: "HWADDR_FMT_plx" -> %p\n",
entry->paddr_index, entry->vaddr_base);
abort();
}
@@ -404,7 +404,7 @@
if (!found) {
fprintf(stderr, "%s, could not find %p\n", __func__, ptr);
QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) {
- DPRINTF(" "TARGET_FMT_plx" -> %p is present\n", reventry->paddr_index,
+ DPRINTF(" "HWADDR_FMT_plx" -> %p is present\n", reventry->paddr_index,
reventry->vaddr_req);
}
abort();
@@ -445,7 +445,7 @@
if (!found) {
DPRINTF("%s, could not find %p\n", __func__, buffer);
QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) {
- DPRINTF(" "TARGET_FMT_plx" -> %p is present\n", reventry->paddr_index, reventry->vaddr_req);
+ DPRINTF(" "HWADDR_FMT_plx" -> %p is present\n", reventry->paddr_index, reventry->vaddr_req);
}
return;
}
@@ -503,7 +503,7 @@
continue;
}
fprintf(stderr, "Locked DMA mapping while invalidating mapcache!"
- " "TARGET_FMT_plx" -> %p is present\n",
+ " "HWADDR_FMT_plx" -> %p is present\n",
reventry->paddr_index, reventry->vaddr_req);
}
@@ -562,7 +562,7 @@
entry = entry->next;
}
if (!entry) {
- DPRINTF("Trying to update an entry for "TARGET_FMT_plx \
+ DPRINTF("Trying to update an entry for "HWADDR_FMT_plx \
"that is not in the mapcache!\n", old_phys_addr);
return NULL;
}
@@ -570,15 +570,15 @@
address_index = new_phys_addr >> MCACHE_BUCKET_SHIFT;
address_offset = new_phys_addr & (MCACHE_BUCKET_SIZE - 1);
- fprintf(stderr, "Replacing a dummy mapcache entry for "TARGET_FMT_plx \
- " with "TARGET_FMT_plx"\n", old_phys_addr, new_phys_addr);
+ fprintf(stderr, "Replacing a dummy mapcache entry for "HWADDR_FMT_plx \
+ " with "HWADDR_FMT_plx"\n", old_phys_addr, new_phys_addr);
xen_remap_bucket(entry, entry->vaddr_base,
cache_size, address_index, false);
if (!test_bits(address_offset >> XC_PAGE_SHIFT,
test_bit_size >> XC_PAGE_SHIFT,
entry->valid_mapping)) {
- DPRINTF("Unable to update a mapcache entry for "TARGET_FMT_plx"!\n",
+ DPRINTF("Unable to update a mapcache entry for "HWADDR_FMT_plx"!\n",
old_phys_addr);
return NULL;
}
diff --git a/hw/i386/xen/xen_platform.c b/hw/i386/xen/xen_platform.c
index 7db0d94..66e6de3 100644
--- a/hw/i386/xen/xen_platform.c
+++ b/hw/i386/xen/xen_platform.c
@@ -445,7 +445,7 @@
unsigned size)
{
DPRINTF("Warning: attempted read from physical address "
- "0x" TARGET_FMT_plx " in xen platform mmio space\n", addr);
+ "0x" HWADDR_FMT_plx " in xen platform mmio space\n", addr);
return 0;
}
@@ -454,7 +454,7 @@
uint64_t val, unsigned size)
{
DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical "
- "address 0x" TARGET_FMT_plx " in xen platform mmio space\n",
+ "address 0x" HWADDR_FMT_plx " in xen platform mmio space\n",
val, addr);
}
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index d599fef..35e8506 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -564,7 +564,7 @@
/* WO registers, return unknown value */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest read from WO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
*data = 0;
return true;
default:
@@ -773,7 +773,7 @@
/* RO registers, ignore the write */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write to RO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
return true;
default:
return false;
@@ -838,7 +838,7 @@
if (!r) {
qemu_log_mask(LOG_GUEST_ERROR,
- "%s: invalid guest read at offset " TARGET_FMT_plx
+ "%s: invalid guest read at offset " HWADDR_FMT_plx
" size %u\n", __func__, offset, size);
trace_gicv3_dist_badread(offset, size, attrs.secure);
/* The spec requires that reserved registers are RAZ/WI;
@@ -879,7 +879,7 @@
if (!r) {
qemu_log_mask(LOG_GUEST_ERROR,
- "%s: invalid guest write at offset " TARGET_FMT_plx
+ "%s: invalid guest write at offset " HWADDR_FMT_plx
" size %u\n", __func__, offset, size);
trace_gicv3_dist_badwrite(offset, data, size, attrs.secure);
/* The spec requires that reserved registers are RAZ/WI;
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 57c79da..43dfd7a 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -1633,7 +1633,7 @@
/* RO register, ignore the write */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write to RO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
}
break;
case GITS_CREADR + 4:
@@ -1643,7 +1643,7 @@
/* RO register, ignore the write */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write to RO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
}
break;
case GITS_BASER ... GITS_BASER + 0x3f:
@@ -1675,7 +1675,7 @@
/* RO registers, ignore the write */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write to RO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
break;
default:
result = false;
@@ -1785,14 +1785,14 @@
/* RO register, ignore the write */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write to RO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
}
break;
case GITS_TYPER:
/* RO registers, ignore the write */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write to RO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
break;
default:
result = false;
@@ -1851,7 +1851,7 @@
if (!result) {
qemu_log_mask(LOG_GUEST_ERROR,
- "%s: invalid guest read at offset " TARGET_FMT_plx
+ "%s: invalid guest read at offset " HWADDR_FMT_plx
" size %u\n", __func__, offset, size);
trace_gicv3_its_badread(offset, size);
/*
@@ -1887,7 +1887,7 @@
if (!result) {
qemu_log_mask(LOG_GUEST_ERROR,
- "%s: invalid guest write at offset " TARGET_FMT_plx
+ "%s: invalid guest write at offset " HWADDR_FMT_plx
" size %u\n", __func__, offset, size);
trace_gicv3_its_badwrite(offset, data, size);
/*
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index c92ceec..297f7f0 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -601,7 +601,7 @@
/* RO registers, ignore the write */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write to RO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
return MEMTX_OK;
/*
* VLPI frame registers. We don't need a version check for
@@ -668,7 +668,7 @@
/* RO register, ignore the write */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write to RO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
return MEMTX_OK;
/*
* VLPI frame registers. We don't need a version check for
@@ -727,7 +727,7 @@
if (r != MEMTX_OK) {
qemu_log_mask(LOG_GUEST_ERROR,
- "%s: invalid guest read at offset " TARGET_FMT_plx
+ "%s: invalid guest read at offset " HWADDR_FMT_plx
" size %u\n", __func__, offset, size);
trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset,
size, attrs.secure);
@@ -786,7 +786,7 @@
if (r != MEMTX_OK) {
qemu_log_mask(LOG_GUEST_ERROR,
- "%s: invalid guest write at offset " TARGET_FMT_plx
+ "%s: invalid guest write at offset " HWADDR_FMT_plx
" size %u\n", __func__, offset, size);
trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data,
size, attrs.secure);
diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c
index a289510..4ba448f 100644
--- a/hw/intc/exynos4210_combiner.c
+++ b/hw/intc/exynos4210_combiner.c
@@ -120,7 +120,7 @@
default:
if (offset >> 2 >= IIC_REGSET_SIZE) {
hw_error("exynos4210.combiner: overflow of reg_set by 0x"
- TARGET_FMT_plx "offset\n", offset);
+ HWADDR_FMT_plx "offset\n", offset);
}
val = s->reg_set[offset >> 2];
}
@@ -184,19 +184,19 @@
if (req_quad_base_n >= IIC_NGRP) {
hw_error("exynos4210.combiner: unallowed write access at offset 0x"
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
return;
}
if (reg_n > 1) {
hw_error("exynos4210.combiner: unallowed write access at offset 0x"
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
return;
}
if (offset >> 2 >= IIC_REGSET_SIZE) {
hw_error("exynos4210.combiner: overflow of reg_set by 0x"
- TARGET_FMT_plx "offset\n", offset);
+ HWADDR_FMT_plx "offset\n", offset);
}
s->reg_set[offset >> 2] = val;
@@ -246,7 +246,7 @@
break;
default:
hw_error("exynos4210.combiner: unallowed write access at offset 0x"
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
break;
}
}
diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c
index 8a8012f..28d50d9 100644
--- a/hw/misc/auxbus.c
+++ b/hw/misc/auxbus.c
@@ -299,7 +299,7 @@
s = AUX_SLAVE(dev);
- monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n",
+ monitor_printf(mon, "%*smemory " HWADDR_FMT_plx "/" HWADDR_FMT_plx "\n",
indent, "",
object_property_get_uint(OBJECT(s->mmio), "addr", NULL),
memory_region_size(s->mmio));
diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c
index 8270db5..d66d912 100644
--- a/hw/misc/ivshmem.c
+++ b/hw/misc/ivshmem.c
@@ -179,7 +179,7 @@
addr &= 0xfc;
- IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr);
+ IVSHMEM_DPRINTF("writing to addr " HWADDR_FMT_plx "\n", addr);
switch (addr)
{
case INTRMASK:
@@ -207,7 +207,7 @@
}
break;
default:
- IVSHMEM_DPRINTF("Unhandled write " TARGET_FMT_plx "\n", addr);
+ IVSHMEM_DPRINTF("Unhandled write " HWADDR_FMT_plx "\n", addr);
}
}
@@ -233,7 +233,7 @@
break;
default:
- IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr);
+ IVSHMEM_DPRINTF("why are we reading " HWADDR_FMT_plx "\n", addr);
ret = 0;
}
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c
index efcc026..43bb1f5 100644
--- a/hw/misc/macio/mac_dbdma.c
+++ b/hw/misc/macio/mac_dbdma.c
@@ -704,7 +704,7 @@
DBDMA_channel *ch = &s->channels[channel];
int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
- DBDMA_DPRINTFCH(ch, "writel 0x" TARGET_FMT_plx " <= 0x%08"PRIx64"\n",
+ DBDMA_DPRINTFCH(ch, "writel 0x" HWADDR_FMT_plx " <= 0x%08"PRIx64"\n",
addr, value);
DBDMA_DPRINTFCH(ch, "channel 0x%x reg 0x%x\n",
(uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
@@ -786,7 +786,7 @@
break;
}
- DBDMA_DPRINTFCH(ch, "readl 0x" TARGET_FMT_plx " => 0x%08x\n", addr, value);
+ DBDMA_DPRINTFCH(ch, "readl 0x" HWADDR_FMT_plx " => 0x%08x\n", addr, value);
DBDMA_DPRINTFCH(ch, "channel 0x%x reg 0x%x\n",
(uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
diff --git a/hw/misc/mst_fpga.c b/hw/misc/mst_fpga.c
index 2aaadfa..7692825 100644
--- a/hw/misc/mst_fpga.c
+++ b/hw/misc/mst_fpga.c
@@ -131,7 +131,7 @@
return s->pcmcia1;
default:
printf("Mainstone - mst_fpga_readb: Bad register offset "
- "0x" TARGET_FMT_plx "\n", addr);
+ "0x" HWADDR_FMT_plx "\n", addr);
}
return 0;
}
@@ -185,7 +185,7 @@
break;
default:
printf("Mainstone - mst_fpga_writeb: Bad register offset "
- "0x" TARGET_FMT_plx "\n", addr);
+ "0x" HWADDR_FMT_plx "\n", addr);
}
}
diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c
index ecc0245..b861d8f 100644
--- a/hw/net/allwinner-sun8i-emac.c
+++ b/hw/net/allwinner-sun8i-emac.c
@@ -663,7 +663,7 @@
break;
default:
qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown "
- "EMAC register 0x" TARGET_FMT_plx "\n",
+ "EMAC register 0x" HWADDR_FMT_plx "\n",
offset);
}
@@ -760,7 +760,7 @@
break;
default:
qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown "
- "EMAC register 0x" TARGET_FMT_plx "\n",
+ "EMAC register 0x" HWADDR_FMT_plx "\n",
offset);
}
}
diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c
index ddddf35..372e5b6 100644
--- a/hw/net/allwinner_emac.c
+++ b/hw/net/allwinner_emac.c
@@ -304,7 +304,7 @@
default:
qemu_log_mask(LOG_UNIMP,
"allwinner_emac: read access to unknown register 0x"
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
ret = 0;
}
@@ -407,7 +407,7 @@
default:
qemu_log_mask(LOG_UNIMP,
"allwinner_emac: write access to unknown register 0x"
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
}
}
diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c
index b75d8e3..c753bfb 100644
--- a/hw/net/fsl_etsec/etsec.c
+++ b/hw/net/fsl_etsec/etsec.c
@@ -99,7 +99,7 @@
break;
}
- DPRINTF("Read 0x%08x @ 0x" TARGET_FMT_plx
+ DPRINTF("Read 0x%08x @ 0x" HWADDR_FMT_plx
" : %s (%s)\n",
ret, addr, reg->name, reg->desc);
@@ -276,7 +276,7 @@
}
}
- DPRINTF("Write 0x%08x @ 0x" TARGET_FMT_plx
+ DPRINTF("Write 0x%08x @ 0x" HWADDR_FMT_plx
" val:0x%08x->0x%08x : %s (%s)\n",
(unsigned int)value, addr, before, reg->value,
reg->name, reg->desc);
diff --git a/hw/net/fsl_etsec/rings.c b/hw/net/fsl_etsec/rings.c
index a32589e..788463f 100644
--- a/hw/net/fsl_etsec/rings.c
+++ b/hw/net/fsl_etsec/rings.c
@@ -109,7 +109,7 @@
{
assert(bd != NULL);
- RING_DEBUG("READ Buffer Descriptor @ 0x" TARGET_FMT_plx"\n", addr);
+ RING_DEBUG("READ Buffer Descriptor @ 0x" HWADDR_FMT_plx"\n", addr);
cpu_physical_memory_read(addr,
bd,
sizeof(eTSEC_rxtx_bd));
@@ -141,7 +141,7 @@
stl_be_p(&bd->bufptr, bd->bufptr);
}
- RING_DEBUG("Write Buffer Descriptor @ 0x" TARGET_FMT_plx"\n", addr);
+ RING_DEBUG("Write Buffer Descriptor @ 0x" HWADDR_FMT_plx"\n", addr);
cpu_physical_memory_write(addr,
bd,
sizeof(eTSEC_rxtx_bd));
diff --git a/hw/net/pcnet.c b/hw/net/pcnet.c
index e63e524..d456094 100644
--- a/hw/net/pcnet.c
+++ b/hw/net/pcnet.c
@@ -908,11 +908,11 @@
s->csr[37] = nnrd >> 16;
#ifdef PCNET_DEBUG
if (bad) {
- printf("pcnet: BAD RMD RECORDS AFTER 0x" TARGET_FMT_plx "\n",
+ printf("pcnet: BAD RMD RECORDS AFTER 0x" HWADDR_FMT_plx "\n",
crda);
}
} else {
- printf("pcnet: BAD RMD RDA=0x" TARGET_FMT_plx "\n", crda);
+ printf("pcnet: BAD RMD RDA=0x" HWADDR_FMT_plx "\n", crda);
#endif
}
}
diff --git a/hw/net/rocker/rocker.c b/hw/net/rocker/rocker.c
index cf54ddf..7ea8eb6 100644
--- a/hw/net/rocker/rocker.c
+++ b/hw/net/rocker/rocker.c
@@ -815,7 +815,7 @@
}
break;
default:
- DPRINTF("not implemented dma reg write(l) addr=0x" TARGET_FMT_plx
+ DPRINTF("not implemented dma reg write(l) addr=0x" HWADDR_FMT_plx
" val=0x%08x (ring %d, addr=0x%02x)\n",
addr, val, index, offset);
break;
@@ -857,7 +857,7 @@
r->lower32 = 0;
break;
default:
- DPRINTF("not implemented write(l) addr=0x" TARGET_FMT_plx
+ DPRINTF("not implemented write(l) addr=0x" HWADDR_FMT_plx
" val=0x%08x\n", addr, val);
break;
}
@@ -876,8 +876,8 @@
desc_ring_set_base_addr(r->rings[index], val);
break;
default:
- DPRINTF("not implemented dma reg write(q) addr=0x" TARGET_FMT_plx
- " val=0x" TARGET_FMT_plx " (ring %d, offset=0x%02x)\n",
+ DPRINTF("not implemented dma reg write(q) addr=0x" HWADDR_FMT_plx
+ " val=0x" HWADDR_FMT_plx " (ring %d, offset=0x%02x)\n",
addr, val, index, offset);
break;
}
@@ -895,8 +895,8 @@
rocker_port_phys_enable_write(r, val);
break;
default:
- DPRINTF("not implemented write(q) addr=0x" TARGET_FMT_plx
- " val=0x" TARGET_FMT_plx "\n", addr, val);
+ DPRINTF("not implemented write(q) addr=0x" HWADDR_FMT_plx
+ " val=0x" HWADDR_FMT_plx "\n", addr, val);
break;
}
}
@@ -987,8 +987,8 @@
static void rocker_mmio_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
- DPRINTF("Write %s addr " TARGET_FMT_plx
- ", size %u, val " TARGET_FMT_plx "\n",
+ DPRINTF("Write %s addr " HWADDR_FMT_plx
+ ", size %u, val " HWADDR_FMT_plx "\n",
rocker_reg_name(opaque, addr), addr, size, val);
switch (size) {
@@ -1060,7 +1060,7 @@
ret = desc_ring_get_credits(r->rings[index]);
break;
default:
- DPRINTF("not implemented dma reg read(l) addr=0x" TARGET_FMT_plx
+ DPRINTF("not implemented dma reg read(l) addr=0x" HWADDR_FMT_plx
" (ring %d, addr=0x%02x)\n", addr, index, offset);
ret = 0;
break;
@@ -1115,7 +1115,7 @@
ret = (uint32_t)(r->switch_id >> 32);
break;
default:
- DPRINTF("not implemented read(l) addr=0x" TARGET_FMT_plx "\n", addr);
+ DPRINTF("not implemented read(l) addr=0x" HWADDR_FMT_plx "\n", addr);
ret = 0;
break;
}
@@ -1136,7 +1136,7 @@
ret = desc_ring_get_base_addr(r->rings[index]);
break;
default:
- DPRINTF("not implemented dma reg read(q) addr=0x" TARGET_FMT_plx
+ DPRINTF("not implemented dma reg read(q) addr=0x" HWADDR_FMT_plx
" (ring %d, addr=0x%02x)\n", addr, index, offset);
ret = 0;
break;
@@ -1165,7 +1165,7 @@
ret = r->switch_id;
break;
default:
- DPRINTF("not implemented read(q) addr=0x" TARGET_FMT_plx "\n", addr);
+ DPRINTF("not implemented read(q) addr=0x" HWADDR_FMT_plx "\n", addr);
ret = 0;
break;
}
@@ -1174,7 +1174,7 @@
static uint64_t rocker_mmio_read(void *opaque, hwaddr addr, unsigned size)
{
- DPRINTF("Read %s addr " TARGET_FMT_plx ", size %u\n",
+ DPRINTF("Read %s addr " HWADDR_FMT_plx ", size %u\n",
rocker_reg_name(opaque, addr), addr, size);
switch (size) {
diff --git a/hw/net/rocker/rocker_desc.c b/hw/net/rocker/rocker_desc.c
index f3068c9..675383d 100644
--- a/hw/net/rocker/rocker_desc.c
+++ b/hw/net/rocker/rocker_desc.c
@@ -104,7 +104,7 @@
bool desc_ring_set_base_addr(DescRing *ring, uint64_t base_addr)
{
if (base_addr & 0x7) {
- DPRINTF("ERROR: ring[%d] desc base addr (0x" TARGET_FMT_plx
+ DPRINTF("ERROR: ring[%d] desc base addr (0x" HWADDR_FMT_plx
") not 8-byte aligned\n", ring->index, base_addr);
return false;
}
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 990ff3a..7e00965 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -524,7 +524,7 @@
if (addr < ARRAY_SIZE(s->regs)) {
r = s->regs[addr];
}
- DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
+ DENET(qemu_log("%s addr=" HWADDR_FMT_plx " v=%x\n",
__func__, addr * 4, r));
break;
}
@@ -630,7 +630,7 @@
break;
default:
- DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
+ DENET(qemu_log("%s addr=" HWADDR_FMT_plx " v=%x\n",
__func__, addr * 4, (unsigned)value));
if (addr < ARRAY_SIZE(s->regs)) {
s->regs[addr] = value;
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index 6e09f7e..99c2281 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -99,7 +99,7 @@
case R_RX_CTRL1:
case R_RX_CTRL0:
r = s->regs[addr];
- D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr * 4, r));
+ D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr * 4, r));
break;
default:
@@ -125,7 +125,7 @@
if (addr == R_TX_CTRL1)
base = 0x800 / 4;
- D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
+ D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n",
__func__, addr * 4, value));
if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
qemu_send_packet(qemu_get_queue(s->nic),
@@ -155,7 +155,7 @@
case R_TX_LEN0:
case R_TX_LEN1:
case R_TX_GIE0:
- D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
+ D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n",
__func__, addr * 4, value));
s->regs[addr] = value;
break;
diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c
index 870d9ba..e752a21 100644
--- a/hw/pci-bridge/pci_expander_bridge.c
+++ b/hw/pci-bridge/pci_expander_bridge.c
@@ -155,7 +155,7 @@
main_host_sbd = SYS_BUS_DEVICE(main_host);
if (main_host_sbd->num_mmio > 0) {
- return g_strdup_printf(TARGET_FMT_plx ",%x",
+ return g_strdup_printf(HWADDR_FMT_plx ",%x",
main_host_sbd->mmio[0].addr, position + 1);
}
if (main_host_sbd->num_pio > 0) {
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index ac1eebf..1cf25ba 100644
--- a/hw/pci-host/bonito.c
+++ b/hw/pci-host/bonito.c
@@ -251,7 +251,7 @@
saddr = addr >> 2;
- DPRINTF("bonito_writel "TARGET_FMT_plx" val %lx saddr %x\n",
+ DPRINTF("bonito_writel "HWADDR_FMT_plx" val %lx saddr %x\n",
addr, val, saddr);
switch (saddr) {
case BONITO_BONPONCFG:
@@ -314,7 +314,7 @@
saddr = addr >> 2;
- DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr);
+ DPRINTF("bonito_readl "HWADDR_FMT_plx"\n", addr);
switch (saddr) {
case BONITO_INTISR:
return s->regs[saddr];
@@ -339,7 +339,7 @@
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
- DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %lx\n", addr, val);
+ DPRINTF("bonito_pciconf_writel "HWADDR_FMT_plx" val %lx\n", addr, val);
d->config_write(d, addr, val, 4);
}
@@ -350,7 +350,7 @@
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
- DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr);
+ DPRINTF("bonito_pciconf_readl "HWADDR_FMT_plx"\n", addr);
return d->config_read(d, addr, 4);
}
@@ -466,7 +466,7 @@
regno = (cfgaddr & BONITO_PCICONF_REG_MASK_HW) >> BONITO_PCICONF_REG_OFFSET;
if (idsel == 0) {
- error_report("error in bonito pci config address 0x" TARGET_FMT_plx
+ error_report("error in bonito pci config address 0x" HWADDR_FMT_plx
",pcimap_cfg=0x%x", addr, s->regs[BONITO_PCIMAP_CFG]);
exit(1);
}
@@ -486,7 +486,7 @@
uint32_t pciaddr;
uint16_t status;
- DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %lx\n",
+ DPRINTF("bonito_spciconf_write "HWADDR_FMT_plx" size %d val %lx\n",
addr, size, val);
pciaddr = bonito_sbridge_pciaddr(s, addr);
@@ -516,7 +516,7 @@
uint32_t pciaddr;
uint16_t status;
- DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size);
+ DPRINTF("bonito_spciconf_read "HWADDR_FMT_plx" size %d\n", addr, size);
pciaddr = bonito_sbridge_pciaddr(s, addr);
diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c
index 568849e..3881424 100644
--- a/hw/pci-host/ppce500.c
+++ b/hw/pci-host/ppce500.c
@@ -189,7 +189,7 @@
break;
}
- pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
+ pci_debug("%s: win:%lx(addr:" HWADDR_FMT_plx ") -> value:%x\n", __func__,
win, addr, value);
return value;
}
@@ -268,7 +268,7 @@
win = addr & 0xfe0;
- pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
+ pci_debug("%s: value:%x -> win:%lx(addr:" HWADDR_FMT_plx ")\n",
__func__, (unsigned)value, win, addr);
switch (win) {
diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c
index ead1d3e..dfd185b 100644
--- a/hw/pci/pci_host.c
+++ b/hw/pci/pci_host.c
@@ -149,7 +149,7 @@
{
PCIHostState *s = opaque;
- PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n",
+ PCI_DPRINTF("%s addr " HWADDR_FMT_plx " len %d val %"PRIx64"\n",
__func__, addr, len, val);
if (addr != 0 || len != 4) {
return;
@@ -163,7 +163,7 @@
PCIHostState *s = opaque;
uint32_t val = s->config_reg;
- PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n",
+ PCI_DPRINTF("%s addr " HWADDR_FMT_plx " len %d val %"PRIx32"\n",
__func__, addr, len, val);
return val;
}
diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c
index a24c80b..4501fb2 100644
--- a/hw/ppc/ppc4xx_sdram.c
+++ b/hw/ppc/ppc4xx_sdram.c
@@ -500,7 +500,7 @@
bcr = 0x8000;
break;
default:
- error_report("invalid RAM size " TARGET_FMT_plx, ram_size);
+ error_report("invalid RAM size " HWADDR_FMT_plx, ram_size);
return 0;
}
bcr |= ram_base >> 2 & 0xffe00000;
diff --git a/hw/rtc/exynos4210_rtc.c b/hw/rtc/exynos4210_rtc.c
index d1620c7..2b8a38a 100644
--- a/hw/rtc/exynos4210_rtc.c
+++ b/hw/rtc/exynos4210_rtc.c
@@ -374,7 +374,7 @@
default:
qemu_log_mask(LOG_GUEST_ERROR,
- "exynos4210.rtc: bad read offset " TARGET_FMT_plx,
+ "exynos4210.rtc: bad read offset " HWADDR_FMT_plx,
offset);
break;
}
@@ -508,7 +508,7 @@
default:
qemu_log_mask(LOG_GUEST_ERROR,
- "exynos4210.rtc: bad write offset " TARGET_FMT_plx,
+ "exynos4210.rtc: bad write offset " HWADDR_FMT_plx,
offset);
break;
diff --git a/hw/s390x/pv.c b/hw/s390x/pv.c
index 8dfe92d..8a1c714 100644
--- a/hw/s390x/pv.c
+++ b/hw/s390x/pv.c
@@ -20,6 +20,7 @@
#include "exec/confidential-guest-support.h"
#include "hw/s390x/ipl.h"
#include "hw/s390x/pv.h"
+#include "hw/s390x/sclp.h"
#include "target/s390x/kvm/kvm_s390x.h"
static bool info_valid;
@@ -249,6 +250,41 @@
ConfidentialGuestSupportClass parent_class;
};
+/*
+ * If protected virtualization is enabled, the amount of data that the
+ * Read SCP Info Service Call can use is limited to one page. The
+ * available space also depends on the Extended-Length SCCB (ELS)
+ * feature which can take more buffer space to store feature
+ * information. This impacts the maximum number of CPUs supported in
+ * the machine.
+ */
+static uint32_t s390_pv_get_max_cpus(void)
+{
+ int offset_cpu = s390_has_feat(S390_FEAT_EXTENDED_LENGTH_SCCB) ?
+ offsetof(ReadInfo, entries) : SCLP_READ_SCP_INFO_FIXED_CPU_OFFSET;
+
+ return (TARGET_PAGE_SIZE - offset_cpu) / sizeof(CPUEntry);
+}
+
+static bool s390_pv_check_cpus(Error **errp)
+{
+ MachineState *ms = MACHINE(qdev_get_machine());
+ uint32_t pv_max_cpus = s390_pv_get_max_cpus();
+
+ if (ms->smp.max_cpus > pv_max_cpus) {
+ error_setg(errp, "Protected VMs support a maximum of %d CPUs",
+ pv_max_cpus);
+ return false;
+ }
+
+ return true;
+}
+
+static bool s390_pv_guest_check(ConfidentialGuestSupport *cgs, Error **errp)
+{
+ return s390_pv_check_cpus(errp);
+}
+
int s390_pv_kvm_init(ConfidentialGuestSupport *cgs, Error **errp)
{
if (!object_dynamic_cast(OBJECT(cgs), TYPE_S390_PV_GUEST)) {
@@ -261,6 +297,10 @@
return -1;
}
+ if (!s390_pv_guest_check(cgs, errp)) {
+ return -1;
+ }
+
cgs->ready = true;
return 0;
diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c
index c77792d..ebe0fd9 100644
--- a/hw/sh4/sh7750.c
+++ b/hw/sh4/sh7750.c
@@ -207,13 +207,13 @@
static void error_access(const char *kind, hwaddr addr)
{
- fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n",
+ fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") not supported\n",
kind, regname(addr), addr);
}
static void ignore_access(const char *kind, hwaddr addr)
{
- fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n",
+ fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") ignored\n",
kind, regname(addr), addr);
}
diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
index b2819a7..5529276 100644
--- a/hw/ssi/xilinx_spi.c
+++ b/hw/ssi/xilinx_spi.c
@@ -232,7 +232,7 @@
break;
}
- DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, r);
+ DB_PRINT("addr=" HWADDR_FMT_plx " = %x\n", addr * 4, r);
xlx_spi_update_irq(s);
return r;
}
@@ -244,7 +244,7 @@
XilinxSPI *s = opaque;
uint32_t value = val64;
- DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value);
+ DB_PRINT("addr=" HWADDR_FMT_plx " = %x\n", addr, value);
addr >>= 2;
switch (addr) {
case R_SRR:
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 1e9dba2..97009d3 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -887,7 +887,7 @@
case R_INTR_STATUS:
ret = s->regs[addr] & IXR_ALL;
s->regs[addr] = 0;
- DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
+ DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr * 4, ret);
xilinx_spips_update_ixr(s);
return ret;
case R_INTR_MASK:
@@ -916,12 +916,12 @@
if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) {
ret <<= 8 * shortfall;
}
- DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
+ DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr * 4, ret);
xilinx_spips_check_flush(s);
xilinx_spips_update_ixr(s);
return ret;
}
- DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4,
+ DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr * 4,
s->regs[addr] & mask);
return s->regs[addr] & mask;
@@ -971,7 +971,7 @@
XilinxSPIPS *s = opaque;
bool try_flush = true;
- DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
+ DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr, (unsigned)value);
addr >>= 2;
switch (addr) {
case R_CONFIG:
diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c
index d5186f4..973eab4 100644
--- a/hw/timer/digic-timer.c
+++ b/hw/timer/digic-timer.c
@@ -76,7 +76,7 @@
default:
qemu_log_mask(LOG_UNIMP,
"digic-timer: read access to unknown register 0x"
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
}
return ret;
@@ -116,7 +116,7 @@
default:
qemu_log_mask(LOG_UNIMP,
"digic-timer: read access to unknown register 0x"
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
}
}
diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c
index ecc2831..2d6d92e 100644
--- a/hw/timer/etraxfs_timer.c
+++ b/hw/timer/etraxfs_timer.c
@@ -324,8 +324,7 @@
t->rw_ack_intr = 0;
break;
default:
- printf ("%s " TARGET_FMT_plx " %x\n",
- __func__, addr, value);
+ printf("%s " HWADDR_FMT_plx " %x\n", __func__, addr, value);
break;
}
}
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
index e175a9f..c17b247 100644
--- a/hw/timer/exynos4210_mct.c
+++ b/hw/timer/exynos4210_mct.c
@@ -1445,7 +1445,7 @@
case L0_ICNTO: case L1_ICNTO:
case L0_FRCNTO: case L1_FRCNTO:
qemu_log_mask(LOG_GUEST_ERROR,
- "exynos4210.mct: write to RO register " TARGET_FMT_plx,
+ "exynos4210.mct: write to RO register " HWADDR_FMT_plx,
offset);
break;
diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
index 02924a9..3528d0f 100644
--- a/hw/timer/exynos4210_pwm.c
+++ b/hw/timer/exynos4210_pwm.c
@@ -257,7 +257,7 @@
default:
qemu_log_mask(LOG_GUEST_ERROR,
- "exynos4210.pwm: bad read offset " TARGET_FMT_plx,
+ "exynos4210.pwm: bad read offset " HWADDR_FMT_plx,
offset);
break;
}
@@ -352,7 +352,7 @@
default:
qemu_log_mask(LOG_GUEST_ERROR,
- "exynos4210.pwm: bad write offset " TARGET_FMT_plx,
+ "exynos4210.pwm: bad write offset " HWADDR_FMT_plx,
offset);
break;
diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c
index 103260e..23ba625 100644
--- a/hw/virtio/virtio-mmio.c
+++ b/hw/virtio/virtio-mmio.c
@@ -829,10 +829,10 @@
assert(section.mr);
if (proxy_path) {
- path = g_strdup_printf("%s/virtio-mmio@" TARGET_FMT_plx, proxy_path,
+ path = g_strdup_printf("%s/virtio-mmio@" HWADDR_FMT_plx, proxy_path,
section.offset_within_address_space);
} else {
- path = g_strdup_printf("virtio-mmio@" TARGET_FMT_plx,
+ path = g_strdup_printf("virtio-mmio@" HWADDR_FMT_plx,
section.offset_within_address_space);
}
memory_region_unref(section.mr);
diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c
index 0ec7e52..8db0532 100644
--- a/hw/xen/xen_pt.c
+++ b/hw/xen/xen_pt.c
@@ -434,7 +434,7 @@
PCIDevice *d = o;
/* if this function is called, that probably means that there is a
* misconfiguration of the IOMMU. */
- XEN_PT_ERR(d, "Should not read BAR through QEMU. @0x"TARGET_FMT_plx"\n",
+ XEN_PT_ERR(d, "Should not read BAR through QEMU. @0x"HWADDR_FMT_plx"\n",
addr);
return 0;
}
@@ -443,7 +443,7 @@
{
PCIDevice *d = o;
/* Same comment as xen_pt_bar_read function */
- XEN_PT_ERR(d, "Should not write BAR through QEMU. @0x"TARGET_FMT_plx"\n",
+ XEN_PT_ERR(d, "Should not write BAR through QEMU. @0x"HWADDR_FMT_plx"\n",
addr);
}
diff --git a/include/exec/hwaddr.h b/include/exec/hwaddr.h
index 8f16d17..50fbb2d 100644
--- a/include/exec/hwaddr.h
+++ b/include/exec/hwaddr.h
@@ -10,7 +10,7 @@
typedef uint64_t hwaddr;
#define HWADDR_MAX UINT64_MAX
-#define TARGET_FMT_plx "%016" PRIx64
+#define HWADDR_FMT_plx "%016" PRIx64
#define HWADDR_PRId PRId64
#define HWADDR_PRIi PRIi64
#define HWADDR_PRIo PRIo64
diff --git a/monitor/misc.c b/monitor/misc.c
index bf3f1c6..fa0a42c 100644
--- a/monitor/misc.c
+++ b/monitor/misc.c
@@ -566,7 +566,7 @@
while (len > 0) {
if (is_physical) {
- monitor_printf(mon, TARGET_FMT_plx ":", addr);
+ monitor_printf(mon, HWADDR_FMT_plx ":", addr);
} else {
monitor_printf(mon, TARGET_FMT_lx ":", (target_ulong)addr);
}
diff --git a/softmmu/memory.c b/softmmu/memory.c
index e05332d..9d64efc 100644
--- a/softmmu/memory.c
+++ b/softmmu/memory.c
@@ -1281,7 +1281,7 @@
unsigned size)
{
#ifdef DEBUG_UNASSIGNED
- printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
+ printf("Unassigned mem read " HWADDR_FMT_plx "\n", addr);
#endif
return 0;
}
@@ -1290,7 +1290,7 @@
uint64_t val, unsigned size)
{
#ifdef DEBUG_UNASSIGNED
- printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
+ printf("Unassigned mem write " HWADDR_FMT_plx " = 0x%"PRIx64"\n", addr, val);
#endif
}
@@ -3220,9 +3220,9 @@
for (i = 0; i < level; i++) {
qemu_printf(MTREE_INDENT);
}
- qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
- " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
- "-" TARGET_FMT_plx "%s",
+ qemu_printf(HWADDR_FMT_plx "-" HWADDR_FMT_plx
+ " (prio %d, %s%s): alias %s @%s " HWADDR_FMT_plx
+ "-" HWADDR_FMT_plx "%s",
cur_start, cur_end,
mr->priority,
mr->nonvolatile ? "nv-" : "",
@@ -3242,7 +3242,7 @@
for (i = 0; i < level; i++) {
qemu_printf(MTREE_INDENT);
}
- qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
+ qemu_printf(HWADDR_FMT_plx "-" HWADDR_FMT_plx
" (prio %d, %s%s): %s%s",
cur_start, cur_end,
mr->priority,
@@ -3329,8 +3329,8 @@
while (n--) {
mr = range->mr;
if (range->offset_in_region) {
- qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
- " (prio %d, %s%s): %s @" TARGET_FMT_plx,
+ qemu_printf(MTREE_INDENT HWADDR_FMT_plx "-" HWADDR_FMT_plx
+ " (prio %d, %s%s): %s @" HWADDR_FMT_plx,
int128_get64(range->addr.start),
int128_get64(range->addr.start)
+ MR_SIZE(range->addr.size),
@@ -3340,7 +3340,7 @@
memory_region_name(mr),
range->offset_in_region);
} else {
- qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
+ qemu_printf(MTREE_INDENT HWADDR_FMT_plx "-" HWADDR_FMT_plx
" (prio %d, %s%s): %s",
int128_get64(range->addr.start),
int128_get64(range->addr.start)
diff --git a/softmmu/memory_mapping.c b/softmmu/memory_mapping.c
index f6f0a82..d7f1d09 100644
--- a/softmmu/memory_mapping.c
+++ b/softmmu/memory_mapping.c
@@ -241,8 +241,8 @@
}
#ifdef DEBUG_GUEST_PHYS_REGION_ADD
- fprintf(stderr, "%s: target_start=" TARGET_FMT_plx " target_end="
- TARGET_FMT_plx ": %s (count: %u)\n", __func__, target_start,
+ fprintf(stderr, "%s: target_start=" HWADDR_FMT_plx " target_end="
+ HWADDR_FMT_plx ": %s (count: %u)\n", __func__, target_start,
target_end, predecessor ? "joined" : "added", g->list->num);
#endif
}
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index edec095..bf585e4 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -2475,7 +2475,7 @@
MemTxResult res;
#if defined(DEBUG_SUBPAGE)
- printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
+ printf("%s: subpage %p len %u addr " HWADDR_FMT_plx "\n", __func__,
subpage, len, addr);
#endif
res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len);
@@ -2493,7 +2493,7 @@
uint8_t buf[8];
#if defined(DEBUG_SUBPAGE)
- printf("%s: subpage %p len %u addr " TARGET_FMT_plx
+ printf("%s: subpage %p len %u addr " HWADDR_FMT_plx
" value %"PRIx64"\n",
__func__, subpage, len, addr, value);
#endif
@@ -2507,7 +2507,7 @@
{
subpage_t *subpage = opaque;
#if defined(DEBUG_SUBPAGE)
- printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
+ printf("%s: subpage %p %c len %u addr " HWADDR_FMT_plx "\n",
__func__, subpage, is_write ? 'w' : 'r', len, addr);
#endif
@@ -2558,7 +2558,7 @@
NULL, TARGET_PAGE_SIZE);
mmio->iomem.subpage = true;
#if defined(DEBUG_SUBPAGE)
- printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
+ printf("%s: %p base " HWADDR_FMT_plx " len %08x\n", __func__,
mmio, base, TARGET_PAGE_SIZE);
#endif
@@ -3703,7 +3703,7 @@
const char *names[] = { " [unassigned]", " [not dirty]",
" [ROM]", " [watch]" };
- qemu_printf(" #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx
+ qemu_printf(" #%d @" HWADDR_FMT_plx ".." HWADDR_FMT_plx
" %s%s%s%s%s",
i,
s->offset_within_address_space,
diff --git a/target/i386/monitor.c b/target/i386/monitor.c
index 8e4b4d6..ad5b7b8 100644
--- a/target/i386/monitor.c
+++ b/target/i386/monitor.c
@@ -57,7 +57,7 @@
{
addr = addr_canonical(env, addr);
- monitor_printf(mon, TARGET_FMT_plx ": " TARGET_FMT_plx
+ monitor_printf(mon, HWADDR_FMT_plx ": " HWADDR_FMT_plx
" %c%c%c%c%c%c%c%c%c\n",
addr,
pte & mask,
@@ -258,8 +258,8 @@
prot1 = *plast_prot;
if (prot != prot1) {
if (*pstart != -1) {
- monitor_printf(mon, TARGET_FMT_plx "-" TARGET_FMT_plx " "
- TARGET_FMT_plx " %c%c%c\n",
+ monitor_printf(mon, HWADDR_FMT_plx "-" HWADDR_FMT_plx " "
+ HWADDR_FMT_plx " %c%c%c\n",
addr_canonical(env, *pstart),
addr_canonical(env, end),
addr_canonical(env, end - *pstart),
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index c6d1de5..cce1db1 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -655,7 +655,7 @@
physical & TARGET_PAGE_MASK, prot,
mmu_idx, TARGET_PAGE_SIZE);
qemu_log_mask(CPU_LOG_MMU,
- "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
+ "%s address=%" VADDR_PRIx " physical " HWADDR_FMT_plx
" prot %d\n", __func__, address, physical, prot);
return true;
} else {
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index 5b745d0..f637803 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -403,7 +403,7 @@
CPUMBState *env = &cpu->env;
qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx
- " physaddr 0x" TARGET_FMT_plx " size %d access type %s\n",
+ " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n",
addr, physaddr, size,
access_type == MMU_INST_FETCH ? "INST_FETCH" :
(access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE"));
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
index 9d16859..e5e1e9d 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -924,7 +924,7 @@
switch (ret) {
case TLBRET_MATCH:
qemu_log_mask(CPU_LOG_MMU,
- "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
+ "%s address=%" VADDR_PRIx " physical " HWADDR_FMT_plx
" prot %d\n", __func__, address, physical, prot);
break;
default:
diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c
index cc091c3..3976416 100644
--- a/target/ppc/mmu-hash32.c
+++ b/target/ppc/mmu-hash32.c
@@ -346,24 +346,24 @@
ptem = (vsid << 7) | (pgidx >> 10);
/* Page address translation */
- qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx
- " htab_mask " TARGET_FMT_plx
- " hash " TARGET_FMT_plx "\n",
+ qemu_log_mask(CPU_LOG_MMU, "htab_base " HWADDR_FMT_plx
+ " htab_mask " HWADDR_FMT_plx
+ " hash " HWADDR_FMT_plx "\n",
ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), hash);
/* Primary PTEG lookup */
- qemu_log_mask(CPU_LOG_MMU, "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "0 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx
" vsid=%" PRIx32 " ptem=%" PRIx32
- " hash=" TARGET_FMT_plx "\n",
+ " hash=" HWADDR_FMT_plx "\n",
ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu),
vsid, ptem, hash);
pteg_off = get_pteg_offset32(cpu, hash);
pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 0, ptem, pte);
if (pte_offset == -1) {
/* Secondary PTEG lookup */
- qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "1 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx
" vsid=%" PRIx32 " api=%" PRIx32
- " hash=" TARGET_FMT_plx "\n", ppc_hash32_hpt_base(cpu),
+ " hash=" HWADDR_FMT_plx "\n", ppc_hash32_hpt_base(cpu),
ppc_hash32_hpt_mask(cpu), vsid, ptem, ~hash);
pteg_off = get_pteg_offset32(cpu, ~hash);
pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 1, ptem, pte);
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index b9b31fd..900f906 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -697,15 +697,15 @@
/* Page address translation */
qemu_log_mask(CPU_LOG_MMU,
- "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
- " hash " TARGET_FMT_plx "\n",
+ "htab_base " HWADDR_FMT_plx " htab_mask " HWADDR_FMT_plx
+ " hash " HWADDR_FMT_plx "\n",
ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), hash);
/* Primary PTEG lookup */
qemu_log_mask(CPU_LOG_MMU,
- "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+ "0 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx
" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
- " hash=" TARGET_FMT_plx "\n",
+ " hash=" HWADDR_FMT_plx "\n",
ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu),
vsid, ptem, hash);
ptex = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift);
@@ -714,9 +714,9 @@
/* Secondary PTEG lookup */
ptem |= HPTE64_V_SECONDARY;
qemu_log_mask(CPU_LOG_MMU,
- "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+ "1 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx
" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
- " hash=" TARGET_FMT_plx "\n", ppc_hash64_hpt_base(cpu),
+ " hash=" HWADDR_FMT_plx "\n", ppc_hash64_hpt_base(cpu),
ppc_hash64_hpt_mask(cpu), vsid, ptem, ~hash);
ptex = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift);
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 8901f4d..7235a4b 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -252,7 +252,7 @@
}
if (best != -1) {
done:
- qemu_log_mask(CPU_LOG_MMU, "found TLB at addr " TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "found TLB at addr " HWADDR_FMT_plx
" prot=%01x ret=%d\n",
ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
/* Update page flags */
@@ -328,7 +328,7 @@
ctx->prot = prot;
ret = check_prot(ctx->prot, access_type);
if (ret == 0) {
- qemu_log_mask(CPU_LOG_MMU, "BAT %d match: r " TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "BAT %d match: r " HWADDR_FMT_plx
" prot=%c%c\n", i, ctx->raddr,
ctx->prot & PAGE_READ ? 'R' : '-',
ctx->prot & PAGE_WRITE ? 'W' : '-');
@@ -403,9 +403,9 @@
/* Check if instruction fetch is allowed, if needed */
if (type != ACCESS_CODE || ctx->nx == 0) {
/* Page address translation */
- qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx
- " htab_mask " TARGET_FMT_plx
- " hash " TARGET_FMT_plx "\n",
+ qemu_log_mask(CPU_LOG_MMU, "htab_base " HWADDR_FMT_plx
+ " htab_mask " HWADDR_FMT_plx
+ " hash " HWADDR_FMT_plx "\n",
ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), hash);
ctx->hash[0] = hash;
ctx->hash[1] = ~hash;
@@ -420,7 +420,7 @@
hwaddr curaddr;
uint32_t a0, a1, a2, a3;
- qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
+ qemu_log("Page table: " HWADDR_FMT_plx " len " HWADDR_FMT_plx
"\n", ppc_hash32_hpt_base(cpu),
ppc_hash32_hpt_mask(cpu) + 0x80);
for (curaddr = ppc_hash32_hpt_base(cpu);
@@ -432,7 +432,7 @@
a2 = ldl_phys(cs->as, curaddr + 8);
a3 = ldl_phys(cs->as, curaddr + 12);
if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
- qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
+ qemu_log(HWADDR_FMT_plx ": %08x %08x %08x %08x\n",
curaddr, a0, a1, a2, a3);
}
}
@@ -578,14 +578,14 @@
if (ret >= 0) {
ctx->raddr = raddr;
qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
- " => " TARGET_FMT_plx
+ " => " HWADDR_FMT_plx
" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
ret);
return 0;
}
}
qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
- " => " TARGET_FMT_plx
+ " => " HWADDR_FMT_plx
" %d %d\n", __func__, address, raddr, ctx->prot, ret);
return ret;
@@ -666,11 +666,11 @@
if (ret >= 0) {
ctx->raddr = raddr;
qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
- " => " TARGET_FMT_plx " %d %d\n", __func__,
+ " => " HWADDR_FMT_plx " %d %d\n", __func__,
address, ctx->raddr, ctx->prot, ret);
} else {
qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
- " => " TARGET_FMT_plx " %d %d\n", __func__,
+ " => " HWADDR_FMT_plx " %d %d\n", __func__,
address, raddr, ctx->prot, ret);
}
@@ -894,11 +894,11 @@
if (ret >= 0) {
ctx->raddr = raddr;
qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
- " => " TARGET_FMT_plx " %d %d\n", __func__, address,
+ " => " HWADDR_FMT_plx " %d %d\n", __func__, address,
ctx->raddr, ctx->prot, ret);
} else {
qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
- " => " TARGET_FMT_plx " %d %d\n", __func__, address,
+ " => " HWADDR_FMT_plx " %d %d\n", __func__, address,
raddr, ctx->prot, ret);
}
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 2a91f3f..64e3043 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -826,7 +826,7 @@
tlb->prot &= ~PAGE_VALID;
}
tlb->PID = env->spr[SPR_40x_PID]; /* PID */
- qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " HWADDR_FMT_plx
" EPN " TARGET_FMT_lx " size " TARGET_FMT_lx
" prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
@@ -864,7 +864,7 @@
if (val & PPC4XX_TLBLO_WR) {
tlb->prot |= PAGE_WRITE;
}
- qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " HWADDR_FMT_plx
" EPN " TARGET_FMT_lx
" size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 8ea3442..9a28816 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1272,7 +1272,7 @@
qemu_log_mask(CPU_LOG_MMU,
"%s 1st-stage address=%" VADDR_PRIx " ret %d physical "
- TARGET_FMT_plx " prot %d\n",
+ HWADDR_FMT_plx " prot %d\n",
__func__, address, ret, pa, prot);
if (ret == TRANSLATE_SUCCESS) {
@@ -1285,7 +1285,7 @@
qemu_log_mask(CPU_LOG_MMU,
"%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
- TARGET_FMT_plx " prot %d\n",
+ HWADDR_FMT_plx " prot %d\n",
__func__, im_address, ret, pa, prot2);
prot &= prot2;
@@ -1295,7 +1295,7 @@
size, access_type, mode);
qemu_log_mask(CPU_LOG_MMU,
- "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+ "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
" %d tlb_size " TARGET_FMT_lu "\n",
__func__, pa, ret, prot_pmp, tlb_size);
@@ -1320,7 +1320,7 @@
qemu_log_mask(CPU_LOG_MMU,
"%s address=%" VADDR_PRIx " ret %d physical "
- TARGET_FMT_plx " prot %d\n",
+ HWADDR_FMT_plx " prot %d\n",
__func__, address, ret, pa, prot);
if (ret == TRANSLATE_SUCCESS) {
@@ -1328,7 +1328,7 @@
size, access_type, mode);
qemu_log_mask(CPU_LOG_MMU,
- "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+ "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
" %d tlb_size " TARGET_FMT_lu "\n",
__func__, pa, ret, prot_pmp, tlb_size);
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index 17e63fa..236f93b 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -64,7 +64,7 @@
return;
}
- monitor_printf(mon, TARGET_FMT_lx " " TARGET_FMT_plx " " TARGET_FMT_lx
+ monitor_printf(mon, TARGET_FMT_lx " " HWADDR_FMT_plx " " TARGET_FMT_lx
" %c%c%c%c%c%c%c\n",
addr_canonical(va_bits, vaddr),
paddr, size,
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index ec4fae7..a53580d 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -430,12 +430,12 @@
#ifdef DEBUG_UNASSIGNED
if (is_asi) {
- printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
+ printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx
" asi 0x%02x from " TARGET_FMT_lx "\n",
is_exec ? "exec" : is_write ? "write" : "read", size,
size == 1 ? "" : "s", addr, is_asi, env->pc);
} else {
- printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
+ printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx
" from " TARGET_FMT_lx "\n",
is_exec ? "exec" : is_write ? "write" : "read", size,
size == 1 ? "" : "s", addr, env->pc);
@@ -490,7 +490,7 @@
CPUSPARCState *env = &cpu->env;
#ifdef DEBUG_UNASSIGNED
- printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
+ printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx
"\n", addr, env->pc);
#endif
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 919448a..158ec2a 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -230,7 +230,7 @@
if (likely(error_code == 0)) {
qemu_log_mask(CPU_LOG_MMU,
"Translate at %" VADDR_PRIx " -> "
- TARGET_FMT_plx ", vaddr " TARGET_FMT_lx "\n",
+ HWADDR_FMT_plx ", vaddr " TARGET_FMT_lx "\n",
address, paddr, vaddr);
tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
return true;
@@ -356,27 +356,27 @@
hwaddr pa;
uint32_t pde;
- qemu_printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
+ qemu_printf("Root ptr: " HWADDR_FMT_plx ", ctx: %d\n",
(hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]);
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
pde = mmu_probe(env, va, 2);
if (pde) {
pa = cpu_get_phys_page_debug(cs, va);
- qemu_printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
+ qemu_printf("VA: " TARGET_FMT_lx ", PA: " HWADDR_FMT_plx
" PDE: " TARGET_FMT_lx "\n", va, pa, pde);
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
pde = mmu_probe(env, va1, 1);
if (pde) {
pa = cpu_get_phys_page_debug(cs, va1);
qemu_printf(" VA: " TARGET_FMT_lx ", PA: "
- TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n",
+ HWADDR_FMT_plx " PDE: " TARGET_FMT_lx "\n",
va1, pa, pde);
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
pde = mmu_probe(env, va2, 0);
if (pde) {
pa = cpu_get_phys_page_debug(cs, va2);
qemu_printf(" VA: " TARGET_FMT_lx ", PA: "
- TARGET_FMT_plx " PTE: "
+ HWADDR_FMT_plx " PTE: "
TARGET_FMT_lx "\n",
va2, pa, pde);
}
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index 1db3280..114685c 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -79,7 +79,7 @@
address, rw, mmu_idx);
qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical "
- TARGET_FMT_plx " prot %d\n",
+ HWADDR_FMT_plx " prot %d\n",
__func__, (target_ulong)address, ret, physical, prot);
if (ret == TLBRET_MATCH) {
diff --git a/tests/qtest/e1000e-test.c b/tests/qtest/e1000e-test.c
index 3fc9204..b63a4d3 100644
--- a/tests/qtest/e1000e-test.c
+++ b/tests/qtest/e1000e-test.c
@@ -1,4 +1,4 @@
- /*
+/*
* QTest testcase for e1000e NIC
*
* Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
diff --git a/tests/qtest/libqos/e1000e.c b/tests/qtest/libqos/e1000e.c
index 37c794b..28fb305 100644
--- a/tests/qtest/libqos/e1000e.c
+++ b/tests/qtest/libqos/e1000e.c
@@ -51,13 +51,13 @@
void e1000e_tx_ring_push(QE1000E *d, void *descr)
{
QE1000E_PCI *d_pci = container_of(d, QE1000E_PCI, e1000e);
- uint32_t tail = e1000e_macreg_read(d, E1000E_TDT);
- uint32_t len = e1000e_macreg_read(d, E1000E_TDLEN) / E1000_RING_DESC_LEN;
+ uint32_t tail = e1000e_macreg_read(d, E1000_TDT);
+ uint32_t len = e1000e_macreg_read(d, E1000_TDLEN) / E1000_RING_DESC_LEN;
qtest_memwrite(d_pci->pci_dev.bus->qts,
d->tx_ring + tail * E1000_RING_DESC_LEN,
descr, E1000_RING_DESC_LEN);
- e1000e_macreg_write(d, E1000E_TDT, (tail + 1) % len);
+ e1000e_macreg_write(d, E1000_TDT, (tail + 1) % len);
/* Read WB data for the packet transmitted */
qtest_memread(d_pci->pci_dev.bus->qts,
@@ -68,13 +68,13 @@
void e1000e_rx_ring_push(QE1000E *d, void *descr)
{
QE1000E_PCI *d_pci = container_of(d, QE1000E_PCI, e1000e);
- uint32_t tail = e1000e_macreg_read(d, E1000E_RDT);
- uint32_t len = e1000e_macreg_read(d, E1000E_RDLEN) / E1000_RING_DESC_LEN;
+ uint32_t tail = e1000e_macreg_read(d, E1000_RDT);
+ uint32_t len = e1000e_macreg_read(d, E1000_RDLEN) / E1000_RING_DESC_LEN;
qtest_memwrite(d_pci->pci_dev.bus->qts,
d->rx_ring + tail * E1000_RING_DESC_LEN,
descr, E1000_RING_DESC_LEN);
- e1000e_macreg_write(d, E1000E_RDT, (tail + 1) % len);
+ e1000e_macreg_write(d, E1000_RDT, (tail + 1) % len);
/* Read WB data for the packet received */
qtest_memread(d_pci->pci_dev.bus->qts,
@@ -145,8 +145,8 @@
(uint32_t) d->e1000e.tx_ring);
e1000e_macreg_write(&d->e1000e, E1000_TDBAH,
(uint32_t) (d->e1000e.tx_ring >> 32));
- e1000e_macreg_write(&d->e1000e, E1000E_TDLEN, E1000E_RING_LEN);
- e1000e_macreg_write(&d->e1000e, E1000E_TDT, 0);
+ e1000e_macreg_write(&d->e1000e, E1000_TDLEN, E1000E_RING_LEN);
+ e1000e_macreg_write(&d->e1000e, E1000_TDT, 0);
e1000e_macreg_write(&d->e1000e, E1000_TDH, 0);
/* Enable transmit */
@@ -156,8 +156,8 @@
(uint32_t)d->e1000e.rx_ring);
e1000e_macreg_write(&d->e1000e, E1000_RDBAH,
(uint32_t)(d->e1000e.rx_ring >> 32));
- e1000e_macreg_write(&d->e1000e, E1000E_RDLEN, E1000E_RING_LEN);
- e1000e_macreg_write(&d->e1000e, E1000E_RDT, 0);
+ e1000e_macreg_write(&d->e1000e, E1000_RDLEN, E1000E_RING_LEN);
+ e1000e_macreg_write(&d->e1000e, E1000_RDT, 0);
e1000e_macreg_write(&d->e1000e, E1000_RDH, 0);
/* Enable receive */
@@ -222,8 +222,10 @@
.device_id = E1000_DEV_ID_82574L,
};
- /* FIXME: every test using this node needs to setup a -netdev socket,id=hs0
- * otherwise QEMU is not going to start */
+ /*
+ * FIXME: every test using this node needs to setup a -netdev socket,id=hs0
+ * otherwise QEMU is not going to start
+ */
QOSGraphEdgeOptions opts = {
.extra_device_opts = "netdev=hs0",
};
diff --git a/tests/qtest/libqos/e1000e.h b/tests/qtest/libqos/e1000e.h
index 3bf285a..091ce13 100644
--- a/tests/qtest/libqos/e1000e.h
+++ b/tests/qtest/libqos/e1000e.h
@@ -25,11 +25,6 @@
#define E1000E_RX0_MSG_ID (0)
#define E1000E_TX0_MSG_ID (1)
-#define E1000E_TDLEN (0x3808)
-#define E1000E_TDT (0x3818)
-#define E1000E_RDLEN (0x2808)
-#define E1000E_RDT (0x2818)
-
typedef struct QE1000E QE1000E;
typedef struct QE1000E_PCI QE1000E_PCI;
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index f0ebb5f..1af63f8 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -207,11 +207,11 @@
(config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \
(config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \
(config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
+ (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
['arm-cpu-features',
'numa-test',
'boot-serial-test',
- 'migration-test',
- 'bcm2835-dma-test']
+ 'migration-test']
qtests_s390x = \
(slirp.found() ? ['pxe-test', 'test-netfilter'] : []) + \
diff --git a/tests/vm/haiku.x86_64 b/tests/vm/haiku.x86_64
index 29668bc..71cf75a 100755
--- a/tests/vm/haiku.x86_64
+++ b/tests/vm/haiku.x86_64
@@ -48,8 +48,8 @@
name = "haiku"
arch = "x86_64"
- link = "https://app.vagrantup.com/haiku-os/boxes/r1beta3-x86_64/versions/20220216/providers/libvirt.box"
- csum = "e67d4aacbcc687013d5cc91990ddd86cc5d70a5d28432ae2691944f8ce5d5041"
+ link = "https://app.vagrantup.com/haiku-os/boxes/r1beta4-x86_64/versions/20230114/providers/libvirt.box"
+ csum = "6e72a2a470e03dbc3c5e808664e057bb4022b390dca88e4c7da6188f26f6a3c9"
poweroff = "shutdown"
@@ -80,13 +80,12 @@
"ninja",
]
- # https://dev.haiku-os.org/ticket/16512 virtio disk1 shows up as 0 (reversed order)
BUILD_SCRIPT = """
set -e;
rm -rf /tmp/qemu-test.*
cd $(mktemp -d /tmp/qemu-test.XXXXXX);
mkdir src build; cd src;
- tar -xf /dev/disk/virtual/virtio_block/0/raw;
+ tar -xf /dev/disk/virtual/virtio_block/1/raw;
mkdir -p /usr/bin
ln -s /boot/system/bin/env /usr/bin/env
cd ../build
