Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
virtio,pc,pci: features, cleanups, fixes
more memslots support in libvhost-user
support PCIe Gen5/Gen6 link speeds in pcie
more traces in vdpa
network simulation devices support in vdpa
SMBIOS type 9 descriptor implementation
Bump max_cpus to 4096 vcpus in q35
aw-bits and granule options in VIRTIO-IOMMU
Support report NUMA nodes for device memory using GI in acpi
Beginning of shutdown event support in pvpanic
fixes, cleanups all over the place.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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# gpg: Signature made Tue 12 Mar 2024 22:03:31 GMT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (68 commits)
docs/specs/pvpanic: document shutdown event
hw/cxl: Fix missing reserved data in CXL Device DVSEC
hmat acpi: Fix out of bounds access due to missing use of indirection
hmat acpi: Do not add Memory Proximity Domain Attributes Structure targetting non existent memory.
qemu-options.hx: Document the virtio-iommu-pci aw-bits option
hw/arm/virt: Set virtio-iommu aw-bits default value to 48
hw/i386/q35: Set virtio-iommu aw-bits default value to 39
virtio-iommu: Add an option to define the input range width
virtio-iommu: Trace domain range limits as unsigned int
qemu-options.hx: Document the virtio-iommu-pci granule option
virtio-iommu: Change the default granule to the host page size
virtio-iommu: Add a granule property
hw/i386/acpi-build: Add support for SRAT Generic Initiator structures
hw/acpi: Implement the SRAT GI affinity structure
qom: new object to associate device to NUMA node
hw/i386/pc: Inline pc_cmos_init() into pc_cmos_init_late() and remove it
hw/i386/pc: Set "normal" boot device order in pc_basic_device_init()
hw/i386/pc: Avoid one use of the current_machine global
hw/i386/pc: Remove "rtc_state" link again
Revert "hw/i386/pc: Confine system flash handling to pc_sysfw"
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts:
# hw/core/machine.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 5abf6f5..409d7db 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -316,7 +316,6 @@
PowerPC TCG CPUs
M: Nicholas Piggin <npiggin@gmail.com>
M: Daniel Henrique Barboza <danielhb413@gmail.com>
-R: Cédric Le Goater <clg@kaod.org>
L: qemu-ppc@nongnu.org
S: Odd Fixes
F: target/ppc/
@@ -468,7 +467,6 @@
PPC KVM CPUs
M: Nicholas Piggin <npiggin@gmail.com>
R: Daniel Henrique Barboza <danielhb413@gmail.com>
-R: Cédric Le Goater <clg@kaod.org>
S: Odd Fixes
F: target/ppc/kvm.c
@@ -1508,7 +1506,6 @@
sPAPR (pseries)
M: Nicholas Piggin <npiggin@gmail.com>
R: Daniel Henrique Barboza <danielhb413@gmail.com>
-R: Cédric Le Goater <clg@kaod.org>
R: David Gibson <david@gibson.dropbear.id.au>
R: Harsh Prateek Bora <harshpb@linux.ibm.com>
L: qemu-ppc@nongnu.org
@@ -1575,6 +1572,7 @@
F: pc-bios/canyonlands.dt[sb]
F: pc-bios/u-boot-sam460ex-20100605.bin
F: roms/u-boot-sam460ex
+F: docs/system/ppc/amigang.rst
pegasos2
M: BALATON Zoltan <balaton@eik.bme.hu>
@@ -2412,6 +2410,7 @@
nvme
M: Keith Busch <kbusch@kernel.org>
M: Klaus Jensen <its@irrelevant.dk>
+R: Jesper Devantier <foss@defmacro.it>
L: qemu-block@nongnu.org
S: Supported
F: hw/nvme/*
@@ -2508,6 +2507,12 @@
F: hw/i2c/i2c_mux_pca954x.c
F: include/hw/i2c/i2c_mux_pca954x.h
+pcf8574
+M: Dmitrii Sharikhin <d.sharikhin@yadro.com>
+S: Maintained
+F: hw/gpio/pcf8574.c
+F: include/gpio/pcf8574.h
+
Generic Loader
M: Alistair Francis <alistair@alistair23.me>
S: Maintained
@@ -3592,6 +3597,7 @@
elf2dmp
M: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
+R: Akihiko Odaki <akihiko.odaki@daynix.com>
S: Maintained
F: contrib/elf2dmp/
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 52239a4..5c70748 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -436,7 +436,6 @@
static inline TranslationBlock * QEMU_DISABLE_CFI
cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
{
- CPUArchState *env = cpu_env(cpu);
uintptr_t ret;
TranslationBlock *last_tb;
const void *tb_ptr = itb->tc.ptr;
@@ -446,7 +445,7 @@
}
qemu_thread_jit_execute();
- ret = tcg_qemu_tb_exec(env, tb_ptr);
+ ret = tcg_qemu_tb_exec(cpu_env(cpu), tb_ptr);
cpu->neg.can_do_io = true;
qemu_plugin_disable_mem_helpers(cpu);
/*
diff --git a/backends/iommufd.c b/backends/iommufd.c
index 1ef683c..62a79fa 100644
--- a/backends/iommufd.c
+++ b/backends/iommufd.c
@@ -43,6 +43,7 @@
static void iommufd_backend_set_fd(Object *obj, const char *str, Error **errp)
{
+ ERRP_GUARD();
IOMMUFDBackend *be = IOMMUFD_BACKEND(obj);
int fd = -1;
diff --git a/block.c b/block.c
index 1ed9214..468cf5e 100644
--- a/block.c
+++ b/block.c
@@ -534,9 +534,9 @@
int coroutine_fn bdrv_co_create(BlockDriver *drv, const char *filename,
QemuOpts *opts, Error **errp)
{
+ ERRP_GUARD();
int ret;
GLOBAL_STATE_CODE();
- ERRP_GUARD();
if (!drv->bdrv_co_create_opts) {
error_setg(errp, "Driver '%s' does not support image creation",
@@ -633,6 +633,7 @@
QemuOpts *opts,
Error **errp)
{
+ ERRP_GUARD();
BlockBackend *blk;
QDict *options;
int64_t size = 0;
@@ -1998,6 +1999,7 @@
static QDict *parse_json_filename(const char *filename, Error **errp)
{
+ ERRP_GUARD();
QObject *options_obj;
QDict *options;
int ret;
@@ -3585,6 +3587,7 @@
int bdrv_open_backing_file(BlockDriverState *bs, QDict *parent_options,
const char *bdref_key, Error **errp)
{
+ ERRP_GUARD();
char *backing_filename = NULL;
char *bdref_key_dot;
const char *reference = NULL;
@@ -3851,6 +3854,7 @@
QDict *snapshot_options,
Error **errp)
{
+ ERRP_GUARD();
g_autofree char *tmp_filename = NULL;
int64_t total_size;
QemuOpts *opts = NULL;
diff --git a/block/copy-before-write.c b/block/copy-before-write.c
index 0842a1a..8aba27a 100644
--- a/block/copy-before-write.c
+++ b/block/copy-before-write.c
@@ -407,6 +407,7 @@
static int cbw_open(BlockDriverState *bs, QDict *options, int flags,
Error **errp)
{
+ ERRP_GUARD();
BDRVCopyBeforeWriteState *s = bs->opaque;
BdrvDirtyBitmap *bitmap = NULL;
int64_t cluster_size;
diff --git a/block/nbd.c b/block/nbd.c
index b9d4f93..ef05f7c 100644
--- a/block/nbd.c
+++ b/block/nbd.c
@@ -852,6 +852,7 @@
BDRVNBDState *s, uint64_t cookie, bool only_structured,
int *request_ret, QEMUIOVector *qiov, void **payload, Error **errp)
{
+ ERRP_GUARD();
int ret;
int i = COOKIE_TO_INDEX(cookie);
void *local_payload = NULL;
diff --git a/block/nvme.c b/block/nvme.c
index 0a0a0a6..3a3c6da 100644
--- a/block/nvme.c
+++ b/block/nvme.c
@@ -168,6 +168,7 @@
static bool nvme_init_queue(BDRVNVMeState *s, NVMeQueue *q,
unsigned nentries, size_t entry_bytes, Error **errp)
{
+ ERRP_GUARD();
size_t bytes;
int r;
@@ -221,6 +222,7 @@
unsigned idx, size_t size,
Error **errp)
{
+ ERRP_GUARD();
int i, r;
NVMeQueuePair *q;
uint64_t prp_list_iova;
@@ -535,6 +537,7 @@
/* Returns true on success, false on failure. */
static bool nvme_identify(BlockDriverState *bs, int namespace, Error **errp)
{
+ ERRP_GUARD();
BDRVNVMeState *s = bs->opaque;
bool ret = false;
QEMU_AUTO_VFREE union {
diff --git a/block/qapi.c b/block/qapi.c
index 9e806fa..31183d4 100644
--- a/block/qapi.c
+++ b/block/qapi.c
@@ -46,11 +46,11 @@
bool flat,
Error **errp)
{
+ ERRP_GUARD();
ImageInfo **p_image_info;
ImageInfo *backing_info;
BlockDriverState *backing;
BlockDeviceInfo *info;
- ERRP_GUARD();
if (!bs->drv) {
error_setg(errp, "Block device %s is ejected", bs->node_name);
@@ -330,8 +330,8 @@
bool skip_implicit_filters,
Error **errp)
{
- ImageInfo *info;
ERRP_GUARD();
+ ImageInfo *info;
info = g_new0(ImageInfo, 1);
bdrv_do_query_node_info(bs, qapi_ImageInfo_base(info), errp);
@@ -382,10 +382,10 @@
BlockGraphInfo **p_info,
Error **errp)
{
+ ERRP_GUARD();
BlockGraphInfo *info;
BlockChildInfoList **children_list_tail;
BdrvChild *c;
- ERRP_GUARD();
info = g_new0(BlockGraphInfo, 1);
bdrv_do_query_node_info(bs, qapi_BlockGraphInfo_base(info), errp);
diff --git a/block/qcow2-bitmap.c b/block/qcow2-bitmap.c
index 0e567ed..874ea56 100644
--- a/block/qcow2-bitmap.c
+++ b/block/qcow2-bitmap.c
@@ -1710,6 +1710,7 @@
uint32_t granularity,
Error **errp)
{
+ ERRP_GUARD();
BDRVQcow2State *s = bs->opaque;
BdrvDirtyBitmap *bitmap;
uint64_t bitmap_directory_size = 0;
diff --git a/block/qcow2.c b/block/qcow2.c
index 204f585..956128b 100644
--- a/block/qcow2.c
+++ b/block/qcow2.c
@@ -3483,6 +3483,7 @@
static int coroutine_fn GRAPH_UNLOCKED
qcow2_co_create(BlockdevCreateOptions *create_options, Error **errp)
{
+ ERRP_GUARD();
BlockdevCreateOptionsQcow2 *qcow2_opts;
QDict *options;
@@ -4283,6 +4284,7 @@
qcow2_co_truncate(BlockDriverState *bs, int64_t offset, bool exact,
PreallocMode prealloc, BdrvRequestFlags flags, Error **errp)
{
+ ERRP_GUARD();
BDRVQcow2State *s = bs->opaque;
uint64_t old_length;
int64_t new_l1_size;
diff --git a/block/qed.c b/block/qed.c
index bc2f0a6..fa5bc11 100644
--- a/block/qed.c
+++ b/block/qed.c
@@ -1579,6 +1579,7 @@
static void coroutine_fn GRAPH_RDLOCK
bdrv_qed_co_invalidate_cache(BlockDriverState *bs, Error **errp)
{
+ ERRP_GUARD();
BDRVQEDState *s = bs->opaque;
int ret;
diff --git a/block/snapshot.c b/block/snapshot.c
index 8694fc0..8242b4a 100644
--- a/block/snapshot.c
+++ b/block/snapshot.c
@@ -566,6 +566,7 @@
bool has_devices, strList *devices,
Error **errp)
{
+ ERRP_GUARD();
g_autoptr(GList) bdrvs = NULL;
GList *iterbdrvs;
@@ -605,6 +606,7 @@
bool has_devices, strList *devices,
Error **errp)
{
+ ERRP_GUARD();
g_autoptr(GList) bdrvs = NULL;
GList *iterbdrvs;
int ret;
diff --git a/block/vdi.c b/block/vdi.c
index 3b57bec..6363da0 100644
--- a/block/vdi.c
+++ b/block/vdi.c
@@ -738,6 +738,7 @@
vdi_co_do_create(BlockdevCreateOptions *create_options, size_t block_size,
Error **errp)
{
+ ERRP_GUARD();
BlockdevCreateOptionsVdi *vdi_opts;
int ret = 0;
uint64_t bytes = 0;
diff --git a/block/vmdk.c b/block/vmdk.c
index bf78e12..3b82979 100644
--- a/block/vmdk.c
+++ b/block/vmdk.c
@@ -1147,6 +1147,7 @@
vmdk_parse_extents(const char *desc, BlockDriverState *bs, QDict *options,
Error **errp)
{
+ ERRP_GUARD();
int ret;
int matches;
char access[11];
diff --git a/bsd-user/signal.c b/bsd-user/signal.c
index e9f80a0..3ac50c2 100644
--- a/bsd-user/signal.c
+++ b/bsd-user/signal.c
@@ -463,14 +463,13 @@
void force_sig_fault(int sig, int code, abi_ulong addr)
{
CPUState *cpu = thread_cpu;
- CPUArchState *env = cpu_env(cpu);
target_siginfo_t info = {};
info.si_signo = sig;
info.si_errno = 0;
info.si_code = code;
info.si_addr = addr;
- queue_signal(env, sig, QEMU_SI_FAULT, &info);
+ queue_signal(cpu_env(cpu), sig, QEMU_SI_FAULT, &info);
}
static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
diff --git a/contrib/elf2dmp/addrspace.c b/contrib/elf2dmp/addrspace.c
index 6f608a5..81295a1 100644
--- a/contrib/elf2dmp/addrspace.c
+++ b/contrib/elf2dmp/addrspace.c
@@ -22,7 +22,7 @@
return NULL;
}
-static uint8_t *pa_space_resolve(struct pa_space *ps, uint64_t pa)
+static void *pa_space_resolve(struct pa_space *ps, uint64_t pa)
{
struct pa_block *block = pa_space_find_block(ps, pa);
@@ -33,6 +33,19 @@
return block->addr + (pa - block->paddr);
}
+static bool pa_space_read64(struct pa_space *ps, uint64_t pa, uint64_t *value)
+{
+ uint64_t *resolved = pa_space_resolve(ps, pa);
+
+ if (!resolved) {
+ return false;
+ }
+
+ *value = *resolved;
+
+ return true;
+}
+
static void pa_block_align(struct pa_block *b)
{
uint64_t low_align = ((b->paddr - 1) | ELF2DMP_PAGE_MASK) + 1 - b->paddr;
@@ -57,7 +70,7 @@
b->paddr += low_align;
}
-int pa_space_create(struct pa_space *ps, QEMU_Elf *qemu_elf)
+void pa_space_create(struct pa_space *ps, QEMU_Elf *qemu_elf)
{
Elf64_Half phdr_nr = elf_getphdrnum(qemu_elf->map);
Elf64_Phdr *phdr = elf64_getphdr(qemu_elf->map);
@@ -75,11 +88,12 @@
ps->block = g_new(struct pa_block, ps->block_nr);
for (i = 0; i < phdr_nr; i++) {
- if (phdr[i].p_type == PT_LOAD) {
+ if (phdr[i].p_type == PT_LOAD && phdr[i].p_offset < qemu_elf->size) {
ps->block[block_i] = (struct pa_block) {
.addr = (uint8_t *)qemu_elf->map + phdr[i].p_offset,
.paddr = phdr[i].p_paddr,
- .size = phdr[i].p_filesz,
+ .size = MIN(phdr[i].p_filesz,
+ qemu_elf->size - phdr[i].p_offset),
};
pa_block_align(&ps->block[block_i]);
block_i = ps->block[block_i].size ? (block_i + 1) : block_i;
@@ -87,8 +101,6 @@
}
ps->block_nr = block_i;
-
- return 0;
}
void pa_space_destroy(struct pa_space *ps)
@@ -108,19 +120,20 @@
va_space_set_dtb(vs, dtb);
}
-static uint64_t get_pml4e(struct va_space *vs, uint64_t va)
+static bool get_pml4e(struct va_space *vs, uint64_t va, uint64_t *value)
{
uint64_t pa = (vs->dtb & 0xffffffffff000) | ((va & 0xff8000000000) >> 36);
- return *(uint64_t *)pa_space_resolve(vs->ps, pa);
+ return pa_space_read64(vs->ps, pa, value);
}
-static uint64_t get_pdpi(struct va_space *vs, uint64_t va, uint64_t pml4e)
+static bool get_pdpi(struct va_space *vs, uint64_t va, uint64_t pml4e,
+ uint64_t *value)
{
uint64_t pdpte_paddr = (pml4e & 0xffffffffff000) |
((va & 0x7FC0000000) >> 27);
- return *(uint64_t *)pa_space_resolve(vs->ps, pdpte_paddr);
+ return pa_space_read64(vs->ps, pdpte_paddr, value);
}
static uint64_t pde_index(uint64_t va)
@@ -133,11 +146,12 @@
return pdpe & 0xFFFFFFFFFF000;
}
-static uint64_t get_pgd(struct va_space *vs, uint64_t va, uint64_t pdpe)
+static bool get_pgd(struct va_space *vs, uint64_t va, uint64_t pdpe,
+ uint64_t *value)
{
uint64_t pgd_entry = pdba_base(pdpe) + pde_index(va) * 8;
- return *(uint64_t *)pa_space_resolve(vs->ps, pgd_entry);
+ return pa_space_read64(vs->ps, pgd_entry, value);
}
static uint64_t pte_index(uint64_t va)
@@ -150,11 +164,12 @@
return pde & 0xFFFFFFFFFF000;
}
-static uint64_t get_pte(struct va_space *vs, uint64_t va, uint64_t pgd)
+static bool get_pte(struct va_space *vs, uint64_t va, uint64_t pgd,
+ uint64_t *value)
{
uint64_t pgd_val = ptba_base(pgd) + pte_index(va) * 8;
- return *(uint64_t *)pa_space_resolve(vs->ps, pgd_val);
+ return pa_space_read64(vs->ps, pgd_val, value);
}
static uint64_t get_paddr(uint64_t va, uint64_t pte)
@@ -186,13 +201,11 @@
{
uint64_t pml4e, pdpe, pgd, pte;
- pml4e = get_pml4e(vs, va);
- if (!is_present(pml4e)) {
+ if (!get_pml4e(vs, va, &pml4e) || !is_present(pml4e)) {
return INVALID_PA;
}
- pdpe = get_pdpi(vs, va, pml4e);
- if (!is_present(pdpe)) {
+ if (!get_pdpi(vs, va, pml4e, &pdpe) || !is_present(pdpe)) {
return INVALID_PA;
}
@@ -200,8 +213,7 @@
return get_1GB_paddr(va, pdpe);
}
- pgd = get_pgd(vs, va, pdpe);
- if (!is_present(pgd)) {
+ if (!get_pgd(vs, va, pdpe, &pgd) || !is_present(pgd)) {
return INVALID_PA;
}
@@ -209,8 +221,7 @@
return get_2MB_paddr(va, pgd);
}
- pte = get_pte(vs, va, pgd);
- if (!is_present(pte)) {
+ if (!get_pte(vs, va, pgd, &pte) || !is_present(pte)) {
return INVALID_PA;
}
@@ -228,8 +239,8 @@
return pa_space_resolve(vs->ps, pa);
}
-int va_space_rw(struct va_space *vs, uint64_t addr,
- void *buf, size_t size, int is_write)
+bool va_space_rw(struct va_space *vs, uint64_t addr,
+ void *buf, size_t size, int is_write)
{
while (size) {
uint64_t page = addr & ELF2DMP_PFN_MASK;
@@ -240,7 +251,7 @@
ptr = va_space_resolve(vs, addr);
if (!ptr) {
- return 1;
+ return false;
}
if (is_write) {
@@ -254,5 +265,5 @@
addr += s;
}
- return 0;
+ return true;
}
diff --git a/contrib/elf2dmp/addrspace.h b/contrib/elf2dmp/addrspace.h
index 039c70c..2ad30a9 100644
--- a/contrib/elf2dmp/addrspace.h
+++ b/contrib/elf2dmp/addrspace.h
@@ -33,13 +33,13 @@
struct pa_space *ps;
};
-int pa_space_create(struct pa_space *ps, QEMU_Elf *qemu_elf);
+void pa_space_create(struct pa_space *ps, QEMU_Elf *qemu_elf);
void pa_space_destroy(struct pa_space *ps);
void va_space_create(struct va_space *vs, struct pa_space *ps, uint64_t dtb);
void va_space_set_dtb(struct va_space *vs, uint64_t dtb);
void *va_space_resolve(struct va_space *vs, uint64_t va);
-int va_space_rw(struct va_space *vs, uint64_t addr,
- void *buf, size_t size, int is_write);
+bool va_space_rw(struct va_space *vs, uint64_t addr,
+ void *buf, size_t size, int is_write);
#endif /* ADDRSPACE_H */
diff --git a/contrib/elf2dmp/download.c b/contrib/elf2dmp/download.c
index bd7650a..21306b3 100644
--- a/contrib/elf2dmp/download.c
+++ b/contrib/elf2dmp/download.c
@@ -9,19 +9,18 @@
#include <curl/curl.h>
#include "download.h"
-int download_url(const char *name, const char *url)
+bool download_url(const char *name, const char *url)
{
- int err = 0;
+ bool success = false;
FILE *file;
CURL *curl = curl_easy_init();
if (!curl) {
- return 1;
+ return false;
}
file = fopen(name, "wb");
if (!file) {
- err = 1;
goto out_curl;
}
@@ -33,13 +32,12 @@
|| curl_easy_perform(curl) != CURLE_OK) {
unlink(name);
fclose(file);
- err = 1;
} else {
- err = fclose(file);
+ success = !fclose(file);
}
out_curl:
curl_easy_cleanup(curl);
- return err;
+ return success;
}
diff --git a/contrib/elf2dmp/download.h b/contrib/elf2dmp/download.h
index 5c27492..f65adb5 100644
--- a/contrib/elf2dmp/download.h
+++ b/contrib/elf2dmp/download.h
@@ -8,6 +8,6 @@
#ifndef DOWNLOAD_H
#define DOWNLOAD_H
-int download_url(const char *name, const char *url);
+bool download_url(const char *name, const char *url);
#endif /* DOWNLOAD_H */
diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
index cbc38a7..d046a72 100644
--- a/contrib/elf2dmp/main.c
+++ b/contrib/elf2dmp/main.c
@@ -6,6 +6,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/bitops.h"
#include "err.h"
#include "addrspace.h"
@@ -47,11 +48,6 @@
s ? printf(#s" = 0x%016"PRIx64"\n", s) :\
eprintf("Failed to resolve "#s"\n"), s)
-static uint64_t rol(uint64_t x, uint64_t y)
-{
- return (x << y) | (x >> (64 - y));
-}
-
/*
* Decoding algorithm can be found in Volatility project
*/
@@ -64,7 +60,7 @@
uint64_t block;
block = src[i];
- block = rol(block ^ kwn, (uint8_t)kwn);
+ block = rol64(block ^ kwn, kwn);
block = __builtin_bswap64(block ^ kdbe) ^ kwa;
dst[i] = block;
}
@@ -79,9 +75,9 @@
bool decode = false;
uint64_t kwn, kwa, KdpDataBlockEncoded;
- if (va_space_rw(vs,
- KdDebuggerDataBlock + offsetof(KDDEBUGGER_DATA64, Header),
- &kdbg_hdr, sizeof(kdbg_hdr), 0)) {
+ if (!va_space_rw(vs,
+ KdDebuggerDataBlock + offsetof(KDDEBUGGER_DATA64, Header),
+ &kdbg_hdr, sizeof(kdbg_hdr), 0)) {
eprintf("Failed to extract KDBG header\n");
return NULL;
}
@@ -97,8 +93,8 @@
return NULL;
}
- if (va_space_rw(vs, KiWaitNever, &kwn, sizeof(kwn), 0) ||
- va_space_rw(vs, KiWaitAlways, &kwa, sizeof(kwa), 0)) {
+ if (!va_space_rw(vs, KiWaitNever, &kwn, sizeof(kwn), 0) ||
+ !va_space_rw(vs, KiWaitAlways, &kwa, sizeof(kwa), 0)) {
return NULL;
}
@@ -122,7 +118,7 @@
kdbg = g_malloc(kdbg_hdr.Size);
- if (va_space_rw(vs, KdDebuggerDataBlock, kdbg, kdbg_hdr.Size, 0)) {
+ if (!va_space_rw(vs, KdDebuggerDataBlock, kdbg, kdbg_hdr.Size, 0)) {
eprintf("Failed to extract entire KDBG\n");
g_free(kdbg);
return NULL;
@@ -186,13 +182,13 @@
* Finds paging-structure hierarchy base,
* if previously set doesn't give access to kernel structures
*/
-static int fix_dtb(struct va_space *vs, QEMU_Elf *qe)
+static bool fix_dtb(struct va_space *vs, QEMU_Elf *qe)
{
/*
* Firstly, test previously set DTB.
*/
if (va_space_resolve(vs, SharedUserData)) {
- return 0;
+ return true;
}
/*
@@ -206,7 +202,7 @@
va_space_set_dtb(vs, s->cr[3]);
printf("DTB 0x%016"PRIx64" has been found from CPU #%zu"
" as system task CR3\n", vs->dtb, i);
- return !(va_space_resolve(vs, SharedUserData));
+ return va_space_resolve(vs, SharedUserData);
}
}
@@ -220,16 +216,16 @@
uint64_t *cr3 = va_space_resolve(vs, Prcb + 0x7000);
if (!cr3) {
- return 1;
+ return false;
}
va_space_set_dtb(vs, *cr3);
printf("DirectoryTableBase = 0x%016"PRIx64" has been found from CPU #0"
" as interrupt handling CR3\n", vs->dtb);
- return !(va_space_resolve(vs, SharedUserData));
+ return va_space_resolve(vs, SharedUserData);
}
- return 1;
+ return true;
}
static void try_merge_runs(struct pa_space *ps,
@@ -268,9 +264,10 @@
}
}
-static int fill_header(WinDumpHeader64 *hdr, struct pa_space *ps,
- struct va_space *vs, uint64_t KdDebuggerDataBlock,
- KDDEBUGGER_DATA64 *kdbg, uint64_t KdVersionBlock, int nr_cpus)
+static bool fill_header(WinDumpHeader64 *hdr, struct pa_space *ps,
+ struct va_space *vs, uint64_t KdDebuggerDataBlock,
+ KDDEBUGGER_DATA64 *kdbg, uint64_t KdVersionBlock,
+ int nr_cpus)
{
uint32_t *suite_mask = va_space_resolve(vs, SharedUserData +
KUSD_OFFSET_SUITE_MASK);
@@ -283,12 +280,12 @@
QEMU_BUILD_BUG_ON(KUSD_OFFSET_PRODUCT_TYPE >= ELF2DMP_PAGE_SIZE);
if (!suite_mask || !product_type) {
- return 1;
+ return false;
}
- if (va_space_rw(vs, KdVersionBlock, &kvb, sizeof(kvb), 0)) {
+ if (!va_space_rw(vs, KdVersionBlock, &kvb, sizeof(kvb), 0)) {
eprintf("Failed to extract KdVersionBlock\n");
- return 1;
+ return false;
}
h = (WinDumpHeader64) {
@@ -333,11 +330,16 @@
*hdr = h;
- return 0;
+ return true;
}
-static int fill_context(KDDEBUGGER_DATA64 *kdbg,
- struct va_space *vs, QEMU_Elf *qe)
+/*
+ * fill_context() continues even if it fails to fill contexts of some CPUs.
+ * A dump may still contain valuable information even if it lacks contexts of
+ * some CPUs due to dump corruption or a failure before starting CPUs.
+ */
+static void fill_context(KDDEBUGGER_DATA64 *kdbg,
+ struct va_space *vs, QEMU_Elf *qe)
{
int i;
@@ -347,10 +349,10 @@
WinContext64 ctx;
QEMUCPUState *s = qe->state[i];
- if (va_space_rw(vs, kdbg->KiProcessorBlock + sizeof(Prcb) * i,
- &Prcb, sizeof(Prcb), 0)) {
+ if (!va_space_rw(vs, kdbg->KiProcessorBlock + sizeof(Prcb) * i,
+ &Prcb, sizeof(Prcb), 0)) {
eprintf("Failed to read CPU #%d PRCB location\n", i);
- return 1;
+ continue;
}
if (!Prcb) {
@@ -358,26 +360,24 @@
continue;
}
- if (va_space_rw(vs, Prcb + kdbg->OffsetPrcbContext,
- &Context, sizeof(Context), 0)) {
+ if (!va_space_rw(vs, Prcb + kdbg->OffsetPrcbContext,
+ &Context, sizeof(Context), 0)) {
eprintf("Failed to read CPU #%d ContextFrame location\n", i);
- return 1;
+ continue;
}
printf("Filling context for CPU #%d...\n", i);
win_context_init_from_qemu_cpu_state(&ctx, s);
- if (va_space_rw(vs, Context, &ctx, sizeof(ctx), 1)) {
+ if (!va_space_rw(vs, Context, &ctx, sizeof(ctx), 1)) {
eprintf("Failed to fill CPU #%d context\n", i);
- return 1;
+ continue;
}
}
-
- return 0;
}
-static int pe_get_data_dir_entry(uint64_t base, void *start_addr, int idx,
- void *entry, size_t size, struct va_space *vs)
+static bool pe_get_data_dir_entry(uint64_t base, void *start_addr, int idx,
+ void *entry, size_t size, struct va_space *vs)
{
const char e_magic[2] = "MZ";
const char Signature[4] = "PE\0\0";
@@ -390,40 +390,38 @@
QEMU_BUILD_BUG_ON(sizeof(*dos_hdr) >= ELF2DMP_PAGE_SIZE);
if (memcmp(&dos_hdr->e_magic, e_magic, sizeof(e_magic))) {
- return 1;
+ return false;
}
- if (va_space_rw(vs, base + dos_hdr->e_lfanew,
- &nt_hdrs, sizeof(nt_hdrs), 0)) {
- return 1;
+ if (!va_space_rw(vs, base + dos_hdr->e_lfanew,
+ &nt_hdrs, sizeof(nt_hdrs), 0)) {
+ return false;
}
if (memcmp(&nt_hdrs.Signature, Signature, sizeof(Signature)) ||
file_hdr->Machine != 0x8664 || opt_hdr->Magic != 0x020b) {
- return 1;
+ return false;
}
- if (va_space_rw(vs,
- base + data_dir[idx].VirtualAddress,
- entry, size, 0)) {
- return 1;
+ if (!va_space_rw(vs, base + data_dir[idx].VirtualAddress, entry, size, 0)) {
+ return false;
}
printf("Data directory entry #%d: RVA = 0x%08"PRIx32"\n", idx,
(uint32_t)data_dir[idx].VirtualAddress);
- return 0;
+ return true;
}
-static int write_dump(struct pa_space *ps,
- WinDumpHeader64 *hdr, const char *name)
+static bool write_dump(struct pa_space *ps,
+ WinDumpHeader64 *hdr, const char *name)
{
FILE *dmp_file = fopen(name, "wb");
size_t i;
if (!dmp_file) {
eprintf("Failed to open output file \'%s\'\n", name);
- return 1;
+ return false;
}
printf("Writing header to file...\n");
@@ -431,7 +429,7 @@
if (fwrite(hdr, sizeof(*hdr), 1, dmp_file) != 1) {
eprintf("Failed to write dump header\n");
fclose(dmp_file);
- return 1;
+ return false;
}
for (i = 0; i < ps->block_nr; i++) {
@@ -442,11 +440,11 @@
if (fwrite(b->addr, b->size, 1, dmp_file) != 1) {
eprintf("Failed to write block\n");
fclose(dmp_file);
- return 1;
+ return false;
}
}
- return fclose(dmp_file);
+ return !fclose(dmp_file);
}
static bool pe_check_pdb_name(uint64_t base, void *start_addr,
@@ -456,8 +454,8 @@
IMAGE_DEBUG_DIRECTORY debug_dir;
char pdb_name[sizeof(PDB_NAME)];
- if (pe_get_data_dir_entry(base, start_addr, IMAGE_FILE_DEBUG_DIRECTORY,
- &debug_dir, sizeof(debug_dir), vs)) {
+ if (!pe_get_data_dir_entry(base, start_addr, IMAGE_FILE_DEBUG_DIRECTORY,
+ &debug_dir, sizeof(debug_dir), vs)) {
eprintf("Failed to get Debug Directory\n");
return false;
}
@@ -467,9 +465,8 @@
return false;
}
- if (va_space_rw(vs,
- base + debug_dir.AddressOfRawData,
- rsds, sizeof(*rsds), 0)) {
+ if (!va_space_rw(vs, base + debug_dir.AddressOfRawData,
+ rsds, sizeof(*rsds), 0)) {
eprintf("Failed to resolve OMFSignatureRSDS\n");
return false;
}
@@ -485,9 +482,9 @@
return false;
}
- if (va_space_rw(vs, base + debug_dir.AddressOfRawData +
- offsetof(OMFSignatureRSDS, name), pdb_name, sizeof(PDB_NAME),
- 0)) {
+ if (!va_space_rw(vs, base + debug_dir.AddressOfRawData +
+ offsetof(OMFSignatureRSDS, name),
+ pdb_name, sizeof(PDB_NAME), 0)) {
eprintf("Failed to resolve PDB name\n");
return false;
}
@@ -511,7 +508,7 @@
int main(int argc, char *argv[])
{
- int err = 0;
+ int err = 1;
QEMU_Elf qemu_elf;
struct pa_space ps;
struct va_space vs;
@@ -535,33 +532,27 @@
return 1;
}
- if (QEMU_Elf_init(&qemu_elf, argv[1])) {
+ if (!QEMU_Elf_init(&qemu_elf, argv[1])) {
eprintf("Failed to initialize QEMU ELF dump\n");
return 1;
}
- if (pa_space_create(&ps, &qemu_elf)) {
- eprintf("Failed to initialize physical address space\n");
- err = 1;
- goto out_elf;
- }
+ pa_space_create(&ps, &qemu_elf);
state = qemu_elf.state[0];
printf("CPU #0 CR3 is 0x%016"PRIx64"\n", state->cr[3]);
va_space_create(&vs, &ps, state->cr[3]);
- if (fix_dtb(&vs, &qemu_elf)) {
+ if (!fix_dtb(&vs, &qemu_elf)) {
eprintf("Failed to find paging base\n");
- err = 1;
- goto out_elf;
+ goto out_ps;
}
printf("CPU #0 IDT is at 0x%016"PRIx64"\n", state->idt.base);
- if (va_space_rw(&vs, state->idt.base,
- &first_idt_desc, sizeof(first_idt_desc), 0)) {
+ if (!va_space_rw(&vs, state->idt.base,
+ &first_idt_desc, sizeof(first_idt_desc), 0)) {
eprintf("Failed to get CPU #0 IDT[0]\n");
- err = 1;
goto out_ps;
}
printf("CPU #0 IDT[0] -> 0x%016"PRIx64"\n", idt_desc_addr(first_idt_desc));
@@ -586,7 +577,6 @@
if (!kernel_found) {
eprintf("Failed to find NT kernel image\n");
- err = 1;
goto out_ps;
}
@@ -598,47 +588,40 @@
sprintf(pdb_url, "%s%s/%s/%s", SYM_URL_BASE, PDB_NAME, pdb_hash, PDB_NAME);
printf("PDB URL is %s\n", pdb_url);
- if (download_url(PDB_NAME, pdb_url)) {
+ if (!download_url(PDB_NAME, pdb_url)) {
eprintf("Failed to download PDB file\n");
- err = 1;
goto out_ps;
}
- if (pdb_init_from_file(PDB_NAME, &pdb)) {
+ if (!pdb_init_from_file(PDB_NAME, &pdb)) {
eprintf("Failed to initialize PDB reader\n");
- err = 1;
goto out_pdb_file;
}
if (!SYM_RESOLVE(KernBase, &pdb, KdDebuggerDataBlock) ||
!SYM_RESOLVE(KernBase, &pdb, KdVersionBlock)) {
- err = 1;
goto out_pdb;
}
kdbg = get_kdbg(KernBase, &pdb, &vs, KdDebuggerDataBlock);
if (!kdbg) {
- err = 1;
goto out_pdb;
}
- if (fill_header(&header, &ps, &vs, KdDebuggerDataBlock, kdbg,
- KdVersionBlock, qemu_elf.state_nr)) {
- err = 1;
+ if (!fill_header(&header, &ps, &vs, KdDebuggerDataBlock, kdbg,
+ KdVersionBlock, qemu_elf.state_nr)) {
goto out_kdbg;
}
- if (fill_context(kdbg, &vs, &qemu_elf)) {
- err = 1;
- goto out_kdbg;
- }
+ fill_context(kdbg, &vs, &qemu_elf);
- if (write_dump(&ps, &header, argv[2])) {
+ if (!write_dump(&ps, &header, argv[2])) {
eprintf("Failed to save dump\n");
- err = 1;
goto out_kdbg;
}
+ err = 0;
+
out_kdbg:
g_free(kdbg);
out_pdb:
@@ -647,7 +630,6 @@
unlink(PDB_NAME);
out_ps:
pa_space_destroy(&ps);
-out_elf:
QEMU_Elf_exit(&qemu_elf);
return err;
diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c
index 40991f5..492aca4 100644
--- a/contrib/elf2dmp/pdb.c
+++ b/contrib/elf2dmp/pdb.c
@@ -19,6 +19,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/bswap.h"
#include "pdb.h"
#include "err.h"
@@ -158,36 +159,35 @@
return pdb_ds_read(r->ds.header, block_list, file_size[file_number]);
}
-static int pdb_init_segments(struct pdb_reader *r)
+static bool pdb_init_segments(struct pdb_reader *r)
{
unsigned stream_idx = r->segments;
r->segs = pdb_ds_read_file(r, stream_idx);
if (!r->segs) {
- return 1;
+ return false;
}
r->segs_size = pdb_get_file_size(r, stream_idx);
if (!r->segs_size) {
- return 1;
+ return false;
}
- return 0;
+ return true;
}
-static int pdb_init_symbols(struct pdb_reader *r)
+static bool pdb_init_symbols(struct pdb_reader *r)
{
- int err = 0;
PDB_SYMBOLS *symbols;
symbols = pdb_ds_read_file(r, 3);
if (!symbols) {
- return 1;
+ return false;
}
r->symbols = symbols;
- r->segments = *(uint16_t *)((const char *)symbols + sizeof(PDB_SYMBOLS) +
+ r->segments = lduw_le_p((const char *)symbols + sizeof(PDB_SYMBOLS) +
symbols->module_size + symbols->offset_size +
symbols->hash_size + symbols->srcmodule_size +
symbols->pdbimport_size + symbols->unknown2_size +
@@ -196,22 +196,21 @@
/* Read global symbol table */
r->modimage = pdb_ds_read_file(r, symbols->gsym_file);
if (!r->modimage) {
- err = 1;
goto out_symbols;
}
- return 0;
+ return true;
out_symbols:
g_free(symbols);
- return err;
+ return false;
}
-static int pdb_reader_ds_init(struct pdb_reader *r, PDB_DS_HEADER *hdr)
+static bool pdb_reader_ds_init(struct pdb_reader *r, PDB_DS_HEADER *hdr)
{
if (hdr->block_size == 0) {
- return 1;
+ return false;
}
memset(r->file_used, 0, sizeof(r->file_used));
@@ -220,42 +219,38 @@
hdr->toc_page * hdr->block_size), hdr->toc_size);
if (!r->ds.toc) {
- return 1;
+ return false;
}
- return 0;
+ return true;
}
-static int pdb_reader_init(struct pdb_reader *r, void *data)
+static bool pdb_reader_init(struct pdb_reader *r, void *data)
{
- int err = 0;
const char pdb7[] = "Microsoft C/C++ MSF 7.00";
if (memcmp(data, pdb7, sizeof(pdb7) - 1)) {
- return 1;
+ return false;
}
- if (pdb_reader_ds_init(r, data)) {
- return 1;
+ if (!pdb_reader_ds_init(r, data)) {
+ return false;
}
r->ds.root = pdb_ds_read_file(r, 1);
if (!r->ds.root) {
- err = 1;
goto out_ds;
}
- if (pdb_init_symbols(r)) {
- err = 1;
+ if (!pdb_init_symbols(r)) {
goto out_root;
}
- if (pdb_init_segments(r)) {
- err = 1;
+ if (!pdb_init_segments(r)) {
goto out_sym;
}
- return 0;
+ return true;
out_sym:
pdb_exit_symbols(r);
@@ -264,7 +259,7 @@
out_ds:
pdb_reader_ds_exit(r);
- return err;
+ return false;
}
static void pdb_reader_exit(struct pdb_reader *r)
@@ -275,32 +270,30 @@
pdb_reader_ds_exit(r);
}
-int pdb_init_from_file(const char *name, struct pdb_reader *reader)
+bool pdb_init_from_file(const char *name, struct pdb_reader *reader)
{
GError *gerr = NULL;
- int err = 0;
void *map;
reader->gmf = g_mapped_file_new(name, TRUE, &gerr);
if (gerr) {
eprintf("Failed to map PDB file \'%s\'\n", name);
g_error_free(gerr);
- return 1;
+ return false;
}
reader->file_size = g_mapped_file_get_length(reader->gmf);
map = g_mapped_file_get_contents(reader->gmf);
- if (pdb_reader_init(reader, map)) {
- err = 1;
+ if (!pdb_reader_init(reader, map)) {
goto out_unmap;
}
- return 0;
+ return true;
out_unmap:
g_mapped_file_unref(reader->gmf);
- return err;
+ return false;
}
void pdb_exit(struct pdb_reader *reader)
diff --git a/contrib/elf2dmp/pdb.h b/contrib/elf2dmp/pdb.h
index 2a50da5..feddf18 100644
--- a/contrib/elf2dmp/pdb.h
+++ b/contrib/elf2dmp/pdb.h
@@ -233,7 +233,7 @@
size_t segs_size;
};
-int pdb_init_from_file(const char *name, struct pdb_reader *reader);
+bool pdb_init_from_file(const char *name, struct pdb_reader *reader);
void pdb_exit(struct pdb_reader *reader);
uint64_t pdb_resolve(uint64_t img_base, struct pdb_reader *r, const char *name);
uint64_t pdb_find_public_v3_symbol(struct pdb_reader *reader, const char *name);
diff --git a/contrib/elf2dmp/qemu_elf.c b/contrib/elf2dmp/qemu_elf.c
index 055e6f8..c9bad6e 100644
--- a/contrib/elf2dmp/qemu_elf.c
+++ b/contrib/elf2dmp/qemu_elf.c
@@ -6,6 +6,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
#include "err.h"
#include "qemu_elf.h"
@@ -15,36 +16,11 @@
#define ROUND_UP(n, d) (((n) + (d) - 1) & -(0 ? (n) : (d)))
#endif
-#ifndef DIV_ROUND_UP
-#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
-#endif
-
-#define ELF_NOTE_SIZE(hdr_size, name_size, desc_size) \
- ((DIV_ROUND_UP((hdr_size), 4) + \
- DIV_ROUND_UP((name_size), 4) + \
- DIV_ROUND_UP((desc_size), 4)) * 4)
-
int is_system(QEMUCPUState *s)
{
return s->gs.base >> 63;
}
-static char *nhdr_get_name(Elf64_Nhdr *nhdr)
-{
- return (char *)nhdr + ROUND_UP(sizeof(*nhdr), 4);
-}
-
-static void *nhdr_get_desc(Elf64_Nhdr *nhdr)
-{
- return nhdr_get_name(nhdr) + ROUND_UP(nhdr->n_namesz, 4);
-}
-
-static Elf64_Nhdr *nhdr_get_next(Elf64_Nhdr *nhdr)
-{
- return (void *)((uint8_t *)nhdr + ELF_NOTE_SIZE(sizeof(*nhdr),
- nhdr->n_namesz, nhdr->n_descsz));
-}
-
Elf64_Phdr *elf64_getphdr(void *map)
{
Elf64_Ehdr *ehdr = map;
@@ -60,54 +36,92 @@
return ehdr->e_phnum;
}
-static int init_states(QEMU_Elf *qe)
+static bool advance_note_offset(uint64_t *offsetp, uint64_t size, uint64_t end)
+{
+ uint64_t offset = *offsetp;
+
+ if (uadd64_overflow(offset, size, &offset) || offset > UINT64_MAX - 3) {
+ return false;
+ }
+
+ offset = ROUND_UP(offset, 4);
+
+ if (offset > end) {
+ return false;
+ }
+
+ *offsetp = offset;
+
+ return true;
+}
+
+static bool init_states(QEMU_Elf *qe)
{
Elf64_Phdr *phdr = elf64_getphdr(qe->map);
- Elf64_Nhdr *start = (void *)((uint8_t *)qe->map + phdr[0].p_offset);
- Elf64_Nhdr *end = (void *)((uint8_t *)start + phdr[0].p_memsz);
Elf64_Nhdr *nhdr;
- size_t cpu_nr = 0;
+ GPtrArray *states;
+ QEMUCPUState *state;
+ uint32_t state_size;
+ uint64_t offset;
+ uint64_t end_offset;
+ char *name;
if (phdr[0].p_type != PT_NOTE) {
eprintf("Failed to find PT_NOTE\n");
- return 1;
+ return false;
}
qe->has_kernel_gs_base = 1;
+ offset = phdr[0].p_offset;
+ states = g_ptr_array_new();
- for (nhdr = start; nhdr < end; nhdr = nhdr_get_next(nhdr)) {
- if (!strcmp(nhdr_get_name(nhdr), QEMU_NOTE_NAME)) {
- QEMUCPUState *state = nhdr_get_desc(nhdr);
+ if (uadd64_overflow(offset, phdr[0].p_memsz, &end_offset) ||
+ end_offset > qe->size) {
+ end_offset = qe->size;
+ }
- if (state->size < sizeof(*state)) {
- eprintf("CPU #%zu: QEMU CPU state size %u doesn't match\n",
- cpu_nr, state->size);
+ while (offset < end_offset) {
+ nhdr = (void *)((uint8_t *)qe->map + offset);
+
+ if (!advance_note_offset(&offset, sizeof(*nhdr), end_offset)) {
+ break;
+ }
+
+ name = (char *)qe->map + offset;
+
+ if (!advance_note_offset(&offset, nhdr->n_namesz, end_offset)) {
+ break;
+ }
+
+ state = (void *)((uint8_t *)qe->map + offset);
+
+ if (!advance_note_offset(&offset, nhdr->n_descsz, end_offset)) {
+ break;
+ }
+
+ if (!strcmp(name, QEMU_NOTE_NAME) &&
+ nhdr->n_descsz >= offsetof(QEMUCPUState, kernel_gs_base)) {
+ state_size = MIN(state->size, nhdr->n_descsz);
+
+ if (state_size < sizeof(*state)) {
+ eprintf("CPU #%u: QEMU CPU state size %u doesn't match\n",
+ states->len, state_size);
/*
* We assume either every QEMU CPU state has KERNEL_GS_BASE or
* no one has.
*/
qe->has_kernel_gs_base = 0;
}
- cpu_nr++;
+ g_ptr_array_add(states, state);
}
}
- printf("%zu CPU states has been found\n", cpu_nr);
+ printf("%u CPU states has been found\n", states->len);
- qe->state = g_new(QEMUCPUState*, cpu_nr);
+ qe->state_nr = states->len;
+ qe->state = (void *)g_ptr_array_free(states, FALSE);
- cpu_nr = 0;
-
- for (nhdr = start; nhdr < end; nhdr = nhdr_get_next(nhdr)) {
- if (!strcmp(nhdr_get_name(nhdr), QEMU_NOTE_NAME)) {
- qe->state[cpu_nr] = nhdr_get_desc(nhdr);
- cpu_nr++;
- }
- }
-
- qe->state_nr = cpu_nr;
-
- return 0;
+ return true;
}
static void exit_states(QEMU_Elf *qe)
@@ -118,6 +132,7 @@
static bool check_ehdr(QEMU_Elf *qe)
{
Elf64_Ehdr *ehdr = qe->map;
+ uint64_t phendoff;
if (sizeof(Elf64_Ehdr) > qe->size) {
eprintf("Invalid input dump file size\n");
@@ -159,10 +174,17 @@
return false;
}
+ if (umul64_overflow(ehdr->e_phnum, sizeof(Elf64_Phdr), &phendoff) ||
+ uadd64_overflow(phendoff, ehdr->e_phoff, &phendoff) ||
+ phendoff > qe->size) {
+ eprintf("phdrs do not fit in file\n");
+ return false;
+ }
+
return true;
}
-static int QEMU_Elf_map(QEMU_Elf *qe, const char *filename)
+static bool QEMU_Elf_map(QEMU_Elf *qe, const char *filename)
{
#ifdef CONFIG_LINUX
struct stat st;
@@ -173,13 +195,13 @@
fd = open(filename, O_RDONLY, 0);
if (fd == -1) {
eprintf("Failed to open ELF dump file \'%s\'\n", filename);
- return 1;
+ return false;
}
if (fstat(fd, &st)) {
eprintf("Failed to get size of ELF dump file\n");
close(fd);
- return 1;
+ return false;
}
qe->size = st.st_size;
@@ -188,7 +210,7 @@
if (qe->map == MAP_FAILED) {
eprintf("Failed to map ELF file\n");
close(fd);
- return 1;
+ return false;
}
close(fd);
@@ -201,14 +223,14 @@
if (gerr) {
eprintf("Failed to map ELF dump file \'%s\'\n", filename);
g_error_free(gerr);
- return 1;
+ return false;
}
qe->map = g_mapped_file_get_contents(qe->gmf);
qe->size = g_mapped_file_get_length(qe->gmf);
#endif
- return 0;
+ return true;
}
static void QEMU_Elf_unmap(QEMU_Elf *qe)
@@ -220,25 +242,25 @@
#endif
}
-int QEMU_Elf_init(QEMU_Elf *qe, const char *filename)
+bool QEMU_Elf_init(QEMU_Elf *qe, const char *filename)
{
- if (QEMU_Elf_map(qe, filename)) {
- return 1;
+ if (!QEMU_Elf_map(qe, filename)) {
+ return false;
}
if (!check_ehdr(qe)) {
eprintf("Input file has the wrong format\n");
QEMU_Elf_unmap(qe);
- return 1;
+ return false;
}
- if (init_states(qe)) {
+ if (!init_states(qe)) {
eprintf("Failed to extract QEMU CPU states\n");
QEMU_Elf_unmap(qe);
- return 1;
+ return false;
}
- return 0;
+ return true;
}
void QEMU_Elf_exit(QEMU_Elf *qe)
diff --git a/contrib/elf2dmp/qemu_elf.h b/contrib/elf2dmp/qemu_elf.h
index afa75f1..adc5023 100644
--- a/contrib/elf2dmp/qemu_elf.h
+++ b/contrib/elf2dmp/qemu_elf.h
@@ -42,7 +42,7 @@
int has_kernel_gs_base;
} QEMU_Elf;
-int QEMU_Elf_init(QEMU_Elf *qe, const char *filename);
+bool QEMU_Elf_init(QEMU_Elf *qe, const char *filename);
void QEMU_Elf_exit(QEMU_Elf *qe);
Elf64_Phdr *elf64_getphdr(void *map);
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index dfd681c..7b54851 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -47,16 +47,6 @@
However, short-form booleans are deprecated and full explicit ``arg_name=on``
form is preferred.
-User-mode emulator command line arguments
------------------------------------------
-
-``-p`` (since 9.0)
-''''''''''''''''''
-
-The ``-p`` option pretends to control the host page size. However,
-it is not possible to change the host page size, and using the
-option only causes failures.
-
``-smp`` (Unsupported "parameter=1" SMP configurations) (since 9.0)
'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
@@ -71,6 +61,16 @@
marked deprecated since 9.0, users have to ensure that all the topology members
described with -smp are supported by the target machine.
+User-mode emulator command line arguments
+-----------------------------------------
+
+``-p`` (since 9.0)
+''''''''''''''''''
+
+The ``-p`` option pretends to control the host page size. However,
+it is not possible to change the host page size, and using the
+option only causes failures.
+
QEMU Machine Protocol (QMP) commands
------------------------------------
@@ -237,13 +237,28 @@
The machine is no longer in existence and has been long unmaintained
in QEMU. This also holds for the TC51828 16MiB flash that it uses.
-``pseries-2.1`` up to ``pseries-2.11`` (since 9.0)
+``pseries-2.1`` up to ``pseries-2.12`` (since 9.0)
''''''''''''''''''''''''''''''''''''''''''''''''''
-Older pseries machines before version 2.12 have undergone many changes
+Older pseries machines before version 3.0 have undergone many changes
to correct issues, mostly regarding migration compatibility. These are
no longer maintained and removing them will make the code easier to
-read and maintain. Use versions 2.12 and above as a replacement.
+read and maintain. Use versions 3.0 and above as a replacement.
+
+Arm machines ``akita``, ``borzoi``, ``cheetah``, ``connex``, ``mainstone``, ``n800``, ``n810``, ``spitz``, ``terrier``, ``tosa``, ``verdex``, ``z2`` (since 9.0)
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+QEMU includes models of some machine types where the QEMU code that
+emulates their SoCs is very old and unmaintained. This code is now
+blocking our ability to move forward with various changes across
+the codebase, and over many years nobody has been interested in
+trying to modernise it. We don't expect any of these machines to have
+a large number of users, because they're all modelling hardware that
+has now passed away into history. We are therefore dropping support
+for all machine types using the PXA2xx and OMAP2 SoCs. We are also
+dropping the ``cheetah`` OMAP1 board, because we don't have any
+test images for it and don't know of anybody who does; the ``sx1``
+and ``sx1-v1`` OMAP1 machines remain supported for now.
Backend options
---------------
diff --git a/docs/conf.py b/docs/conf.py
index 1b2afa2..aae0304 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -88,7 +88,7 @@
# General information about the project.
project = u'QEMU'
-copyright = u'2023, The QEMU Project Developers'
+copyright = u'2024, The QEMU Project Developers'
author = u'The QEMU Project Developers'
# The version info for the project you're documenting, acts as replacement for
diff --git a/docs/devel/migration/main.rst b/docs/devel/migration/main.rst
index 8024275..54385a2 100644
--- a/docs/devel/migration/main.rst
+++ b/docs/devel/migration/main.rst
@@ -44,7 +44,8 @@
- file migration: do the migration using a file that is passed to QEMU
by path. A file offset option is supported to allow a management
application to add its own metadata to the start of the file without
- QEMU interference.
+ QEMU interference. Note that QEMU does not flush cached file
+ data/metadata at the end of migration.
In addition, support is included for migration using RDMA, which
transports the page data using ``RDMA``, where the hardware takes care of
diff --git a/docs/devel/nested-papr.txt b/docs/devel/nested-papr.txt
new file mode 100644
index 0000000..9094365
--- /dev/null
+++ b/docs/devel/nested-papr.txt
@@ -0,0 +1,119 @@
+Nested PAPR API (aka KVM on PowerVM)
+====================================
+
+This API aims at providing support to enable nested virtualization with
+KVM on PowerVM. While the existing support for nested KVM on PowerNV was
+introduced with cap-nested-hv option, however, with a slight design change,
+to enable this on papr/pseries, a new cap-nested-papr option is added. eg:
+
+ qemu-system-ppc64 -cpu POWER10 -machine pseries,cap-nested-papr=true ...
+
+Work by:
+ Michael Neuling <mikey@neuling.org>
+ Vaibhav Jain <vaibhav@linux.ibm.com>
+ Jordan Niethe <jniethe5@gmail.com>
+ Harsh Prateek Bora <harshpb@linux.ibm.com>
+ Shivaprasad G Bhat <sbhat@linux.ibm.com>
+ Kautuk Consul <kconsul@linux.vnet.ibm.com>
+
+Below taken from the kernel documentation:
+
+Introduction
+============
+
+This document explains how a guest operating system can act as a
+hypervisor and run nested guests through the use of hypercalls, if the
+hypervisor has implemented them. The terms L0, L1, and L2 are used to
+refer to different software entities. L0 is the hypervisor mode entity
+that would normally be called the "host" or "hypervisor". L1 is a
+guest virtual machine that is directly run under L0 and is initiated
+and controlled by L0. L2 is a guest virtual machine that is initiated
+and controlled by L1 acting as a hypervisor. A significant design change
+wrt existing API is that now the entire L2 state is maintained within L0.
+
+Existing Nested-HV API
+======================
+
+Linux/KVM has had support for Nesting as an L0 or L1 since 2018
+
+The L0 code was added::
+
+ commit 8e3f5fc1045dc49fd175b978c5457f5f51e7a2ce
+ Author: Paul Mackerras <paulus@ozlabs.org>
+ Date: Mon Oct 8 16:31:03 2018 +1100
+ KVM: PPC: Book3S HV: Framework and hcall stubs for nested virtualization
+
+The L1 code was added::
+
+ commit 360cae313702cdd0b90f82c261a8302fecef030a
+ Author: Paul Mackerras <paulus@ozlabs.org>
+ Date: Mon Oct 8 16:31:04 2018 +1100
+ KVM: PPC: Book3S HV: Nested guest entry via hypercall
+
+This API works primarily using a signal hcall h_enter_nested(). This
+call made by the L1 to tell the L0 to start an L2 vCPU with the given
+state. The L0 then starts this L2 and runs until an L2 exit condition
+is reached. Once the L2 exits, the state of the L2 is given back to
+the L1 by the L0. The full L2 vCPU state is always transferred from
+and to L1 when the L2 is run. The L0 doesn't keep any state on the L2
+vCPU (except in the short sequence in the L0 on L1 -> L2 entry and L2
+-> L1 exit).
+
+The only state kept by the L0 is the partition table. The L1 registers
+it's partition table using the h_set_partition_table() hcall. All
+other state held by the L0 about the L2s is cached state (such as
+shadow page tables).
+
+The L1 may run any L2 or vCPU without first informing the L0. It
+simply starts the vCPU using h_enter_nested(). The creation of L2s and
+vCPUs is done implicitly whenever h_enter_nested() is called.
+
+In this document, we call this existing API the v1 API.
+
+New PAPR API
+===============
+
+The new PAPR API changes from the v1 API such that the creating L2 and
+associated vCPUs is explicit. In this document, we call this the v2
+API.
+
+h_enter_nested() is replaced with H_GUEST_VCPU_RUN(). Before this can
+be called the L1 must explicitly create the L2 using h_guest_create()
+and any associated vCPUs() created with h_guest_create_vCPU(). Getting
+and setting vCPU state can also be performed using h_guest_{g|s}et
+hcall.
+
+The basic execution flow is for an L1 to create an L2, run it, and
+delete it is:
+
+- L1 and L0 negotiate capabilities with H_GUEST_{G,S}ET_CAPABILITIES()
+ (normally at L1 boot time).
+
+- L1 requests the L0 to create an L2 with H_GUEST_CREATE() and receives a token
+
+- L1 requests the L0 to create an L2 vCPU with H_GUEST_CREATE_VCPU()
+
+- L1 and L0 communicate the vCPU state using the H_GUEST_{G,S}ET() hcall
+
+- L1 requests the L0 to run the vCPU using H_GUEST_RUN_VCPU() hcall
+
+- L1 deletes L2 with H_GUEST_DELETE()
+
+For more details, please refer:
+
+[1] Linux Kernel documentation (upstream documentation commit):
+
+commit 476652297f94a2e5e5ef29e734b0da37ade94110
+Author: Michael Neuling <mikey@neuling.org>
+Date: Thu Sep 14 13:06:00 2023 +1000
+
+ docs: powerpc: Document nested KVM on POWER
+
+ Document support for nested KVM on POWER using the existing API as well
+ as the new PAPR API. This includes the new HCALL interface and how it
+ used by KVM.
+
+ Signed-off-by: Michael Neuling <mikey@neuling.org>
+ Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
+ Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+ Link: https://msgid.link/20230914030600.16993-12-jniethe5@gmail.com
diff --git a/docs/devel/tracing.rst b/docs/devel/tracing.rst
index d288480..043bed7 100644
--- a/docs/devel/tracing.rst
+++ b/docs/devel/tracing.rst
@@ -357,8 +357,7 @@
scripts/tracetool.py --backends=dtrace --format=stap \
--binary path/to/qemu-binary \
- --target-type system \
- --target-name x86_64 \
+ --probe-prefix qemu.system.x86_64 \
--group=all \
trace-events-all \
qemu.stp
diff --git a/docs/system/devices/nvme.rst b/docs/system/devices/nvme.rst
index 4ea957b..d2b1ca9 100644
--- a/docs/system/devices/nvme.rst
+++ b/docs/system/devices/nvme.rst
@@ -81,6 +81,13 @@
Set the UUID of the namespace. This will be reported as a "Namespace UUID"
descriptor in the Namespace Identification Descriptor List.
+``nguid``
+ Set the NGUID of the namespace. This will be reported as a "Namespace Globally
+ Unique Identifier" descriptor in the Namespace Identification Descriptor List.
+ It is specified as a string of hexadecimal digits containing exactly 16 bytes
+ or "auto" for a random value. An optional '-' separator could be used to group
+ bytes. If not specified the NGUID will remain all zeros.
+
``eui64``
Set the EUI-64 of the namespace. This will be reported as a "IEEE Extended
Unique Identifier" descriptor in the Namespace Identification Descriptor List.
diff --git a/docs/system/ppc/amigang.rst b/docs/system/ppc/amigang.rst
new file mode 100644
index 0000000..ba1a3d8
--- /dev/null
+++ b/docs/system/ppc/amigang.rst
@@ -0,0 +1,161 @@
+=========================================================
+AmigaNG boards (``amigaone``, ``pegasos2``, ``sam460ex``)
+=========================================================
+
+These PowerPC machines emulate boards that are primarily used for
+running Amiga like OSes (AmigaOS 4, MorphOS and AROS) but these can
+also run Linux which is what this section documents.
+
+Eyetech AmigaOne/Mai Logic Teron (``amigaone``)
+===============================================
+
+The ``amigaone`` machine emulates an AmigaOne XE mainboard by Eyetech
+which is a rebranded Mai Logic Teron board with modified U-Boot
+firmware to support AmigaOS 4.
+
+Emulated devices
+----------------
+
+ * PowerPC 7457 CPU (can also use``-cpu g3, 750cxe, 750fx`` or ``750gx``)
+ * Articia S north bridge
+ * VIA VT82C686B south bridge
+ * PCI VGA compatible card (guests may need other card instead)
+ * PS/2 keyboard and mouse
+
+Firmware
+--------
+
+A firmware binary is necessary for the boot process. It is a modified
+U-Boot under GPL but its source is lost so it cannot be included in
+QEMU. A binary is available at
+https://www.hyperion-entertainment.com/index.php/downloads?view=files&parent=28.
+The ROM image is in the last 512kB which can be extracted with the
+following command:
+
+.. code-block:: bash
+
+ $ tail -c 524288 updater.image > u-boot-amigaone.bin
+
+The BIOS emulator in the firmware is unable to run QEMU‘s standard
+vgabios so ``VGABIOS-lgpl-latest.bin`` is needed instead which can be
+downloaded from http://www.nongnu.org/vgabios.
+
+Running Linux
+-------------
+
+There are some Linux images under the following link that work on the
+``amigaone`` machine:
+https://sourceforge.net/projects/amigaone-linux/files/debian-installer/.
+To boot the system run:
+
+.. code-block:: bash
+
+ $ qemu-system-ppc -machine amigaone -bios u-boot-amigaone.bin \
+ -cdrom "A1 Linux Net Installer.iso" \
+ -device ati-vga,model=rv100,romfile=VGABIOS-lgpl-latest.bin
+
+From the firmware menu that appears select ``Boot sequence`` →
+``Amiga Multiboot Options`` and set ``Boot device 1`` to
+``Onboard VIA IDE CDROM``. Then hit escape until the main screen appears again,
+hit escape once more and from the exit menu that appears select either
+``Save settings and exit`` or ``Use settings for this session only``. It may
+take a long time loading the kernel into memory but eventually it boots and the
+installer becomes visible. The ``ati-vga`` RV100 emulation is not
+complete yet so only frame buffer works, DRM and 3D is not available.
+
+Genesi/bPlan Pegasos II (``pegasos2``)
+======================================
+
+The ``pegasos2`` machine emulates the Pegasos II sold by Genesi and
+designed by bPlan. Its schematics are available at
+https://www.powerdeveloper.org/platforms/pegasos/schematics.
+
+Emulated devices
+----------------
+
+ * PowerPC 7457 CPU (can also use``-cpu g3`` or ``750cxe``)
+ * Marvell MV64361 Discovery II north bridge
+ * VIA VT8231 south bridge
+ * PCI VGA compatible card (guests may need other card instead)
+ * PS/2 keyboard and mouse
+
+Firmware
+--------
+
+The Pegasos II board has an Open Firmware compliant ROM based on
+SmartFirmware with some changes that are not open-sourced therefore
+the ROM binary cannot be included in QEMU. An updater was available
+from bPlan, it can be found in the `Internet Archive
+<http://web.archive.org/web/20071021223056/http://www.bplan-gmbh.de/up050404/up050404>`_.
+The ROM image can be extracted from it with the following command:
+
+.. code-block:: bash
+
+ $ tail -c +85581 up050404 | head -c 524288 > pegasos2.rom
+
+Running Linux
+-------------
+
+The PowerPC version of Debian 8.11 supported Pegasos II. The BIOS
+emulator in the firmware binary is unable to run QEMU‘s standard
+vgabios so it needs to be disabled. To boot the system run:
+
+.. code-block:: bash
+
+ $ qemu-system-ppc -machine pegasos2 -bios pegasos2.rom \
+ -cdrom debian-8.11.0-powerpc-netinst.iso \
+ -device VGA,romfile="" -serial stdio
+
+At the firmware ``ok`` prompt enter ``boot cd install/pegasos``.
+
+Alternatively, it is possible to boot the kernel directly without
+firmware ROM using the QEMU built-in minimal Virtual Open Firmware
+(VOF) emulation which is also supported on ``pegasos2``. For this,
+extract the kernel ``install/powerpc/vmlinuz-chrp.initrd`` from the CD
+image, then run:
+
+.. code-block:: bash
+
+ $ qemu-system-ppc -machine pegasos2 -serial stdio \
+ -kernel vmlinuz-chrp.initrd -append "---" \
+ -cdrom debian-8.11.0-powerpc-netinst.iso
+
+aCube Sam460ex (``sam460ex``)
+=============================
+
+The ``sam460ex`` machine emulates the Sam460ex board by aCube which is
+based on the AMCC PowerPC 460EX SoC (that despite its name has a
+PPC440 CPU core).
+
+Firmware
+--------
+
+The board has a firmware based on an older U-Boot version with
+modifications to support booting AmigaOS 4. The firmware ROM is
+included with QEMU.
+
+Emulated devices
+----------------
+
+ * PowerPC 460EX SoC
+ * M41T80 serial RTC chip
+ * Silicon Motion SM501 display parts (identical to SM502 on real board)
+ * Silicon Image SiI3112 2 port SATA controller
+ * USB keyboard and mouse
+
+Running Linux
+-------------
+
+The only Linux distro that supported Sam460ex out of box was CruxPPC
+2.x. It can be booted by running:
+
+.. code-block:: bash
+
+ $ qemu-system-ppc -machine sam460ex -serial stdio \
+ -drive if=none,id=cd,format=raw,file=crux-ppc-2.7a.iso \
+ -device ide-cd,drive=cd,bus=ide.1
+
+There are some other kernels and instructions for booting other
+distros on aCube's product page at
+https://www.acube-systems.biz/index.php?page=hardware&pid=5
+but those are untested.
diff --git a/docs/system/target-ppc.rst b/docs/system/target-ppc.rst
index 4f6eb93..87bf412 100644
--- a/docs/system/target-ppc.rst
+++ b/docs/system/target-ppc.rst
@@ -17,6 +17,7 @@
.. toctree::
:maxdepth: 1
+ ppc/amigang
ppc/embedded
ppc/powermac
ppc/powernv
diff --git a/ebpf/ebpf.c b/ebpf/ebpf.c
new file mode 100644
index 0000000..2d73beb
--- /dev/null
+++ b/ebpf/ebpf.c
@@ -0,0 +1,69 @@
+/*
+ * QEMU eBPF binary declaration routine.
+ *
+ * Developed by Daynix Computing LTD (http://www.daynix.com)
+ *
+ * Authors:
+ * Andrew Melnychenko <andrew@daynix.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/queue.h"
+#include "qapi/error.h"
+#include "qapi/qapi-commands-ebpf.h"
+#include "ebpf/ebpf.h"
+
+typedef struct ElfBinaryDataEntry {
+ int id;
+ const void *data;
+ size_t datalen;
+
+ QSLIST_ENTRY(ElfBinaryDataEntry) node;
+} ElfBinaryDataEntry;
+
+static QSLIST_HEAD(, ElfBinaryDataEntry) ebpf_elf_obj_list =
+ QSLIST_HEAD_INITIALIZER();
+
+void ebpf_register_binary_data(int id, const void *data, size_t datalen)
+{
+ struct ElfBinaryDataEntry *dataentry = NULL;
+
+ dataentry = g_new0(struct ElfBinaryDataEntry, 1);
+ dataentry->data = data;
+ dataentry->datalen = datalen;
+ dataentry->id = id;
+
+ QSLIST_INSERT_HEAD(&ebpf_elf_obj_list, dataentry, node);
+}
+
+const void *ebpf_find_binary_by_id(int id, size_t *sz, Error **errp)
+{
+ struct ElfBinaryDataEntry *it = NULL;
+ QSLIST_FOREACH(it, &ebpf_elf_obj_list, node) {
+ if (id == it->id) {
+ *sz = it->datalen;
+ return it->data;
+ }
+ }
+
+ error_setg(errp, "can't find eBPF object with id: %d", id);
+
+ return NULL;
+}
+
+EbpfObject *qmp_request_ebpf(EbpfProgramID id, Error **errp)
+{
+ EbpfObject *ret = NULL;
+ size_t size = 0;
+ const void *data = ebpf_find_binary_by_id(id, &size, errp);
+ if (!data) {
+ return NULL;
+ }
+
+ ret = g_new0(EbpfObject, 1);
+ ret->object = g_base64_encode(data, size);
+
+ return ret;
+}
diff --git a/ebpf/ebpf.h b/ebpf/ebpf.h
new file mode 100644
index 0000000..378d4e9
--- /dev/null
+++ b/ebpf/ebpf.h
@@ -0,0 +1,29 @@
+/*
+ * QEMU eBPF binary declaration routine.
+ *
+ * Developed by Daynix Computing LTD (http://www.daynix.com)
+ *
+ * Authors:
+ * Andrew Melnychenko <andrew@daynix.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef EBPF_H
+#define EBPF_H
+
+
+void ebpf_register_binary_data(int id, const void *data,
+ size_t datalen);
+const void *ebpf_find_binary_by_id(int id, size_t *sz,
+ struct Error **errp);
+
+#define ebpf_binary_init(id, fn) \
+static void __attribute__((constructor)) ebpf_binary_init_ ## fn(void) \
+{ \
+ size_t datalen = 0; \
+ const void *data = fn(&datalen); \
+ ebpf_register_binary_data(id, data, datalen); \
+}
+
+#endif /* EBPF_H */
diff --git a/ebpf/ebpf_rss-stub.c b/ebpf/ebpf_rss-stub.c
index e71e2291..8d7fae2 100644
--- a/ebpf/ebpf_rss-stub.c
+++ b/ebpf/ebpf_rss-stub.c
@@ -28,6 +28,12 @@
return false;
}
+bool ebpf_rss_load_fds(struct EBPFRSSContext *ctx, int program_fd,
+ int config_fd, int toeplitz_fd, int table_fd)
+{
+ return false;
+}
+
bool ebpf_rss_set_all(struct EBPFRSSContext *ctx, struct EBPFRSSConfig *config,
uint16_t *indirections_table, uint8_t *toeplitz_key)
{
diff --git a/ebpf/ebpf_rss.c b/ebpf/ebpf_rss.c
index cee658c..2e506f9 100644
--- a/ebpf/ebpf_rss.c
+++ b/ebpf/ebpf_rss.c
@@ -13,6 +13,8 @@
#include "qemu/osdep.h"
#include "qemu/error-report.h"
+#include "qapi/qapi-types-misc.h"
+#include "qapi/qapi-commands-ebpf.h"
#include <bpf/libbpf.h>
#include <bpf/bpf.h>
@@ -21,38 +23,97 @@
#include "ebpf/ebpf_rss.h"
#include "ebpf/rss.bpf.skeleton.h"
-#include "trace.h"
+#include "ebpf/ebpf.h"
void ebpf_rss_init(struct EBPFRSSContext *ctx)
{
if (ctx != NULL) {
ctx->obj = NULL;
+ ctx->program_fd = -1;
+ ctx->map_configuration = -1;
+ ctx->map_toeplitz_key = -1;
+ ctx->map_indirections_table = -1;
+
+ ctx->mmap_configuration = NULL;
+ ctx->mmap_toeplitz_key = NULL;
+ ctx->mmap_indirections_table = NULL;
}
}
bool ebpf_rss_is_loaded(struct EBPFRSSContext *ctx)
{
- return ctx != NULL && ctx->obj != NULL;
+ return ctx != NULL && (ctx->obj != NULL || ctx->program_fd != -1);
+}
+
+static bool ebpf_rss_mmap(struct EBPFRSSContext *ctx)
+{
+ if (!ebpf_rss_is_loaded(ctx)) {
+ return false;
+ }
+
+ ctx->mmap_configuration = mmap(NULL, qemu_real_host_page_size(),
+ PROT_READ | PROT_WRITE, MAP_SHARED,
+ ctx->map_configuration, 0);
+ if (ctx->mmap_configuration == MAP_FAILED) {
+ return false;
+ }
+ ctx->mmap_toeplitz_key = mmap(NULL, qemu_real_host_page_size(),
+ PROT_READ | PROT_WRITE, MAP_SHARED,
+ ctx->map_toeplitz_key, 0);
+ if (ctx->mmap_toeplitz_key == MAP_FAILED) {
+ goto toeplitz_fail;
+ }
+ ctx->mmap_indirections_table = mmap(NULL, qemu_real_host_page_size(),
+ PROT_READ | PROT_WRITE, MAP_SHARED,
+ ctx->map_indirections_table, 0);
+ if (ctx->mmap_indirections_table == MAP_FAILED) {
+ goto indirection_fail;
+ }
+
+ return true;
+
+indirection_fail:
+ munmap(ctx->mmap_toeplitz_key, qemu_real_host_page_size());
+ ctx->mmap_toeplitz_key = NULL;
+toeplitz_fail:
+ munmap(ctx->mmap_configuration, qemu_real_host_page_size());
+ ctx->mmap_configuration = NULL;
+
+ ctx->mmap_indirections_table = NULL;
+ return false;
+}
+
+static void ebpf_rss_munmap(struct EBPFRSSContext *ctx)
+{
+ if (!ebpf_rss_is_loaded(ctx)) {
+ return;
+ }
+
+ munmap(ctx->mmap_indirections_table, qemu_real_host_page_size());
+ munmap(ctx->mmap_toeplitz_key, qemu_real_host_page_size());
+ munmap(ctx->mmap_configuration, qemu_real_host_page_size());
+
+ ctx->mmap_configuration = NULL;
+ ctx->mmap_toeplitz_key = NULL;
+ ctx->mmap_indirections_table = NULL;
}
bool ebpf_rss_load(struct EBPFRSSContext *ctx)
{
struct rss_bpf *rss_bpf_ctx;
- if (ctx == NULL) {
+ if (ebpf_rss_is_loaded(ctx)) {
return false;
}
rss_bpf_ctx = rss_bpf__open();
if (rss_bpf_ctx == NULL) {
- trace_ebpf_error("eBPF RSS", "can not open eBPF RSS object");
goto error;
}
bpf_program__set_type(rss_bpf_ctx->progs.tun_rss_steering_prog, BPF_PROG_TYPE_SOCKET_FILTER);
if (rss_bpf__load(rss_bpf_ctx)) {
- trace_ebpf_error("eBPF RSS", "can not load RSS program");
goto error;
}
@@ -66,26 +127,57 @@
ctx->map_toeplitz_key = bpf_map__fd(
rss_bpf_ctx->maps.tap_rss_map_toeplitz_key);
+ if (!ebpf_rss_mmap(ctx)) {
+ goto error;
+ }
+
return true;
error:
rss_bpf__destroy(rss_bpf_ctx);
ctx->obj = NULL;
+ ctx->program_fd = -1;
+ ctx->map_configuration = -1;
+ ctx->map_toeplitz_key = -1;
+ ctx->map_indirections_table = -1;
return false;
}
+bool ebpf_rss_load_fds(struct EBPFRSSContext *ctx, int program_fd,
+ int config_fd, int toeplitz_fd, int table_fd)
+{
+ if (ebpf_rss_is_loaded(ctx)) {
+ return false;
+ }
+
+ if (program_fd < 0 || config_fd < 0 || toeplitz_fd < 0 || table_fd < 0) {
+ return false;
+ }
+
+ ctx->program_fd = program_fd;
+ ctx->map_configuration = config_fd;
+ ctx->map_toeplitz_key = toeplitz_fd;
+ ctx->map_indirections_table = table_fd;
+
+ if (!ebpf_rss_mmap(ctx)) {
+ ctx->program_fd = -1;
+ ctx->map_configuration = -1;
+ ctx->map_toeplitz_key = -1;
+ ctx->map_indirections_table = -1;
+ return false;
+ }
+
+ return true;
+}
+
static bool ebpf_rss_set_config(struct EBPFRSSContext *ctx,
struct EBPFRSSConfig *config)
{
- uint32_t map_key = 0;
-
if (!ebpf_rss_is_loaded(ctx)) {
return false;
}
- if (bpf_map_update_elem(ctx->map_configuration,
- &map_key, config, 0) < 0) {
- return false;
- }
+
+ memcpy(ctx->mmap_configuration, config, sizeof(*config));
return true;
}
@@ -93,27 +185,19 @@
uint16_t *indirections_table,
size_t len)
{
- uint32_t i = 0;
-
if (!ebpf_rss_is_loaded(ctx) || indirections_table == NULL ||
len > VIRTIO_NET_RSS_MAX_TABLE_LEN) {
return false;
}
- for (; i < len; ++i) {
- if (bpf_map_update_elem(ctx->map_indirections_table, &i,
- indirections_table + i, 0) < 0) {
- return false;
- }
- }
+ memcpy(ctx->mmap_indirections_table, indirections_table,
+ sizeof(*indirections_table) * len);
return true;
}
static bool ebpf_rss_set_toepliz_key(struct EBPFRSSContext *ctx,
uint8_t *toeplitz_key)
{
- uint32_t map_key = 0;
-
/* prepare toeplitz key */
uint8_t toe[VIRTIO_NET_RSS_MAX_KEY_SIZE] = {};
@@ -123,10 +207,7 @@
memcpy(toe, toeplitz_key, VIRTIO_NET_RSS_MAX_KEY_SIZE);
*(uint32_t *)toe = ntohl(*(uint32_t *)toe);
- if (bpf_map_update_elem(ctx->map_toeplitz_key, &map_key, toe,
- 0) < 0) {
- return false;
- }
+ memcpy(ctx->mmap_toeplitz_key, toe, VIRTIO_NET_RSS_MAX_KEY_SIZE);
return true;
}
@@ -160,6 +241,22 @@
return;
}
- rss_bpf__destroy(ctx->obj);
+ ebpf_rss_munmap(ctx);
+
+ if (ctx->obj) {
+ rss_bpf__destroy(ctx->obj);
+ } else {
+ close(ctx->program_fd);
+ close(ctx->map_configuration);
+ close(ctx->map_toeplitz_key);
+ close(ctx->map_indirections_table);
+ }
+
ctx->obj = NULL;
+ ctx->program_fd = -1;
+ ctx->map_configuration = -1;
+ ctx->map_toeplitz_key = -1;
+ ctx->map_indirections_table = -1;
}
+
+ebpf_binary_init(EBPF_PROGRAMID_RSS, rss_bpf__elf_bytes)
diff --git a/ebpf/ebpf_rss.h b/ebpf/ebpf_rss.h
index bf3f257..239242b 100644
--- a/ebpf/ebpf_rss.h
+++ b/ebpf/ebpf_rss.h
@@ -14,12 +14,19 @@
#ifndef QEMU_EBPF_RSS_H
#define QEMU_EBPF_RSS_H
+#define EBPF_RSS_MAX_FDS 4
+
struct EBPFRSSContext {
void *obj;
int program_fd;
int map_configuration;
int map_toeplitz_key;
int map_indirections_table;
+
+ /* mapped eBPF maps for direct access to omit bpf_map_update_elem() */
+ void *mmap_configuration;
+ void *mmap_toeplitz_key;
+ void *mmap_indirections_table;
};
struct EBPFRSSConfig {
@@ -36,6 +43,9 @@
bool ebpf_rss_load(struct EBPFRSSContext *ctx);
+bool ebpf_rss_load_fds(struct EBPFRSSContext *ctx, int program_fd,
+ int config_fd, int toeplitz_fd, int table_fd);
+
bool ebpf_rss_set_all(struct EBPFRSSContext *ctx, struct EBPFRSSConfig *config,
uint16_t *indirections_table, uint8_t *toeplitz_key);
diff --git a/ebpf/meson.build b/ebpf/meson.build
index 2f627d6..c5bf929 100644
--- a/ebpf/meson.build
+++ b/ebpf/meson.build
@@ -1 +1 @@
-system_ss.add(when: libbpf, if_true: files('ebpf_rss.c'), if_false: files('ebpf_rss-stub.c'))
+common_ss.add(when: libbpf, if_true: files('ebpf.c', 'ebpf_rss.c'), if_false: files('ebpf_rss-stub.c'))
diff --git a/ebpf/rss.bpf.skeleton.h b/ebpf/rss.bpf.skeleton.h
index 18eb2ad..aed4ef9 100644
--- a/ebpf/rss.bpf.skeleton.h
+++ b/ebpf/rss.bpf.skeleton.h
@@ -176,642 +176,647 @@
static inline const void *rss_bpf__elf_bytes(size_t *sz)
{
- *sz = 20440;
+ *sz = 20600;
return (const void *)"\
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+\x01\0\xbf\x19\0\0\0\0\0\0\xb7\x01\0\0\0\0\0\0\x63\x1a\x4c\xff\0\0\0\0\xbf\xa7\
+\0\0\0\0\0\0\x07\x07\0\0\x4c\xff\xff\xff\x18\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
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-\0\0\x3c\0\0\0\x7b\x1a\x48\xff\0\0\0\0\xbf\x91\0\0\0\0\0\0\x57\x01\0\0\xff\0\0\
-\0\x15\x01\x19\0\0\0\0\0\x57\x07\0\0\xff\0\0\0\x55\x07\x17\0\0\0\0\0\x57\x09\0\
-\0\xff\0\0\0\x15\x09\x5a\x01\x11\0\0\0\x55\x09\x14\0\x06\0\0\0\xb7\x01\0\0\x01\
-\0\0\0\x73\x1a\x5b\xff\0\0\0\0\xb7\x01\0\0\0\0\0\0\x63\x1a\xe0\xff\0\0\0\0\x7b\
-\x1a\xd8\xff\0\0\0\0\x7b\x1a\xd0\xff\0\0\0\0\xbf\xa3\0\0\0\0\0\0\x07\x03\0\0\
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+\x34\x36\0\x4c\x42\x42\x30\x5f\x31\x30\x36\0\x4c\x42\x42\x30\x5f\x39\x35\0\x4c\
+\x42\x42\x30\x5f\x37\x35\0\x4c\x42\x42\x30\x5f\x36\x35\0\x4c\x42\x42\x30\x5f\
+\x34\x35\0\x4c\x42\x42\x30\x5f\x34\0\x4c\x42\x42\x30\x5f\x36\x34\0\x4c\x42\x42\
+\x30\x5f\x34\x34\0\x4c\x42\x42\x30\x5f\x33\x34\0\x4c\x42\x42\x30\x5f\x31\x30\
+\x34\0\x4c\x42\x42\x30\x5f\x35\x33\0\x4c\x42\x42\x30\x5f\x34\x33\0\x4c\x42\x42\
+\x30\x5f\x33\x33\0\x4c\x42\x42\x30\x5f\x32\x33\0\x4c\x42\x42\x30\x5f\x31\x30\
+\x33\0\x4c\x42\x42\x30\x5f\x39\x32\0\x4c\x42\x42\x30\x5f\x38\x32\0\x4c\x42\x42\
+\x30\x5f\x35\x32\0\x4c\x42\x42\x30\x5f\x34\x32\0\x4c\x42\x42\x30\x5f\x32\x32\0\
+\x4c\x42\x42\x30\x5f\x31\x30\x32\0\x4c\x42\x42\x30\x5f\x38\x31\0\x4c\x42\x42\
+\x30\x5f\x35\x31\0\x4c\x42\x42\x30\x5f\x31\x31\0\x4c\x42\x42\x30\x5f\x31\x30\
+\x31\0\x4c\x42\x42\x30\x5f\x39\x30\0\x4c\x42\x42\x30\x5f\x38\x30\0\x4c\x42\x42\
+\x30\x5f\x37\x30\0\x4c\x42\x42\x30\x5f\x36\x30\0\x4c\x42\x42\x30\x5f\x35\x30\0\
+\x4c\x42\x42\x30\x5f\x34\x30\0\x4c\x42\x42\x30\x5f\x32\x30\0\x4c\x42\x42\x30\
+\x5f\x31\x30\x30\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
+\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xa4\0\0\0\
+\x03\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xe5\x4a\0\0\0\0\0\0\x53\x02\0\0\0\0\
+\0\0\0\0\0\0\0\0\0\0\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x1a\0\0\0\x01\0\0\0\x06\
+\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x40\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
+\0\x04\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x31\0\0\0\x01\0\0\0\x06\0\0\0\0\0\0\0\0\0\
+\0\0\0\0\0\0\x40\0\0\0\0\0\0\0\xb0\x13\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x08\0\0\0\0\
+\0\0\0\0\0\0\0\0\0\0\0\x2d\0\0\0\x09\0\0\0\x40\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
+\xb0\x3d\0\0\0\0\0\0\x30\0\0\0\0\0\0\0\x0c\0\0\0\x03\0\0\0\x08\0\0\0\0\0\0\0\
+\x10\0\0\0\0\0\0\0\x38\0\0\0\x01\0\0\0\x03\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xf0\
+\x13\0\0\0\0\0\0\x78\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x08\0\0\0\0\0\0\0\0\0\0\0\0\
+\0\0\0\x7e\0\0\0\x01\0\0\0\x03\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x68\x14\0\0\0\0\0\
+\0\x07\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xb8\0\0\
+\0\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x70\x14\0\0\0\0\0\0\xf5\x16\0\0\0\
+\0\0\0\0\0\0\0\0\0\0\0\x04\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xb4\0\0\0\x09\0\0\0\
+\x40\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xe0\x3d\0\0\0\0\0\0\x40\0\0\0\0\0\0\0\x0c\0\
+\0\0\x07\0\0\0\x08\0\0\0\0\0\0\0\x10\0\0\0\0\0\0\0\x24\0\0\0\x01\0\0\0\0\0\0\0\
+\0\0\0\0\0\0\0\0\0\0\0\0\x68\x2b\0\0\0\0\0\0\xf0\x0c\0\0\0\0\0\0\0\0\0\0\0\0\0\
+\0\x04\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x20\0\0\0\x09\0\0\0\x40\0\0\0\0\0\0\0\0\0\
+\0\0\0\0\0\0\x20\x3e\0\0\0\0\0\0\xc0\x0c\0\0\0\0\0\0\x0c\0\0\0\x09\0\0\0\x08\0\
+\0\0\0\0\0\0\x10\0\0\0\0\0\0\0\x6f\0\0\0\x03\x4c\xff\x6f\0\0\0\x80\0\0\0\0\0\0\
+\0\0\0\0\0\0\xe0\x4a\0\0\0\0\0\0\x05\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x01\0\0\0\0\
+\0\0\0\0\0\0\0\0\0\0\0\xac\0\0\0\x02\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x58\
+\x38\0\0\0\0\0\0\x58\x05\0\0\0\0\0\0\x01\0\0\0\x34\0\0\0\x08\0\0\0\0\0\0\0\x18\
+\0\0\0\0\0\0\0";
}
#ifdef __cplusplus
diff --git a/ebpf/trace.h b/ebpf/trace.h
deleted file mode 100644
index abefc46..0000000
--- a/ebpf/trace.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "trace/trace-ebpf.h"
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
index d5de540..9146269 100644
--- a/hw/arm/gumstix.c
+++ b/hw/arm/gumstix.c
@@ -106,6 +106,7 @@
mc->desc = "Gumstix Connex (PXA255)";
mc->init = connex_init;
mc->ignore_memory_transaction_failures = true;
+ mc->deprecation_reason = "machine is old and unmaintained";
}
static const TypeInfo connex_type = {
@@ -121,6 +122,7 @@
mc->desc = "Gumstix Verdex Pro XL6P COMs (PXA270)";
mc->init = verdex_init;
mc->ignore_memory_transaction_failures = true;
+ mc->deprecation_reason = "machine is old and unmaintained";
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
}
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index d2e2e68..3a6c22f 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -169,6 +169,7 @@
mc->init = mainstone_init;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
+ mc->deprecation_reason = "machine is old and unmaintained";
}
DEFINE_MACHINE("mainstone", mainstone2_machine_init)
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index 35deb74..3536431 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -1430,6 +1430,7 @@
/* Actually two chips of 0x4000000 bytes each */
mc->default_ram_size = 0x08000000;
mc->default_ram_id = "omap2.dram";
+ mc->deprecation_reason = "machine is old and unmaintained";
machine_add_audiodev_property(mc);
}
@@ -1452,6 +1453,7 @@
/* Actually two chips of 0x4000000 bytes each */
mc->default_ram_size = 0x08000000;
mc->default_ram_id = "omap2.dram";
+ mc->deprecation_reason = "machine is old and unmaintained";
machine_add_audiodev_property(mc);
}
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index 8c4c831..e04ac92 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -309,6 +309,7 @@
mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
mc->default_ram_size = 0x02000000;
mc->default_ram_id = "omap1.dram";
+ mc->deprecation_reason = "machine is old and unmaintained";
machine_add_audiodev_property(mc);
}
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index 643a02b..62cd55b 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -1041,6 +1041,7 @@
mc->block_default_type = IF_IDE;
mc->ignore_memory_transaction_failures = true;
mc->init = spitz_common_init;
+ mc->deprecation_reason = "machine is old and unmaintained";
machine_add_audiodev_property(mc);
}
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index 3ca2e44..5891f60 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -270,6 +270,7 @@
mc->init = tosa_init;
mc->block_default_type = IF_IDE;
mc->ignore_memory_transaction_failures = true;
+ mc->deprecation_reason = "machine is old and unmaintained";
}
DEFINE_MACHINE("tosa", tosapda_machine_init)
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index eb2ff8d..fc5672e 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -347,6 +347,7 @@
mc->init = z2_init;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
+ mc->deprecation_reason = "machine is old and unmaintained";
machine_add_audiodev_property(mc);
}
diff --git a/hw/block/virtio-blk.c b/hw/block/virtio-blk.c
index 738cb2a..92de315 100644
--- a/hw/block/virtio-blk.c
+++ b/hw/block/virtio-blk.c
@@ -1682,6 +1682,7 @@
/* Context: BQL held */
static bool virtio_blk_vq_aio_context_init(VirtIOBlock *s, Error **errp)
{
+ ERRP_GUARD();
VirtIODevice *vdev = VIRTIO_DEVICE(s);
VirtIOBlkConf *conf = &s->conf;
BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(vdev)));
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index 0108fb1..4bd9c70 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -22,14 +22,10 @@
#include "qapi/error.h"
#include "hw/core/cpu.h"
#include "sysemu/hw_accel.h"
-#include "qemu/notify.h"
#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "exec/log.h"
-#include "exec/cpu-common.h"
#include "exec/gdbstub.h"
-#include "qemu/error-report.h"
-#include "qemu/qemu-print.h"
#include "sysemu/tcg.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
diff --git a/hw/core/loader-fit.c b/hw/core/loader-fit.c
index b7c7b3b..9f20007 100644
--- a/hw/core/loader-fit.c
+++ b/hw/core/loader-fit.c
@@ -120,6 +120,7 @@
int cfg, void *opaque, hwaddr *pend,
Error **errp)
{
+ ERRP_GUARD();
const char *name;
const void *data;
const void *load_data;
@@ -178,6 +179,7 @@
int cfg, void *opaque, const void *match_data,
hwaddr kernel_end, Error **errp)
{
+ ERRP_GUARD();
Error *err = NULL;
const char *name;
const void *data;
diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c
index 3860a50..4b72009 100644
--- a/hw/core/machine-qmp-cmds.c
+++ b/hw/core/machine-qmp-cmds.c
@@ -19,7 +19,6 @@
#include "qapi/qmp/qobject.h"
#include "qapi/qobject-input-visitor.h"
#include "qapi/type-helpers.h"
-#include "qemu/main-loop.h"
#include "qemu/uuid.h"
#include "qom/qom-qobject.h"
#include "sysemu/hostmem.h"
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 4b89172..37ede0e 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -34,6 +34,7 @@
#include "audio/audio.h"
GlobalProperty hw_compat_8_2[] = {
+ { "migration", "zero-page-detection", "legacy"},
{ TYPE_VIRTIO_IOMMU_PCI, "granule", "4k" },
{ TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "64" },
};
@@ -104,6 +105,7 @@
{ "PIIX4_PM", "smm-compat", "on"},
{ "virtio-blk-device", "report-discard-granularity", "off" },
{ "virtio-net-pci-base", "vectors", "3"},
+ { "nvme", "msix-exclusive-bar", "on"},
};
const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2);
@@ -720,7 +722,7 @@
mc->possible_cpu_arch_ids(machine);
for (i = 0; i < machine->possible_cpus->len; i++) {
- Object *cpu;
+ CPUState *cpu;
HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type);
@@ -730,7 +732,7 @@
cpu = machine->possible_cpus->cpus[i].cpu;
if (cpu) {
- cpu_item->qom_path = object_get_canonical_path(cpu);
+ cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu));
}
QAPI_LIST_PREPEND(head, cpu_item);
}
diff --git a/hw/core/numa.c b/hw/core/numa.c
index 58a32f1..f8ce332 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -28,7 +28,6 @@
#include "sysemu/numa.h"
#include "exec/cpu-common.h"
#include "exec/ramlist.h"
-#include "qemu/bitmap.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qapi/opts-visitor.h"
@@ -36,7 +35,6 @@
#include "sysemu/qtest.h"
#include "hw/core/cpu.h"
#include "hw/mem/pc-dimm.h"
-#include "migration/vmstate.h"
#include "hw/boards.h"
#include "hw/mem/memory-device.h"
#include "qemu/option.h"
diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c
index 28ce616..d79d6f4 100644
--- a/hw/core/qdev-properties-system.c
+++ b/hw/core/qdev-properties-system.c
@@ -242,6 +242,7 @@
static void set_chr(Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp)
{
+ ERRP_GUARD();
Property *prop = opaque;
CharBackend *be = object_field_prop_ptr(obj, prop);
Chardev *s;
@@ -693,6 +694,16 @@
.set_default_value = qdev_propinfo_set_default_value_enum,
};
+const PropertyInfo qdev_prop_zero_page_detection = {
+ .name = "ZeroPageDetection",
+ .description = "zero_page_detection values, "
+ "none,legacy,multifd",
+ .enum_table = &ZeroPageDetection_lookup,
+ .get = qdev_propinfo_get_enum,
+ .set = qdev_propinfo_set_enum,
+ .set_default_value = qdev_propinfo_set_default_value_enum,
+};
+
/* --- Reserved Region --- */
/*
diff --git a/hw/display/ati.c b/hw/display/ati.c
index 569b8f6..8d2501b 100644
--- a/hw/display/ati.c
+++ b/hw/display/ati.c
@@ -991,7 +991,7 @@
}
vga_init(vga, OBJECT(s), pci_address_space(dev),
pci_address_space_io(dev), true);
- vga->con = graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, &s->vga);
+ vga->con = graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, vga);
if (s->cursor_guest_mode) {
vga->cursor_invalidate = ati_cursor_invalidate;
vga->cursor_draw_line = ati_cursor_draw_line;
diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c
index 1c1ee23..78d5a4f 100644
--- a/hw/display/virtio-gpu.c
+++ b/hw/display/virtio-gpu.c
@@ -600,6 +600,7 @@
static void virtio_gpu_update_scanout(VirtIOGPU *g,
uint32_t scanout_id,
struct virtio_gpu_simple_resource *res,
+ struct virtio_gpu_framebuffer *fb,
struct virtio_gpu_rect *r)
{
struct virtio_gpu_simple_resource *ores;
@@ -617,9 +618,10 @@
scanout->y = r->y;
scanout->width = r->width;
scanout->height = r->height;
+ scanout->fb = *fb;
}
-static void virtio_gpu_do_set_scanout(VirtIOGPU *g,
+static bool virtio_gpu_do_set_scanout(VirtIOGPU *g,
uint32_t scanout_id,
struct virtio_gpu_framebuffer *fb,
struct virtio_gpu_simple_resource *res,
@@ -645,7 +647,7 @@
r->x, r->y, r->width, r->height,
fb->width, fb->height);
*error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
- return;
+ return false;
}
g->parent_obj.enable = 1;
@@ -653,11 +655,12 @@
if (res->blob) {
if (console_has_gl(scanout->con)) {
if (!virtio_gpu_update_dmabuf(g, scanout_id, res, fb, r)) {
- virtio_gpu_update_scanout(g, scanout_id, res, r);
+ virtio_gpu_update_scanout(g, scanout_id, res, fb, r);
} else {
*error = VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY;
+ return false;
}
- return;
+ return true;
}
data = res->blob;
@@ -684,10 +687,6 @@
/* realloc the surface ptr */
scanout->ds = qemu_create_displaysurface_pixman(rect);
- if (!scanout->ds) {
- *error = VIRTIO_GPU_RESP_ERR_UNSPEC;
- return;
- }
#ifdef WIN32
qemu_displaysurface_win32_set_handle(scanout->ds, res->handle, fb->offset);
#endif
@@ -697,7 +696,8 @@
scanout->ds);
}
- virtio_gpu_update_scanout(g, scanout_id, res, r);
+ virtio_gpu_update_scanout(g, scanout_id, res, fb, r);
+ return true;
}
static void virtio_gpu_set_scanout(VirtIOGPU *g,
@@ -1168,7 +1168,8 @@
static const VMStateDescription vmstate_virtio_gpu_scanout = {
.name = "virtio-gpu-one-scanout",
- .version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 1,
.fields = (const VMStateField[]) {
VMSTATE_UINT32(resource_id, struct virtio_gpu_scanout),
VMSTATE_UINT32(width, struct virtio_gpu_scanout),
@@ -1180,6 +1181,12 @@
VMSTATE_UINT32(cursor.hot_y, struct virtio_gpu_scanout),
VMSTATE_UINT32(cursor.pos.x, struct virtio_gpu_scanout),
VMSTATE_UINT32(cursor.pos.y, struct virtio_gpu_scanout),
+ VMSTATE_UINT32_V(fb.format, struct virtio_gpu_scanout, 2),
+ VMSTATE_UINT32_V(fb.bytes_pp, struct virtio_gpu_scanout, 2),
+ VMSTATE_UINT32_V(fb.width, struct virtio_gpu_scanout, 2),
+ VMSTATE_UINT32_V(fb.height, struct virtio_gpu_scanout, 2),
+ VMSTATE_UINT32_V(fb.stride, struct virtio_gpu_scanout, 2),
+ VMSTATE_UINT32_V(fb.offset, struct virtio_gpu_scanout, 2),
VMSTATE_END_OF_LIST()
},
};
@@ -1351,6 +1358,7 @@
if (!res->blob_size) {
continue;
}
+ assert(!res->image);
qemu_put_be32(f, res->resource_id);
qemu_put_be32(f, res->blob_size);
qemu_put_be32(f, res->iov_cnt);
@@ -1413,24 +1421,40 @@
int i;
for (i = 0; i < g->parent_obj.conf.max_outputs; i++) {
- /* FIXME: should take scanout.r.{x,y} into account */
scanout = &g->parent_obj.scanout[i];
if (!scanout->resource_id) {
continue;
}
+
res = virtio_gpu_find_resource(g, scanout->resource_id);
if (!res) {
return -EINVAL;
}
- scanout->ds = qemu_create_displaysurface_pixman(res->image);
- if (!scanout->ds) {
- return -EINVAL;
- }
-#ifdef WIN32
- qemu_displaysurface_win32_set_handle(scanout->ds, res->handle, 0);
-#endif
- dpy_gfx_replace_surface(scanout->con, scanout->ds);
+ if (scanout->fb.format != 0) {
+ uint32_t error = 0;
+ struct virtio_gpu_rect r = {
+ .x = scanout->x,
+ .y = scanout->y,
+ .width = scanout->width,
+ .height = scanout->height
+ };
+
+ if (!virtio_gpu_do_set_scanout(g, i, &scanout->fb, res, &r, &error)) {
+ return -EINVAL;
+ }
+ } else {
+ /* legacy v1 migration support */
+ if (!res->image) {
+ return -EINVAL;
+ }
+ scanout->ds = qemu_create_displaysurface_pixman(res->image);
+#ifdef WIN32
+ qemu_displaysurface_win32_set_handle(scanout->ds, res->handle, 0);
+#endif
+ dpy_gfx_replace_surface(scanout->con, scanout->ds);
+ }
+
dpy_gfx_update_full(scanout->con);
if (scanout->cursor.resource_id) {
update_cursor(g, &scanout->cursor);
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
index 712940b..19c97cc 100644
--- a/hw/gpio/Kconfig
+++ b/hw/gpio/Kconfig
@@ -19,3 +19,7 @@
config STM32L4X5_GPIO
bool
+
+config PCF8574
+ bool
+ depends on I2C
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
index 3454b50..791e93a 100644
--- a/hw/gpio/meson.build
+++ b/hw/gpio/meson.build
@@ -16,3 +16,4 @@
system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio.c'))
system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
+system_ss.add(when: 'CONFIG_PCF8574', if_true: files('pcf8574.c'))
diff --git a/hw/gpio/pcf8574.c b/hw/gpio/pcf8574.c
new file mode 100644
index 0000000..d37909e
--- /dev/null
+++ b/hw/gpio/pcf8574.c
@@ -0,0 +1,162 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * NXP PCF8574 8-port I2C GPIO expansion chip.
+ * Copyright (c) 2024 KNS Group (YADRO).
+ * Written by Dmitrii Sharikhin <d.sharikhin@yadro.com>
+ */
+
+#include "qemu/osdep.h"
+#include "hw/i2c/i2c.h"
+#include "hw/gpio/pcf8574.h"
+#include "hw/irq.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qom/object.h"
+
+/*
+ * PCF8574 and compatible chips incorporate quasi-bidirectional
+ * IO. Electrically it means that device sustain pull-up to line
+ * unless IO port is configured as output _and_ driven low.
+ *
+ * IO access is implemented as simple I2C single-byte read
+ * or write operation. So, to configure line to input user write 1
+ * to corresponding bit. To configure line to output and drive it low
+ * user write 0 to corresponding bit.
+ *
+ * In essence, user can think of quasi-bidirectional IO as
+ * open-drain line, except presence of builtin rising edge acceleration
+ * embedded in PCF8574 IC
+ *
+ * PCF8574 has interrupt request line, which is being pulled down when
+ * port line state differs from last read. Port read operation clears
+ * state and INT line returns to high state via pullup.
+ */
+
+OBJECT_DECLARE_SIMPLE_TYPE(PCF8574State, PCF8574)
+
+#define PORTS_COUNT (8)
+
+struct PCF8574State {
+ I2CSlave parent_obj;
+ uint8_t lastrq; /* Last requested state. If changed - assert irq */
+ uint8_t input; /* external electrical line state */
+ uint8_t output; /* Pull-up (1) or drive low (0) on bit */
+ qemu_irq handler[PORTS_COUNT];
+ qemu_irq intrq; /* External irq request */
+};
+
+static void pcf8574_reset(DeviceState *dev)
+{
+ PCF8574State *s = PCF8574(dev);
+ s->lastrq = MAKE_64BIT_MASK(0, PORTS_COUNT);
+ s->input = MAKE_64BIT_MASK(0, PORTS_COUNT);
+ s->output = MAKE_64BIT_MASK(0, PORTS_COUNT);
+}
+
+static inline uint8_t pcf8574_line_state(PCF8574State *s)
+{
+ /* we driving line low or external circuit does that */
+ return s->input & s->output;
+}
+
+static uint8_t pcf8574_rx(I2CSlave *i2c)
+{
+ PCF8574State *s = PCF8574(i2c);
+ uint8_t linestate = pcf8574_line_state(s);
+ if (s->lastrq != linestate) {
+ s->lastrq = linestate;
+ if (s->intrq) {
+ qemu_set_irq(s->intrq, 1);
+ }
+ }
+ return linestate;
+}
+
+static int pcf8574_tx(I2CSlave *i2c, uint8_t data)
+{
+ PCF8574State *s = PCF8574(i2c);
+ uint8_t prev;
+ uint8_t diff;
+ uint8_t actual;
+ int line = 0;
+
+ prev = pcf8574_line_state(s);
+ s->output = data;
+ actual = pcf8574_line_state(s);
+
+ for (diff = (actual ^ prev); diff; diff &= ~(1 << line)) {
+ line = ctz32(diff);
+ if (s->handler[line]) {
+ qemu_set_irq(s->handler[line], (actual >> line) & 1);
+ }
+ }
+
+ if (s->intrq) {
+ qemu_set_irq(s->intrq, actual == s->lastrq);
+ }
+
+ return 0;
+}
+
+static const VMStateDescription vmstate_pcf8574 = {
+ .name = "pcf8574",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_I2C_SLAVE(parent_obj, PCF8574State),
+ VMSTATE_UINT8(lastrq, PCF8574State),
+ VMSTATE_UINT8(input, PCF8574State),
+ VMSTATE_UINT8(output, PCF8574State),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void pcf8574_gpio_set(void *opaque, int line, int level)
+{
+ PCF8574State *s = (PCF8574State *) opaque;
+ assert(line >= 0 && line < ARRAY_SIZE(s->handler));
+
+ if (level) {
+ s->input |= (1 << line);
+ } else {
+ s->input &= ~(1 << line);
+ }
+
+ if (pcf8574_line_state(s) != s->lastrq && s->intrq) {
+ qemu_set_irq(s->intrq, 0);
+ }
+}
+
+static void pcf8574_realize(DeviceState *dev, Error **errp)
+{
+ PCF8574State *s = PCF8574(dev);
+
+ qdev_init_gpio_in(dev, pcf8574_gpio_set, ARRAY_SIZE(s->handler));
+ qdev_init_gpio_out(dev, s->handler, ARRAY_SIZE(s->handler));
+ qdev_init_gpio_out_named(dev, &s->intrq, "nINT", 1);
+}
+
+static void pcf8574_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
+
+ k->recv = pcf8574_rx;
+ k->send = pcf8574_tx;
+ dc->realize = pcf8574_realize;
+ dc->reset = pcf8574_reset;
+ dc->vmsd = &vmstate_pcf8574;
+}
+
+static const TypeInfo pcf8574_infos[] = {
+ {
+ .name = TYPE_PCF8574,
+ .parent = TYPE_I2C_SLAVE,
+ .instance_size = sizeof(PCF8574State),
+ .class_init = pcf8574_class_init,
+ }
+};
+
+DEFINE_TYPES(pcf8574_infos);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 1590352..feb7a93 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -699,7 +699,8 @@
assert(MACHINE(pcms)->kernel_filename != NULL);
- fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
+ fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
+ &address_space_memory);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
rom_set_fw(fw_cfg);
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 807e09b..ffbda48 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -225,7 +225,7 @@
}
found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL);
- found_cpu->cpu = OBJECT(dev);
+ found_cpu->cpu = CPU(dev);
out:
error_propagate(errp, local_err);
}
diff --git a/hw/ide/ahci_internal.h b/hw/ide/ahci-internal.h
similarity index 100%
rename from hw/ide/ahci_internal.h
rename to hw/ide/ahci-internal.h
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index b8123bc..bfefad2 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -37,7 +37,7 @@
#include "hw/ide/pci.h"
#include "hw/ide/ahci-pci.h"
#include "hw/ide/ahci-sysbus.h"
-#include "ahci_internal.h"
+#include "ahci-internal.h"
#include "ide-internal.h"
#include "trace.h"
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index 3ea793d..9b909c8 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -70,7 +70,7 @@
#include "sysemu/dma.h"
#include "hw/ide/pci.h"
#include "hw/ide/ahci-pci.h"
-#include "ahci_internal.h"
+#include "ahci-internal.h"
#define ICH9_MSI_CAP_OFFSET 0x80
#define ICH9_SATA_CAP_OFFSET 0xA8
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 1e98d8b..efce112 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -858,7 +858,7 @@
for (i = 0; i < possible_cpus->len; i++) {
cpu = cpu_create(machine->cpu_type);
cpu->cpu_index = i;
- machine->possible_cpus->cpus[i].cpu = OBJECT(cpu);
+ machine->possible_cpus->cpus[i].cpu = cpu;
lacpu = LOONGARCH_CPU(cpu);
lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id;
}
diff --git a/hw/m68k/virt.c b/hw/m68k/virt.c
index e2792ef..b8e5e10 100644
--- a/hw/m68k/virt.c
+++ b/hw/m68k/virt.c
@@ -239,9 +239,20 @@
param_ptr = param_blob;
BOOTINFO1(param_ptr, BI_MACHTYPE, MACH_VIRT);
- BOOTINFO1(param_ptr, BI_FPUTYPE, FPU_68040);
- BOOTINFO1(param_ptr, BI_MMUTYPE, MMU_68040);
- BOOTINFO1(param_ptr, BI_CPUTYPE, CPU_68040);
+ if (m68k_feature(&cpu->env, M68K_FEATURE_M68020)) {
+ BOOTINFO1(param_ptr, BI_CPUTYPE, CPU_68020);
+ } else if (m68k_feature(&cpu->env, M68K_FEATURE_M68030)) {
+ BOOTINFO1(param_ptr, BI_MMUTYPE, MMU_68030);
+ BOOTINFO1(param_ptr, BI_CPUTYPE, CPU_68030);
+ } else if (m68k_feature(&cpu->env, M68K_FEATURE_M68040)) {
+ BOOTINFO1(param_ptr, BI_FPUTYPE, FPU_68040);
+ BOOTINFO1(param_ptr, BI_MMUTYPE, MMU_68040);
+ BOOTINFO1(param_ptr, BI_CPUTYPE, CPU_68040);
+ } else if (m68k_feature(&cpu->env, M68K_FEATURE_M68060)) {
+ BOOTINFO1(param_ptr, BI_FPUTYPE, FPU_68060);
+ BOOTINFO1(param_ptr, BI_MMUTYPE, MMU_68060);
+ BOOTINFO1(param_ptr, BI_CPUTYPE, CPU_68060);
+ }
BOOTINFO2(param_ptr, BI_MEMCHUNK, 0, ram_size);
BOOTINFO1(param_ptr, BI_VIRT_QEMU_VERSION,
diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c
index a2fd0bc..de49d1b 100644
--- a/hw/misc/ivshmem.c
+++ b/hw/misc/ivshmem.c
@@ -832,6 +832,7 @@
static void ivshmem_common_realize(PCIDevice *dev, Error **errp)
{
+ ERRP_GUARD();
IVShmemState *s = IVSHMEM_COMMON(dev);
Error *err = NULL;
uint8_t *pci_conf;
diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c
index e9a90da..e40c51b 100644
--- a/hw/misc/macio/pmu.c
+++ b/hw/misc/macio/pmu.c
@@ -737,8 +737,7 @@
timer_mod(s->one_sec_timer, s->one_sec_target);
if (s->has_adb) {
- qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
- dev, "adb.0");
+ qbus_init(adb_bus, sizeof(*adb_bus), TYPE_ADB_BUS, dev, "adb.0");
adb_register_autopoll_callback(adb_bus, pmu_adb_poll, s);
}
}
diff --git a/hw/misc/pvpanic-pci.c b/hw/misc/pvpanic-pci.c
index c01e4ce..83be95d 100644
--- a/hw/misc/pvpanic-pci.c
+++ b/hw/misc/pvpanic-pci.c
@@ -48,7 +48,7 @@
PVPanicPCIState *s = PVPANIC_PCI_DEVICE(dev);
PVPanicState *ps = &s->pvpanic;
- pvpanic_setup_io(&s->pvpanic, DEVICE(s), 2);
+ pvpanic_setup_io(ps, DEVICE(s), 2);
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &ps->mr);
}
diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c
index e324c02..3ae2a18 100644
--- a/hw/net/e1000e_core.c
+++ b/hw/net/e1000e_core.c
@@ -123,14 +123,6 @@
}
}
-static void
-e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer)
-{
- if (timer->running) {
- timer_del(timer->timer);
- }
-}
-
static inline void
e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer)
{
@@ -399,24 +391,6 @@
}
static void
-e1000e_intrmgr_pause(E1000ECore *core)
-{
- int i;
-
- e1000e_intmgr_timer_pause(&core->radv);
- e1000e_intmgr_timer_pause(&core->rdtr);
- e1000e_intmgr_timer_pause(&core->raid);
- e1000e_intmgr_timer_pause(&core->tidv);
- e1000e_intmgr_timer_pause(&core->tadv);
-
- e1000e_intmgr_timer_pause(&core->itr);
-
- for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
- e1000e_intmgr_timer_pause(&core->eitr[i]);
- }
-}
-
-static void
e1000e_intrmgr_reset(E1000ECore *core)
{
int i;
@@ -3334,12 +3308,6 @@
return 0;
}
-static inline void
-e1000e_autoneg_pause(E1000ECore *core)
-{
- timer_del(core->autoneg_timer);
-}
-
static void
e1000e_autoneg_resume(E1000ECore *core)
{
@@ -3351,22 +3319,6 @@
}
}
-static void
-e1000e_vm_state_change(void *opaque, bool running, RunState state)
-{
- E1000ECore *core = opaque;
-
- if (running) {
- trace_e1000e_vm_state_running();
- e1000e_intrmgr_resume(core);
- e1000e_autoneg_resume(core);
- } else {
- trace_e1000e_vm_state_stopped();
- e1000e_autoneg_pause(core);
- e1000e_intrmgr_pause(core);
- }
-}
-
void
e1000e_core_pci_realize(E1000ECore *core,
const uint16_t *eeprom_templ,
@@ -3379,9 +3331,6 @@
e1000e_autoneg_timer, core);
e1000e_intrmgr_pci_realize(core);
- core->vmstate =
- qemu_add_vm_change_state_handler(e1000e_vm_state_change, core);
-
for (i = 0; i < E1000E_NUM_QUEUES; i++) {
net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS);
}
@@ -3405,8 +3354,6 @@
e1000e_intrmgr_pci_unint(core);
- qemu_del_vm_change_state_handler(core->vmstate);
-
for (i = 0; i < E1000E_NUM_QUEUES; i++) {
net_tx_pkt_uninit(core->tx[i].tx_pkt);
}
@@ -3576,5 +3523,12 @@
*/
nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0;
+ /*
+ * we need to restart intrmgr timers, as an older version of
+ * QEMU can have stopped them before migration
+ */
+ e1000e_intrmgr_resume(core);
+ e1000e_autoneg_resume(core);
+
return 0;
}
diff --git a/hw/net/e1000e_core.h b/hw/net/e1000e_core.h
index 66b025c..01510ca 100644
--- a/hw/net/e1000e_core.h
+++ b/hw/net/e1000e_core.h
@@ -98,8 +98,6 @@
E1000IntrDelayTimer eitr[E1000E_MSIX_VEC_NUM];
- VMChangeStateEntry *vmstate;
-
uint32_t itr_guest_value;
uint32_t eitr_guest_value[E1000E_MSIX_VEC_NUM];
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 2a7a11a..bcd5f6c 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -161,14 +161,6 @@
}
static void
-igb_intmgr_timer_pause(IGBIntrDelayTimer *timer)
-{
- if (timer->running) {
- timer_del(timer->timer);
- }
-}
-
-static void
igb_intrmgr_on_msix_throttling_timer(void *opaque)
{
IGBIntrDelayTimer *timer = opaque;
@@ -213,16 +205,6 @@
}
static void
-igb_intrmgr_pause(IGBCore *core)
-{
- int i;
-
- for (i = 0; i < IGB_INTR_NUM; i++) {
- igb_intmgr_timer_pause(&core->eitr[i]);
- }
-}
-
-static void
igb_intrmgr_reset(IGBCore *core)
{
int i;
@@ -4290,12 +4272,6 @@
return 0;
}
-static inline void
-igb_autoneg_pause(IGBCore *core)
-{
- timer_del(core->autoneg_timer);
-}
-
static void
igb_autoneg_resume(IGBCore *core)
{
@@ -4307,22 +4283,6 @@
}
}
-static void
-igb_vm_state_change(void *opaque, bool running, RunState state)
-{
- IGBCore *core = opaque;
-
- if (running) {
- trace_e1000e_vm_state_running();
- igb_intrmgr_resume(core);
- igb_autoneg_resume(core);
- } else {
- trace_e1000e_vm_state_stopped();
- igb_autoneg_pause(core);
- igb_intrmgr_pause(core);
- }
-}
-
void
igb_core_pci_realize(IGBCore *core,
const uint16_t *eeprom_templ,
@@ -4335,8 +4295,6 @@
igb_autoneg_timer, core);
igb_intrmgr_pci_realize(core);
- core->vmstate = qemu_add_vm_change_state_handler(igb_vm_state_change, core);
-
for (i = 0; i < IGB_NUM_QUEUES; i++) {
net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS);
}
@@ -4360,8 +4318,6 @@
igb_intrmgr_pci_unint(core);
- qemu_del_vm_change_state_handler(core->vmstate);
-
for (i = 0; i < IGB_NUM_QUEUES; i++) {
net_tx_pkt_uninit(core->tx[i].tx_pkt);
}
@@ -4586,5 +4542,12 @@
*/
nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0;
+ /*
+ * we need to restart intrmgr timers, as an older version of
+ * QEMU can have stopped them before migration
+ */
+ igb_intrmgr_resume(core);
+ igb_autoneg_resume(core);
+
return 0;
}
diff --git a/hw/net/igb_core.h b/hw/net/igb_core.h
index bf8c46f..d70b54e 100644
--- a/hw/net/igb_core.h
+++ b/hw/net/igb_core.h
@@ -90,8 +90,6 @@
IGBIntrDelayTimer eitr[IGB_INTR_NUM];
- VMChangeStateEntry *vmstate;
-
uint32_t eitr_guest_value[IGB_INTR_NUM];
uint8_t permanent_mac[ETH_ALEN];
diff --git a/hw/net/pcnet.c b/hw/net/pcnet.c
index 494eab8..ad675ab 100644
--- a/hw/net/pcnet.c
+++ b/hw/net/pcnet.c
@@ -632,7 +632,7 @@
{
struct qemu_ether_header *hdr = (void *)buf;
if ((*(hdr->ether_dhost)&0x01) &&
- ((uint64_t *)&s->csr[8])[0] != 0LL) {
+ (s->csr[8] | s->csr[9] | s->csr[10] | s->csr[11]) != 0) {
uint8_t ladr[8] = {
s->csr[8] & 0xff, s->csr[8] >> 8,
s->csr[9] & 0xff, s->csr[9] >> 8,
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 27055a4..9959f19 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -42,6 +42,7 @@
#include "sysemu/sysemu.h"
#include "trace.h"
#include "monitor/qdev.h"
+#include "monitor/monitor.h"
#include "hw/pci/pci_device.h"
#include "net_rx_pkt.h"
#include "hw/virtio/vhost.h"
@@ -1328,14 +1329,53 @@
virtio_net_attach_ebpf_to_backend(n->nic, -1);
}
-static bool virtio_net_load_ebpf(VirtIONet *n)
+static bool virtio_net_load_ebpf_fds(VirtIONet *n, Error **errp)
{
- if (!virtio_net_attach_ebpf_to_backend(n->nic, -1)) {
- /* backend doesn't support steering ebpf */
- return false;
+ int fds[EBPF_RSS_MAX_FDS] = { [0 ... EBPF_RSS_MAX_FDS - 1] = -1};
+ int ret = true;
+ int i = 0;
+
+ ERRP_GUARD();
+
+ if (n->nr_ebpf_rss_fds != EBPF_RSS_MAX_FDS) {
+ error_setg(errp,
+ "Expected %d file descriptors but got %d",
+ EBPF_RSS_MAX_FDS, n->nr_ebpf_rss_fds);
+ return false;
+ }
+
+ for (i = 0; i < n->nr_ebpf_rss_fds; i++) {
+ fds[i] = monitor_fd_param(monitor_cur(), n->ebpf_rss_fds[i], errp);
+ if (*errp) {
+ ret = false;
+ goto exit;
+ }
}
- return ebpf_rss_load(&n->ebpf_rss);
+ ret = ebpf_rss_load_fds(&n->ebpf_rss, fds[0], fds[1], fds[2], fds[3]);
+
+exit:
+ if (!ret || *errp) {
+ for (i = 0; i < n->nr_ebpf_rss_fds && fds[i] != -1; i++) {
+ close(fds[i]);
+ }
+ }
+
+ return ret;
+}
+
+static bool virtio_net_load_ebpf(VirtIONet *n, Error **errp)
+{
+ bool ret = false;
+
+ if (virtio_net_attach_ebpf_to_backend(n->nic, -1)) {
+ if (!(n->ebpf_rss_fds
+ && virtio_net_load_ebpf_fds(n, errp))) {
+ ret = ebpf_rss_load(&n->ebpf_rss);
+ }
+ }
+
+ return ret;
}
static void virtio_net_unload_ebpf(VirtIONet *n)
@@ -3784,7 +3824,7 @@
net_rx_pkt_init(&n->rx_pkt);
if (virtio_has_feature(n->host_features, VIRTIO_NET_F_RSS)) {
- virtio_net_load_ebpf(n);
+ virtio_net_load_ebpf(n, errp);
}
}
@@ -3946,6 +3986,8 @@
VIRTIO_NET_F_RSS, false),
DEFINE_PROP_BIT64("hash", VirtIONet, host_features,
VIRTIO_NET_F_HASH_REPORT, false),
+ DEFINE_PROP_ARRAY("ebpf-rss-fds", VirtIONet, nr_ebpf_rss_fds,
+ ebpf_rss_fds, qdev_prop_string, char*),
DEFINE_PROP_BIT64("guest_rsc_ext", VirtIONet, host_features,
VIRTIO_NET_F_RSC_EXT, false),
DEFINE_PROP_UINT32("rsc_interval", VirtIONet, rsc_timeout,
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 40159f3..c2b17de 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -2855,7 +2855,7 @@
uint32_t nlb;
nvme_copy_source_range_parse(iocb->ranges, idx, iocb->format, NULL,
&nlb, NULL, NULL, NULL);
- copy_len += nlb + 1;
+ copy_len += nlb;
}
if (copy_len > ns->id_ns.mcl) {
@@ -5642,6 +5642,10 @@
} QEMU_PACKED uuid = {};
struct {
NvmeIdNsDescr hdr;
+ uint8_t v[NVME_NIDL_NGUID];
+ } QEMU_PACKED nguid = {};
+ struct {
+ NvmeIdNsDescr hdr;
uint64_t v;
} QEMU_PACKED eui64 = {};
struct {
@@ -5668,6 +5672,14 @@
pos += sizeof(uuid);
}
+ if (!nvme_nguid_is_null(&ns->params.nguid)) {
+ nguid.hdr.nidt = NVME_NIDT_NGUID;
+ nguid.hdr.nidl = NVME_NIDL_NGUID;
+ memcpy(nguid.v, ns->params.nguid.data, NVME_NIDL_NGUID);
+ memcpy(pos, &nguid, sizeof(nguid));
+ pos += sizeof(nguid);
+ }
+
if (ns->params.eui64) {
eui64.hdr.nidt = NVME_NIDT_EUI64;
eui64.hdr.nidl = NVME_NIDL_EUI64;
@@ -7794,6 +7806,11 @@
}
if (n->pmr.dev) {
+ if (params->msix_exclusive_bar) {
+ error_setg(errp, "not enough BARs available to enable PMR");
+ return false;
+ }
+
if (host_memory_backend_is_mapped(n->pmr.dev)) {
error_setg(errp, "can't use already busy memdev: %s",
object_get_canonical_path_component(OBJECT(n->pmr.dev)));
@@ -7999,13 +8016,18 @@
memory_region_set_enabled(&n->pmr.dev->mr, false);
}
-static uint64_t nvme_bar_size(unsigned total_queues, unsigned total_irqs,
- unsigned *msix_table_offset,
- unsigned *msix_pba_offset)
+static uint64_t nvme_mbar_size(unsigned total_queues, unsigned total_irqs,
+ unsigned *msix_table_offset,
+ unsigned *msix_pba_offset)
{
- uint64_t bar_size, msix_table_size, msix_pba_size;
+ uint64_t bar_size, msix_table_size;
bar_size = sizeof(NvmeBar) + 2 * total_queues * NVME_DB_SIZE;
+
+ if (total_irqs == 0) {
+ goto out;
+ }
+
bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB);
if (msix_table_offset) {
@@ -8020,11 +8042,10 @@
*msix_pba_offset = bar_size;
}
- msix_pba_size = QEMU_ALIGN_UP(total_irqs, 64) / 8;
- bar_size += msix_pba_size;
+ bar_size += QEMU_ALIGN_UP(total_irqs, 64) / 8;
- bar_size = pow2ceil(bar_size);
- return bar_size;
+out:
+ return pow2ceil(bar_size);
}
static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offset)
@@ -8032,7 +8053,7 @@
uint16_t vf_dev_id = n->params.use_intel_id ?
PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_NVME;
NvmePriCtrlCap *cap = &n->pri_ctrl_cap;
- uint64_t bar_size = nvme_bar_size(le16_to_cpu(cap->vqfrsm),
+ uint64_t bar_size = nvme_mbar_size(le16_to_cpu(cap->vqfrsm),
le16_to_cpu(cap->vifrsm),
NULL, NULL);
@@ -8071,7 +8092,7 @@
ERRP_GUARD();
uint8_t *pci_conf = pci_dev->config;
uint64_t bar_size;
- unsigned msix_table_offset, msix_pba_offset;
+ unsigned msix_table_offset = 0, msix_pba_offset = 0;
int ret;
pci_conf[PCI_INTERRUPT_PIN] = 1;
@@ -8093,24 +8114,38 @@
pcie_ari_init(pci_dev, 0x100);
}
- /* add one to max_ioqpairs to account for the admin queue pair */
- bar_size = nvme_bar_size(n->params.max_ioqpairs + 1, n->params.msix_qsize,
- &msix_table_offset, &msix_pba_offset);
-
- memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size);
- memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme",
- msix_table_offset);
- memory_region_add_subregion(&n->bar0, 0, &n->iomem);
-
- if (pci_is_vf(pci_dev)) {
- pcie_sriov_vf_register_bar(pci_dev, 0, &n->bar0);
- } else {
+ if (n->params.msix_exclusive_bar && !pci_is_vf(pci_dev)) {
+ bar_size = nvme_mbar_size(n->params.max_ioqpairs + 1, 0, NULL, NULL);
+ memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme",
+ bar_size);
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
- PCI_BASE_ADDRESS_MEM_TYPE_64, &n->bar0);
+ PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem);
+ ret = msix_init_exclusive_bar(pci_dev, n->params.msix_qsize, 4, errp);
+ } else {
+ assert(n->params.msix_qsize >= 1);
+
+ /* add one to max_ioqpairs to account for the admin queue pair */
+ bar_size = nvme_mbar_size(n->params.max_ioqpairs + 1,
+ n->params.msix_qsize, &msix_table_offset,
+ &msix_pba_offset);
+
+ memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size);
+ memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme",
+ msix_table_offset);
+ memory_region_add_subregion(&n->bar0, 0, &n->iomem);
+
+ if (pci_is_vf(pci_dev)) {
+ pcie_sriov_vf_register_bar(pci_dev, 0, &n->bar0);
+ } else {
+ pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
+ PCI_BASE_ADDRESS_MEM_TYPE_64, &n->bar0);
+ }
+
+ ret = msix_init(pci_dev, n->params.msix_qsize,
+ &n->bar0, 0, msix_table_offset,
+ &n->bar0, 0, msix_pba_offset, 0, errp);
}
- ret = msix_init(pci_dev, n->params.msix_qsize,
- &n->bar0, 0, msix_table_offset,
- &n->bar0, 0, msix_pba_offset, 0, errp);
+
if (ret == -ENOTSUP) {
/* report that msix is not supported, but do not error out */
warn_report_err(*errp);
@@ -8305,9 +8340,15 @@
if (pci_is_vf(pci_dev)) {
/*
* VFs derive settings from the parent. PF's lifespan exceeds
- * that of VF's, so it's safe to share params.serial.
+ * that of VF's.
*/
memcpy(&n->params, &pn->params, sizeof(NvmeParams));
+
+ /*
+ * Set PF's serial value to a new string memory to prevent 'serial'
+ * property object release of PF when a VF is removed from the system.
+ */
+ n->params.serial = g_strdup(pn->params.serial);
n->subsys = pn->subsys;
}
@@ -8408,6 +8449,8 @@
params.sriov_max_vi_per_vf, 0),
DEFINE_PROP_UINT8("sriov_max_vq_per_vf", NvmeCtrl,
params.sriov_max_vq_per_vf, 0),
+ DEFINE_PROP_BOOL("msix-exclusive-bar", NvmeCtrl, params.msix_exclusive_bar,
+ false),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/nvme/meson.build b/hw/nvme/meson.build
index 1a6a2ca..7d5caa5 100644
--- a/hw/nvme/meson.build
+++ b/hw/nvme/meson.build
@@ -1 +1 @@
-system_ss.add(when: 'CONFIG_NVME_PCI', if_true: files('ctrl.c', 'dif.c', 'ns.c', 'subsys.c'))
+system_ss.add(when: 'CONFIG_NVME_PCI', if_true: files('ctrl.c', 'dif.c', 'ns.c', 'subsys.c', 'nguid.c'))
\ No newline at end of file
diff --git a/hw/nvme/nguid.c b/hw/nvme/nguid.c
new file mode 100644
index 0000000..829832b
--- /dev/null
+++ b/hw/nvme/nguid.c
@@ -0,0 +1,187 @@
+/*
+ * QEMU NVMe NGUID functions
+ *
+ * Copyright 2024 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/visitor.h"
+#include "qemu/ctype.h"
+#include "nvme.h"
+
+#define NGUID_SEPARATOR '-'
+
+#define NGUID_VALUE_AUTO "auto"
+
+#define NGUID_FMT \
+ "%02hhx%02hhx%02hhx%02hhx" \
+ "%02hhx%02hhx%02hhx%02hhx" \
+ "%02hhx%02hhx%02hhx%02hhx" \
+ "%02hhx%02hhx%02hhx%02hhx"
+
+#define NGUID_STR_LEN (2 * NGUID_LEN + 1)
+
+bool nvme_nguid_is_null(const NvmeNGUID *nguid)
+{
+ static NvmeNGUID null_nguid;
+ return memcmp(nguid, &null_nguid, sizeof(NvmeNGUID)) == 0;
+}
+
+static void nvme_nguid_generate(NvmeNGUID *out)
+{
+ int i;
+ uint32_t x;
+
+ QEMU_BUILD_BUG_ON((NGUID_LEN % sizeof(x)) != 0);
+
+ for (i = 0; i < NGUID_LEN; i += sizeof(x)) {
+ x = g_random_int();
+ memcpy(&out->data[i], &x, sizeof(x));
+ }
+}
+
+/*
+ * The Linux Kernel typically prints the NGUID of an NVMe namespace using the
+ * same format as the UUID. For instance:
+ *
+ * $ cat /sys/class/block/nvme0n1/nguid
+ * e9accd3b-8390-4e13-167c-f0593437f57d
+ *
+ * When there is no UUID but there is NGUID the Kernel will print the NGUID as
+ * wwid and it won't use the UUID format:
+ *
+ * $ cat /sys/class/block/nvme0n1/wwid
+ * eui.e9accd3b83904e13167cf0593437f57d
+ *
+ * The NGUID has different fields compared to the UUID, so the grouping used in
+ * the UUID format has no relation with the 3 fields of the NGUID.
+ *
+ * This implementation won't expect a strict format as the UUID one and instead
+ * it will admit any string of hexadecimal digits. Byte groups could be created
+ * using the '-' separator. The number of bytes needs to be exactly 16 and the
+ * separator '-' has to be exactly in a byte boundary. The following are
+ * examples of accepted formats for the NGUID string:
+ *
+ * nguid="e9accd3b-8390-4e13-167c-f0593437f57d"
+ * nguid="e9accd3b83904e13167cf0593437f57d"
+ * nguid="FEDCBA9876543210-ABCDEF-0123456789"
+ */
+static bool nvme_nguid_is_valid(const char *str)
+{
+ int i;
+ int digit_count = 0;
+
+ for (i = 0; i < strlen(str); i++) {
+ const char c = str[i];
+ if (qemu_isxdigit(c)) {
+ digit_count++;
+ continue;
+ }
+ if (c == NGUID_SEPARATOR) {
+ /*
+ * We need to make sure the separator is in a byte boundary, the
+ * string does not start with the separator and they are not back to
+ * back "--".
+ */
+ if ((i > 0) && (str[i - 1] != NGUID_SEPARATOR) &&
+ (digit_count % 2) == 0) {
+ continue;
+ }
+ }
+ return false;
+ }
+ /*
+ * The string should have the correct byte length and not finish with the
+ * separator
+ */
+ return (digit_count == (2 * NGUID_LEN)) && (str[i - 1] != NGUID_SEPARATOR);
+}
+
+static int nvme_nguid_parse(const char *str, NvmeNGUID *nguid)
+{
+ uint8_t *id = &nguid->data[0];
+ int ret = 0;
+ int i;
+ const char *ptr = str;
+
+ if (!nvme_nguid_is_valid(str)) {
+ return -1;
+ }
+
+ for (i = 0; i < NGUID_LEN; i++) {
+ ret = sscanf(ptr, "%02hhx", &id[i]);
+ if (ret != 1) {
+ return -1;
+ }
+ ptr += 2;
+ if (*ptr == NGUID_SEPARATOR) {
+ ptr++;
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * When converted back to string this implementation will use a raw hex number
+ * with no separators, for instance:
+ *
+ * "e9accd3b83904e13167cf0593437f57d"
+ */
+static void nvme_nguid_stringify(const NvmeNGUID *nguid, char *out)
+{
+ const uint8_t *id = &nguid->data[0];
+ snprintf(out, NGUID_STR_LEN, NGUID_FMT,
+ id[0], id[1], id[2], id[3], id[4], id[5], id[6], id[7],
+ id[8], id[9], id[10], id[11], id[12], id[13], id[14], id[15]);
+}
+
+static void get_nguid(Object *obj, Visitor *v, const char *name, void *opaque,
+ Error **errp)
+{
+ Property *prop = opaque;
+ NvmeNGUID *nguid = object_field_prop_ptr(obj, prop);
+ char buffer[NGUID_STR_LEN];
+ char *p = buffer;
+
+ nvme_nguid_stringify(nguid, buffer);
+
+ visit_type_str(v, name, &p, errp);
+}
+
+static void set_nguid(Object *obj, Visitor *v, const char *name, void *opaque,
+ Error **errp)
+{
+ Property *prop = opaque;
+ NvmeNGUID *nguid = object_field_prop_ptr(obj, prop);
+ char *str;
+
+ if (!visit_type_str(v, name, &str, errp)) {
+ return;
+ }
+
+ if (!strcmp(str, NGUID_VALUE_AUTO)) {
+ nvme_nguid_generate(nguid);
+ } else if (nvme_nguid_parse(str, nguid) < 0) {
+ error_set_from_qdev_prop_error(errp, EINVAL, obj, name, str);
+ }
+ g_free(str);
+}
+
+const PropertyInfo qdev_prop_nguid = {
+ .name = "str",
+ .description =
+ "NGUID or \"" NGUID_VALUE_AUTO "\" for random value",
+ .get = get_nguid,
+ .set = set_nguid,
+};
diff --git a/hw/nvme/ns.c b/hw/nvme/ns.c
index 0eabcf5..ea8db17 100644
--- a/hw/nvme/ns.c
+++ b/hw/nvme/ns.c
@@ -89,6 +89,7 @@
id_ns->mcl = cpu_to_le32(ns->params.mcl);
id_ns->msrc = ns->params.msrc;
id_ns->eui64 = cpu_to_be64(ns->params.eui64);
+ memcpy(&id_ns->nguid, &ns->params.nguid.data, sizeof(id_ns->nguid));
ds = 31 - clz32(ns->blkconf.logical_block_size);
ms = ns->params.ms;
@@ -797,6 +798,7 @@
DEFINE_PROP_BOOL("shared", NvmeNamespace, params.shared, true),
DEFINE_PROP_UINT32("nsid", NvmeNamespace, params.nsid, 0),
DEFINE_PROP_UUID_NODEFAULT("uuid", NvmeNamespace, params.uuid),
+ DEFINE_PROP_NGUID_NODEFAULT("nguid", NvmeNamespace, params.nguid),
DEFINE_PROP_UINT64("eui64", NvmeNamespace, params.eui64, 0),
DEFINE_PROP_UINT16("ms", NvmeNamespace, params.ms, 0),
DEFINE_PROP_UINT8("mset", NvmeNamespace, params.mset, 0),
diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h
index 5f2ae7b..bed8191 100644
--- a/hw/nvme/nvme.h
+++ b/hw/nvme/nvme.h
@@ -171,13 +171,27 @@
[FDP_EVT_RUH_IMPLICIT_RU_CHANGE] = 33,
};
+#define NGUID_LEN 16
+
+typedef struct {
+ uint8_t data[NGUID_LEN];
+} NvmeNGUID;
+
+bool nvme_nguid_is_null(const NvmeNGUID *nguid);
+
+extern const PropertyInfo qdev_prop_nguid;
+
+#define DEFINE_PROP_NGUID_NODEFAULT(_name, _state, _field) \
+ DEFINE_PROP(_name, _state, _field, qdev_prop_nguid, NvmeNGUID)
+
typedef struct NvmeNamespaceParams {
- bool detached;
- bool shared;
- uint32_t nsid;
- QemuUUID uuid;
- uint64_t eui64;
- bool eui64_default;
+ bool detached;
+ bool shared;
+ uint32_t nsid;
+ QemuUUID uuid;
+ NvmeNGUID nguid;
+ uint64_t eui64;
+ bool eui64_default;
uint16_t ms;
uint8_t mset;
@@ -522,6 +536,7 @@
uint16_t sriov_vi_flexible;
uint8_t sriov_max_vq_per_vf;
uint8_t sriov_max_vi_per_vf;
+ bool msix_exclusive_bar;
} NvmeParams;
typedef struct NvmeCtrl {
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
index 62f9699..8a30da6 100644
--- a/hw/pci-bridge/cxl_root_port.c
+++ b/hw/pci-bridge/cxl_root_port.c
@@ -175,7 +175,7 @@
cxl_cstate->dvsec_offset = CXL_ROOT_PORT_DVSEC_OFFSET;
cxl_cstate->pdev = pci_dev;
- build_dvsecs(&crp->cxl_cstate);
+ build_dvsecs(cxl_cstate);
cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate,
TYPE_CXL_ROOT_PORT);
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 0b4817e..4b2f080 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -28,6 +28,7 @@
#include "hw/pci/pcie_regs.h"
#include "hw/pci/pcie_port.h"
#include "qemu/range.h"
+#include "trace.h"
//#define DEBUG_PCIE
#ifdef DEBUG_PCIE
@@ -45,6 +46,23 @@
&& (sltctl & PCI_EXP_SLTCTL_PIC) == PCI_EXP_SLTCTL_PWR_IND_OFF;
}
+static const char *pcie_led_state_to_str(uint16_t value)
+{
+ switch (value) {
+ case PCI_EXP_SLTCTL_PWR_IND_ON:
+ case PCI_EXP_SLTCTL_ATTN_IND_ON:
+ return "on";
+ case PCI_EXP_SLTCTL_PWR_IND_BLINK:
+ case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
+ return "blink";
+ case PCI_EXP_SLTCTL_PWR_IND_OFF:
+ case PCI_EXP_SLTCTL_ATTN_IND_OFF:
+ return "off";
+ default:
+ return "invalid";
+ }
+}
+
/***************************************************************************
* pci express capability helper functions
*/
@@ -743,6 +761,28 @@
*slt_sta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
}
+static void find_child_fn(PCIBus *bus, PCIDevice *dev, void *opaque)
+{
+ PCIDevice **child = opaque;
+
+ if (!*child) {
+ *child = dev;
+ }
+}
+
+/*
+ * Returns the plugged device or first function of multifunction plugged device
+ */
+static PCIDevice *pcie_cap_slot_find_child(PCIDevice *dev)
+{
+ PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
+ PCIDevice *child = NULL;
+
+ pci_for_each_device(sec_bus, pci_bus_num(sec_bus), find_child_fn, &child);
+
+ return child;
+}
+
void pcie_cap_slot_write_config(PCIDevice *dev,
uint16_t old_slt_ctl, uint16_t old_slt_sta,
uint32_t addr, uint32_t val, int len)
@@ -787,6 +827,22 @@
sltsta);
}
+ if (trace_event_get_state_backends(TRACE_PCIE_CAP_SLOT_WRITE_CONFIG)) {
+ DeviceState *parent = DEVICE(dev);
+ DeviceState *child = DEVICE(pcie_cap_slot_find_child(dev));
+
+ trace_pcie_cap_slot_write_config(
+ parent->canonical_path,
+ child ? child->canonical_path : "no-child",
+ (sltsta & PCI_EXP_SLTSTA_PDS) ? "present" : "not present",
+ pcie_led_state_to_str(old_slt_ctl & PCI_EXP_SLTCTL_PIC),
+ pcie_led_state_to_str(val & PCI_EXP_SLTCTL_PIC),
+ pcie_led_state_to_str(old_slt_ctl & PCI_EXP_SLTCTL_AIC),
+ pcie_led_state_to_str(val & PCI_EXP_SLTCTL_AIC),
+ (old_slt_ctl & PCI_EXP_SLTCTL_PWR_OFF) ? "off" : "on",
+ (val & PCI_EXP_SLTCTL_PWR_OFF) ? "off" : "on");
+ }
+
/*
* If the slot is populated, power indicator is off and power
* controller is off, it is safe to detach the devices.
diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c
index d2a5eea..aac6f2d 100644
--- a/hw/pci/shpc.c
+++ b/hw/pci/shpc.c
@@ -8,6 +8,7 @@
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/msi.h"
+#include "trace.h"
/* TODO: model power only and disabled slot states. */
/* TODO: handle SERR and wakeups */
@@ -123,6 +124,34 @@
#define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
#define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
+static const char *shpc_led_state_to_str(uint8_t value)
+{
+ switch (value) {
+ case SHPC_LED_ON:
+ return "on";
+ case SHPC_LED_BLINK:
+ return "blink";
+ case SHPC_LED_OFF:
+ return "off";
+ default:
+ return "invalid";
+ }
+}
+
+static const char *shpc_slot_state_to_str(uint8_t value)
+{
+ switch (value) {
+ case SHPC_STATE_PWRONLY:
+ return "power-only";
+ case SHPC_STATE_ENABLED:
+ return "enabled";
+ case SHPC_STATE_DISABLED:
+ return "disabled";
+ default:
+ return "invalid";
+ }
+}
+
static uint8_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk)
{
uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
@@ -302,6 +331,23 @@
shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
}
+ if (trace_event_get_state_backends(TRACE_SHPC_SLOT_COMMAND)) {
+ DeviceState *parent = DEVICE(d);
+ int pci_slot = SHPC_IDX_TO_PCI(slot);
+ DeviceState *child =
+ DEVICE(shpc->sec_bus->devices[PCI_DEVFN(pci_slot, 0)]);
+
+ trace_shpc_slot_command(
+ parent->canonical_path, pci_slot,
+ child ? child->canonical_path : "no-child",
+ shpc_led_state_to_str(old_power),
+ shpc_led_state_to_str(power),
+ shpc_led_state_to_str(old_attn),
+ shpc_led_state_to_str(attn),
+ shpc_slot_state_to_str(old_state),
+ shpc_slot_state_to_str(state));
+ }
+
if (!shpc_slot_is_off(old_state, old_power, old_attn) &&
shpc_slot_is_off(state, power, attn))
{
diff --git a/hw/pci/trace-events b/hw/pci/trace-events
index 4243086..19643aa 100644
--- a/hw/pci/trace-events
+++ b/hw/pci/trace-events
@@ -16,3 +16,9 @@
sriov_register_vfs(const char *name, int slot, int function, int num_vfs) "%s %02x:%x: creating %d vf devs"
sriov_unregister_vfs(const char *name, int slot, int function, int num_vfs) "%s %02x:%x: Unregistering %d vf devs"
sriov_config_write(const char *name, int slot, int fun, uint32_t offset, uint32_t val, uint32_t len) "%s %02x:%x: sriov offset 0x%x val 0x%x len %d"
+
+# pcie.c
+pcie_cap_slot_write_config(const char *parent, const char *child, const char *pds, const char *old_pic, const char *new_pic, const char *old_aic, const char *new_aic, const char *old_power, const char *new_power) "%s > %s: pds: %s, pic: %s->%s, aic: %s->%s, power: %s->%s"
+
+# shpc.c
+shpc_slot_command(const char *parent, int pci_slot, const char *child, const char *old_pic, const char *new_pic, const char *old_aic, const char *new_aic, const char *old_state, const char *new_state) "%s[%d] > %s: pic: %s->%s, aic: %s->%s, state: %s->%s"
diff --git a/hw/ppc/mpc8544_guts.c b/hw/ppc/mpc8544_guts.c
index a26e83d..e3540b0 100644
--- a/hw/ppc/mpc8544_guts.c
+++ b/hw/ppc/mpc8544_guts.c
@@ -71,8 +71,7 @@
unsigned size)
{
uint32_t value = 0;
- PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(current_cpu);
addr &= MPC8544_GUTS_MMIO_SIZE - 1;
switch (addr) {
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 0b47b92..6e3a5cc 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -133,7 +133,7 @@
* device tree, used in XSCOM to address cores and in interrupt
* servers.
*/
-static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
+static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
{
PowerPCCPU *cpu = pc->threads[0];
CPUState *cs = CPU(cpu);
@@ -141,32 +141,31 @@
int smt_threads = CPU_CORE(pc)->nr_threads;
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
+ PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip);
g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
int i;
+ uint32_t pir;
uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
0xffffffff, 0xffffffff};
uint32_t tbfreq = PNV_TIMEBASE_FREQ;
uint32_t cpufreq = 1000000000;
uint32_t page_sizes_prop[64];
size_t page_sizes_prop_size;
- const uint8_t pa_features[] = { 24, 0,
- 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
- 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
int offset;
char *nodename;
int cpus_offset = get_cpus_node(fdt);
- nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
+ pir = pnv_cc->chip_pir(chip, pc->hwid, 0);
+
+ nodename = g_strdup_printf("%s@%x", dc->fw_name, pir);
offset = fdt_add_subnode(fdt, cpus_offset, nodename);
_FDT(offset);
g_free(nodename);
_FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
- _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
- _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
+ _FDT((fdt_setprop_cell(fdt, offset, "reg", pir)));
+ _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir)));
_FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
_FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
@@ -236,20 +235,21 @@
page_sizes_prop, page_sizes_prop_size)));
}
- _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
- pa_features, sizeof(pa_features))));
-
/* Build interrupt servers properties */
for (i = 0; i < smt_threads; i++) {
- servers_prop[i] = cpu_to_be32(pc->pir + i);
+ servers_prop[i] = cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i));
}
_FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
servers_prop, sizeof(*servers_prop) * smt_threads)));
+
+ return offset;
}
-static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
+static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid,
uint32_t nr_threads)
{
+ PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
+ uint32_t pir = pcc->chip_pir(chip, hwid, 0);
uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
char *name;
const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
@@ -263,6 +263,7 @@
rsize = sizeof(uint64_t) * 2 * nr_threads;
reg = g_malloc(rsize);
for (i = 0; i < nr_threads; i++) {
+ /* We know P8 PIR is linear with thread id */
reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
reg[i * 2 + 1] = cpu_to_be64(0x1000);
}
@@ -299,6 +300,17 @@
return chip;
}
+/*
+ * Same as spapr pa_features_207 except pnv always enables CI largepages bit.
+ * HTM is always enabled because TCG does implement HTM, it's just a
+ * degenerate implementation.
+ */
+static const uint8_t pa_features_207[] = { 24, 0,
+ 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0,
+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
+
static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
{
static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
@@ -311,11 +323,15 @@
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
+ int offset;
- pnv_dt_core(chip, pnv_core, fdt);
+ offset = pnv_dt_core(chip, pnv_core, fdt);
+
+ _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
+ pa_features_207, sizeof(pa_features_207))));
/* Interrupt Control Presenters (ICP). One per core. */
- pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
+ pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads);
}
if (chip->ram_size) {
@@ -323,6 +339,35 @@
}
}
+/*
+ * Same as spapr pa_features_300 except pnv always enables CI largepages bit.
+ */
+static const uint8_t pa_features_300[] = { 66, 0,
+ /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
+ /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
+ 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
+ /* 6: DS207 */
+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
+ /* 16: Vector */
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
+ /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
+ /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
+ /* 32: LE atomic, 34: EBB + ext EBB */
+ 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
+ /* 40: Radix MMU */
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
+ /* 42: PM, 44: PC RA, 46: SC vec'd */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
+ /* 48: SIMD, 50: QP BFP, 52: String */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
+ /* 54: DecFP, 56: DecI, 58: SHA */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
+ /* 60: NM atomic, 62: RNG */
+ 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
+};
+
static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
{
static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
@@ -335,8 +380,12 @@
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
+ int offset;
- pnv_dt_core(chip, pnv_core, fdt);
+ offset = pnv_dt_core(chip, pnv_core, fdt);
+
+ _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
+ pa_features_300, sizeof(pa_features_300))));
}
if (chip->ram_size) {
@@ -346,6 +395,40 @@
pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
}
+/*
+ * Same as spapr pa_features_31 except pnv always enables CI largepages bit,
+ * always disables copy/paste.
+ */
+static const uint8_t pa_features_31[] = { 74, 0,
+ /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
+ /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
+ 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
+ /* 6: DS207 */
+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
+ /* 16: Vector */
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
+ /* 18: Vec. Scalar, 20: Vec. XOR */
+ 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
+ /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
+ /* 32: LE atomic, 34: EBB + ext EBB */
+ 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
+ /* 40: Radix MMU */
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
+ /* 42: PM, 44: PC RA, 46: SC vec'd */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
+ /* 48: SIMD, 50: QP BFP, 52: String */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
+ /* 54: DecFP, 56: DecI, 58: SHA */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
+ /* 60: NM atomic, 62: RNG */
+ 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
+ /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */
+ 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
+ /* 72: [P]HASHST/[P]HASHCHK */
+ 0x80, 0x00, /* 72 - 73 */
+};
+
static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
{
static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
@@ -358,8 +441,12 @@
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
+ int offset;
- pnv_dt_core(chip, pnv_core, fdt);
+ offset = pnv_dt_core(chip, pnv_core, fdt);
+
+ _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
+ pa_features_31, sizeof(pa_features_31))));
}
if (chip->ram_size) {
@@ -995,9 +1082,10 @@
* 25:28 Core number
* 29:31 Thread ID
*/
-static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
+static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id,
+ uint32_t thread_id)
{
- return (chip->chip_id << 7) | (core_id << 3);
+ return (chip->chip_id << 7) | (core_id << 3) | thread_id;
}
static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
@@ -1049,14 +1137,37 @@
*
* We only care about the lower bits. uint32_t is fine for the moment.
*/
-static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
+static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id,
+ uint32_t thread_id)
{
- return (chip->chip_id << 8) | (core_id << 2);
+ if (chip->nr_threads == 8) {
+ return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id << 3) |
+ (thread_id >> 1);
+ } else {
+ return (chip->chip_id << 8) | (core_id << 2) | thread_id;
+ }
}
-static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
+/*
+ * 0:48 Reserved - Read as zeroes
+ * 49:52 Node ID
+ * 53:55 Chip ID
+ * 56 Reserved - Read as zero
+ * 57:59 Quad ID
+ * 60 Core Chiplet Pair ID
+ * 61:63 Thread/Core Chiplet ID t0-t2
+ *
+ * We only care about the lower bits. uint32_t is fine for the moment.
+ */
+static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id,
+ uint32_t thread_id)
{
- return (chip->chip_id << 8) | (core_id << 2);
+ if (chip->nr_threads == 8) {
+ return (chip->chip_id << 8) | ((core_id / 4) << 4) |
+ ((core_id % 2) << 3) | thread_id;
+ } else {
+ return (chip->chip_id << 8) | (core_id << 2) | thread_id;
+ }
}
static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
@@ -1235,7 +1346,7 @@
int core_hwid = CPU_CORE(pnv_core)->core_id;
for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
- uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
+ uint32_t pir = pcc->chip_pir(chip, core_hwid, j);
PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
@@ -1265,11 +1376,11 @@
}
/* Processor Service Interface (PSI) Host Bridge */
- object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip),
+ object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip),
&error_fatal);
- object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS,
+ object_property_set_link(OBJECT(psi8), ICS_PROP_XICS,
OBJECT(chip8->xics), &error_abort);
- if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) {
+ if (!qdev_realize(DEVICE(psi8), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
@@ -1300,7 +1411,7 @@
}
pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
qdev_connect_gpio_out(DEVICE(&chip8->occ), 0,
- qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC));
+ qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC));
/* OCC SRAM model */
memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
@@ -1348,7 +1459,7 @@
k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
k->cores_mask = POWER8E_CORE_MASK;
k->num_phbs = 3;
- k->core_pir = pnv_chip_core_pir_p8;
+ k->chip_pir = pnv_chip_pir_p8;
k->intc_create = pnv_chip_power8_intc_create;
k->intc_reset = pnv_chip_power8_intc_reset;
k->intc_destroy = pnv_chip_power8_intc_destroy;
@@ -1372,7 +1483,7 @@
k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
k->cores_mask = POWER8_CORE_MASK;
k->num_phbs = 3;
- k->core_pir = pnv_chip_core_pir_p8;
+ k->chip_pir = pnv_chip_pir_p8;
k->intc_create = pnv_chip_power8_intc_create;
k->intc_reset = pnv_chip_power8_intc_reset;
k->intc_destroy = pnv_chip_power8_intc_destroy;
@@ -1396,7 +1507,7 @@
k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
k->cores_mask = POWER8_CORE_MASK;
k->num_phbs = 4;
- k->core_pir = pnv_chip_core_pir_p8;
+ k->chip_pir = pnv_chip_pir_p8;
k->intc_create = pnv_chip_power8_intc_create;
k->intc_reset = pnv_chip_power8_intc_reset;
k->intc_destroy = pnv_chip_power8_intc_destroy;
@@ -1553,12 +1664,12 @@
&chip9->xive.xscom_regs);
/* Processor Service Interface (PSI) Host Bridge */
- object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip),
+ object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip),
&error_fatal);
/* This is the only device with 4k ESB pages */
- object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K,
+ object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K,
&error_fatal);
- if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) {
+ if (!qdev_realize(DEVICE(psi9), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
@@ -1594,7 +1705,7 @@
}
pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in(
- DEVICE(&chip9->psi), PSIHB9_IRQ_OCC));
+ DEVICE(psi9), PSIHB9_IRQ_OCC));
/* OCC SRAM model */
memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
@@ -1609,7 +1720,7 @@
pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE,
&chip9->sbe.xscom_mbox_regs);
qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in(
- DEVICE(&chip9->psi), PSIHB9_IRQ_PSU));
+ DEVICE(psi9), PSIHB9_IRQ_PSU));
/* HOMER */
object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip),
@@ -1650,7 +1761,7 @@
PNV9_XSCOM_I2CM_SIZE,
&chip9->i2c[i].xscom_regs);
qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0,
- qdev_get_gpio_in(DEVICE(&chip9->psi),
+ qdev_get_gpio_in(DEVICE(psi9),
PSIHB9_IRQ_SBE_I2C));
}
}
@@ -1669,7 +1780,7 @@
k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
k->cores_mask = POWER9_CORE_MASK;
- k->core_pir = pnv_chip_core_pir_p9;
+ k->chip_pir = pnv_chip_pir_p9;
k->intc_create = pnv_chip_power9_intc_create;
k->intc_reset = pnv_chip_power9_intc_reset;
k->intc_destroy = pnv_chip_power9_intc_destroy;
@@ -1981,7 +2092,7 @@
k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
k->cores_mask = POWER10_CORE_MASK;
- k->core_pir = pnv_chip_core_pir_p10;
+ k->chip_pir = pnv_chip_pir_p10;
k->intc_create = pnv_chip_power10_intc_create;
k->intc_reset = pnv_chip_power10_intc_reset;
k->intc_destroy = pnv_chip_power10_intc_destroy;
@@ -2071,8 +2182,8 @@
chip->nr_threads, &error_fatal);
object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
core_hwid, &error_fatal);
- object_property_set_int(OBJECT(pnv_core), "pir",
- pcc->core_pir(chip, core_hwid), &error_fatal);
+ object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid,
+ &error_fatal);
object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
&error_fatal);
object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
@@ -2412,8 +2523,7 @@
static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
cpu_synchronize_state(cs);
ppc_cpu_do_system_reset(cs);
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 8c7afe0..f40ab72 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -226,7 +226,7 @@
int thread_index)
{
CPUPPCState *env = &cpu->env;
- int core_pir;
+ int core_hwid;
ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
ppc_spr_t *tir = &env->spr_cb[SPR_TIR];
Error *local_err = NULL;
@@ -242,10 +242,10 @@
return;
}
- core_pir = object_property_get_uint(OBJECT(pc), "pir", &error_abort);
+ core_hwid = object_property_get_uint(OBJECT(pc), "hwid", &error_abort);
tir->default_value = thread_index;
- pir->default_value = core_pir + thread_index;
+ pir->default_value = pcc->chip_pir(pc->chip, core_hwid, thread_index);
/* Set time-base frequency to 512 MHz */
cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
@@ -342,7 +342,7 @@
}
static Property pnv_core_properties[] = {
- DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
+ DEFINE_PROP_UINT32("hwid", PnvCore, hwid, 0),
DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0),
DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *),
DEFINE_PROP_END_OF_LIST(),
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
index 805b1d0..a17816d 100644
--- a/hw/ppc/pnv_xscom.c
+++ b/hw/ppc/pnv_xscom.c
@@ -44,15 +44,12 @@
* passed for the cpu, and no CPU completion is generated.
*/
if (cs) {
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
-
/*
* TODO: Need a CPU helper to set HMER, also handle generation
* of HMIs
*/
cpu_synchronize_state(cs);
- env->spr[SPR_HMER] |= hmer_bits;
+ cpu_env(cs)->spr[SPR_HMER] |= hmer_bits;
}
}
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index fadb8f5..e6fa558 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -633,6 +633,16 @@
((uint64_t)value << 32) | tb);
}
+void cpu_ppc_increase_tb_by_offset(CPUPPCState *env, int64_t offset)
+{
+ env->tb_env->tb_offset += offset;
+}
+
+void cpu_ppc_decrease_tb_by_offset(CPUPPCState *env, int64_t offset)
+{
+ env->tb_env->tb_offset -= offset;
+}
+
uint64_t cpu_ppc_load_vtb(CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c
index bbce63e..dfbe759 100644
--- a/hw/ppc/ppce500_spin.c
+++ b/hw/ppc/ppce500_spin.c
@@ -90,8 +90,7 @@
static void spin_kick(CPUState *cs, run_on_cpu_data data)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
SpinInfo *curspin = data.host_ptr;
hwaddr map_size = 64 * MiB;
hwaddr map_start;
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 7e34b6c..d42b677 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -33,6 +33,7 @@
#include "hw/char/serial.h"
#include "hw/i2c/ppc4xx_i2c.h"
#include "hw/i2c/smbus_eeprom.h"
+#include "hw/ide/pci.h"
#include "hw/usb/hcd-ehci.h"
#include "hw/ppc/fdt.h"
#include "hw/qdev-properties.h"
@@ -449,15 +450,27 @@
/* PCI devices */
pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501");
- /* SoC has a single SATA port but we don't emulate that yet
+ /*
+ * SoC has a single SATA port but we don't emulate that
* However, firmware and usual clients have driver for SiI311x
- * so add one for convenience by default */
+ * PCI SATA card so add one for convenience by default
+ */
if (defaults_enabled()) {
- pci_create_simple(pci_bus, -1, "sii3112");
+ PCIIDEState *s = PCI_IDE(pci_create_simple(pci_bus, -1, "sii3112"));
+ DriveInfo *di;
+
+ di = drive_get_by_index(IF_IDE, 0);
+ if (di) {
+ ide_bus_create_drive(&s->bus[0], 0, di);
+ }
+ /* Use index 2 only if 1 does not exist, this allows -cdrom */
+ di = drive_get_by_index(IF_IDE, 1) ?: drive_get_by_index(IF_IDE, 2);
+ if (di) {
+ ide_bus_create_drive(&s->bus[1], 0, di);
+ }
}
- /* SoC has 4 UARTs
- * but board has only one wired and two are present in fdt */
+ /* SoC has 4 UARTs but board has only one wired and two described in fdt */
if (serial_hd(0) != NULL) {
serial_mm_init(get_system_memory(), 0x4ef600300, 0,
qdev_get_gpio_in(uic[1], 1),
@@ -531,6 +544,7 @@
{
mc->desc = "aCube Sam460ex";
mc->init = sam460ex_init;
+ mc->block_default_type = IF_IDE;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb");
mc->default_ram_size = 512 * MiB;
mc->default_ram_id = "ppc4xx.sdram";
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 55263f0..c417f9d 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -233,29 +233,40 @@
PowerPCCPU *cpu,
void *fdt, int offset)
{
+ /*
+ * SSO (SAO) ordering is supported on KVM and thread=single hosts,
+ * but not MTTCG, so disable it. To advertise it, a cap would have
+ * to be added, or support implemented for MTTCG.
+ *
+ * Copy/paste is not supported by TCG, so it is not advertised. KVM
+ * can execute them but it has no accelerator drivers which are usable,
+ * so there isn't much need for it anyway.
+ */
+
+ /* These should be kept in sync with pnv */
uint8_t pa_features_206[] = { 6, 0,
- 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
+ 0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 };
uint8_t pa_features_207[] = { 24, 0,
- 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
+ 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0,
0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
uint8_t pa_features_300[] = { 66, 0,
/* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
- /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
- 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
+ /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
+ 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
/* 6: DS207 */
0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
/* 16: Vector */
0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
- /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
+ /* 18: Vec. Scalar, 20: Vec. XOR */
0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
/* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
- /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
- 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
- /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
- 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
+ /* 32: LE atomic, 34: EBB + ext EBB */
+ 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
+ /* 40: Radix MMU */
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
/* 42: PM, 44: PC RA, 46: SC vec'd */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
/* 48: SIMD, 50: QP BFP, 52: String */
@@ -265,6 +276,36 @@
/* 60: NM atomic, 62: RNG */
0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
};
+ /* 3.1 removes SAO, HTM support */
+ uint8_t pa_features_31[] = { 74, 0,
+ /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
+ /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
+ 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
+ /* 6: DS207 */
+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
+ /* 16: Vector */
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
+ /* 18: Vec. Scalar, 20: Vec. XOR */
+ 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
+ /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
+ /* 32: LE atomic, 34: EBB + ext EBB */
+ 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
+ /* 40: Radix MMU */
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
+ /* 42: PM, 44: PC RA, 46: SC vec'd */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
+ /* 48: SIMD, 50: QP BFP, 52: String */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
+ /* 54: DecFP, 56: DecI, 58: SHA */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
+ /* 60: NM atomic, 62: RNG */
+ 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
+ /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */
+ 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
+ /* 72: [P]HASHST/[P]HASHCHK */
+ 0x80, 0x00, /* 72 - 73 */
+ };
uint8_t *pa_features = NULL;
size_t pa_size;
@@ -280,6 +321,10 @@
pa_features = pa_features_300;
pa_size = sizeof(pa_features_300);
}
+ if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0, cpu->compat_pvr)) {
+ pa_features = pa_features_31;
+ pa_size = sizeof(pa_features_31);
+ }
if (!pa_features) {
return;
}
@@ -1362,7 +1407,6 @@
}
}
-
static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
target_ulong lpid, ppc_v3_pate_t *entry)
{
@@ -1375,33 +1419,16 @@
/* Copy PATE1:GR into PATE0:HR */
entry->dw0 = spapr->patb_entry & PATE0_HR;
entry->dw1 = spapr->patb_entry;
-
+ return true;
} else {
- uint64_t patb, pats;
-
- assert(lpid != 0);
-
- patb = spapr->nested_ptcr & PTCR_PATB;
- pats = spapr->nested_ptcr & PTCR_PATS;
-
- /* Check if partition table is properly aligned */
- if (patb & MAKE_64BIT_MASK(0, pats + 12)) {
- return false;
+ if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) {
+ return spapr_get_pate_nested_hv(spapr, cpu, lpid, entry);
+ } else if (spapr_nested_api(spapr) == NESTED_API_PAPR) {
+ return spapr_get_pate_nested_papr(spapr, cpu, lpid, entry);
+ } else {
+ g_assert_not_reached();
}
-
- /* Calculate number of entries */
- pats = 1ull << (pats + 12 - 4);
- if (pats <= lpid) {
- return false;
- }
-
- /* Grab entry */
- patb += 16 * lpid;
- entry->dw0 = ldq_phys(CPU(cpu)->as, patb);
- entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8);
}
-
- return true;
}
#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
@@ -1689,6 +1716,7 @@
pef_kvm_reset(machine->cgs, &error_fatal);
spapr_caps_apply(spapr);
+ spapr_nested_reset(spapr);
first_ppc_cpu = POWERPC_CPU(first_cpu);
if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
@@ -2138,6 +2166,7 @@
&vmstate_spapr_cap_fwnmi,
&vmstate_spapr_fwnmi,
&vmstate_spapr_cap_rpt_invalidate,
+ &vmstate_spapr_cap_nested_papr,
NULL
}
};
@@ -3481,8 +3510,7 @@
void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
{
SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
cpu_synchronize_state(cs);
/* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */
@@ -3979,7 +4007,6 @@
SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev));
CPUCore *cc = CPU_CORE(dev);
- CPUState *cs;
SpaprDrc *drc;
CPUArchId *core_slot;
int index;
@@ -4013,7 +4040,7 @@
}
}
- core_slot->cpu = OBJECT(dev);
+ core_slot->cpu = CPU(dev);
/*
* Set compatibility mode to match the boot CPU, which was either set
@@ -4029,7 +4056,7 @@
if (smc->pre_2_10_has_unused_icps) {
for (i = 0; i < cc->nr_threads; i++) {
- cs = CPU(core->threads[i]);
+ CPUState *cs = CPU(core->threads[i]);
pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
}
}
@@ -4704,6 +4731,7 @@
smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND;
smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */
smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF;
+ smc->default_caps.caps[SPAPR_CAP_NESTED_PAPR] = SPAPR_CAP_OFF;
smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON;
smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON;
smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON;
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index e889244..0a15415 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -194,8 +194,7 @@
static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
{
ERRP_GUARD();
- PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(first_cpu);
if (!val) {
/* TODO: We don't support disabling vsx yet */
@@ -213,14 +212,12 @@
static void cap_dfp_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
{
ERRP_GUARD();
- PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
- CPUPPCState *env = &cpu->env;
if (!val) {
/* TODO: We don't support disabling dfp yet */
return;
}
- if (!(env->insns_flags2 & PPC2_DFP)) {
+ if (!(cpu_env(first_cpu)->insns_flags2 & PPC2_DFP)) {
error_setg(errp, "DFP support not available");
error_append_hint(errp, "Try appending -machine cap-dfp=off\n");
}
@@ -487,6 +484,50 @@
error_append_hint(errp, "Try appending -machine cap-nested-hv=off "
"or use threads=1 with -smp\n");
}
+ if (spapr_nested_api(spapr) &&
+ spapr_nested_api(spapr) != NESTED_API_KVM_HV) {
+ error_setg(errp, "Nested-HV APIs are mutually exclusive");
+ error_append_hint(errp, "Please use either cap-nested-hv or "
+ "cap-nested-papr to proceed.\n");
+ return;
+ } else {
+ spapr->nested.api = NESTED_API_KVM_HV;
+ }
+ }
+}
+
+static void cap_nested_papr_apply(SpaprMachineState *spapr,
+ uint8_t val, Error **errp)
+{
+ ERRP_GUARD();
+ PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
+ CPUPPCState *env = &cpu->env;
+
+ if (!val) {
+ /* capability disabled by default */
+ return;
+ }
+
+ if (tcg_enabled()) {
+ if (!(env->insns_flags2 & PPC2_ISA300)) {
+ error_setg(errp, "Nested-PAPR only supported on POWER9 and later");
+ error_append_hint(errp,
+ "Try appending -machine cap-nested-papr=off\n");
+ return;
+ }
+ if (spapr_nested_api(spapr) &&
+ spapr_nested_api(spapr) != NESTED_API_PAPR) {
+ error_setg(errp, "Nested-HV APIs are mutually exclusive");
+ error_append_hint(errp, "Please use either cap-nested-hv or "
+ "cap-nested-papr to proceed.\n");
+ return;
+ } else {
+ spapr->nested.api = NESTED_API_PAPR;
+ }
+ } else if (kvm_enabled()) {
+ error_setg(errp, "KVM implementation does not support Nested-PAPR");
+ error_append_hint(errp,
+ "Try appending -machine cap-nested-papr=off\n");
}
}
@@ -735,6 +776,15 @@
.type = "bool",
.apply = cap_nested_kvm_hv_apply,
},
+ [SPAPR_CAP_NESTED_PAPR] = {
+ .name = "nested-papr",
+ .description = "Allow Nested HV (PAPR API)",
+ .index = SPAPR_CAP_NESTED_PAPR,
+ .get = spapr_cap_get_bool,
+ .set = spapr_cap_set_bool,
+ .type = "bool",
+ .apply = cap_nested_papr_apply,
+ },
[SPAPR_CAP_LARGE_DECREMENTER] = {
.name = "large-decr",
.description = "Allow Large Decrementer",
@@ -919,6 +969,7 @@
SPAPR_CAP_MIG_STATE(ibs, SPAPR_CAP_IBS);
SPAPR_CAP_MIG_STATE(hpt_maxpagesize, SPAPR_CAP_HPT_MAXPAGESIZE);
SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV);
+SPAPR_CAP_MIG_STATE(nested_papr, SPAPR_CAP_NESTED_PAPR);
SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER);
SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST);
SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI);
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 40b7c52..e7c9edd 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -39,9 +39,13 @@
/*
* "PowerPC Processor binding to IEEE 1275" defines the initial MSR state
- * as 32bit (MSR_SF=0) in "8.2.1. Initial Register Values".
+ * as 32bit (MSR_SF=0) with MSR_ME=1 and MSR_FP=1 in "8.2.1. Initial
+ * Register Values". This can also be found in "LoPAPR 1.1" "C.9.2.1
+ * Initial Register Values".
*/
env->msr &= ~(1ULL << MSR_SF);
+ env->msr |= (1ULL << MSR_ME) | (1ULL << MSR_FP);
+
env->spr[SPR_HIOR] = 0;
lpcr = env->spr[SPR_LPCR];
@@ -394,10 +398,8 @@
DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
- DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"),
- DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"),
DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
#ifdef CONFIG_KVM
DEFINE_SPAPR_CPU_CORE_TYPE("host"),
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 75c2d12..5e1d020 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1525,6 +1525,28 @@
*slot = fn;
}
+void spapr_unregister_hypercall(target_ulong opcode)
+{
+ spapr_hcall_fn *slot;
+
+ if (opcode <= MAX_HCALL_OPCODE) {
+ assert((opcode & 0x3) == 0);
+
+ slot = &papr_hypercall_table[opcode / 4];
+ } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) {
+ /* we only have SVM-related hcall numbers assigned in multiples of 4 */
+ assert((opcode & 0x3) == 0);
+
+ slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4];
+ } else {
+ assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX));
+
+ slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
+ }
+
+ *slot = NULL;
+}
+
target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
target_ulong *args)
{
@@ -1638,8 +1660,6 @@
spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support);
spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt);
-
- spapr_register_nested();
}
type_init(hypercall_register_types)
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
index 121aa96..936659b 100644
--- a/hw/ppc/spapr_nested.c
+++ b/hw/ppc/spapr_nested.c
@@ -6,8 +6,85 @@
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "hw/ppc/spapr_nested.h"
+#include "mmu-book3s-v3.h"
+#include "cpu-models.h"
+#include "qemu/log.h"
+
+void spapr_nested_reset(SpaprMachineState *spapr)
+{
+ if (spapr_get_cap(spapr, SPAPR_CAP_NESTED_KVM_HV)) {
+ spapr_unregister_nested_hv();
+ spapr_register_nested_hv();
+ } else if (spapr_get_cap(spapr, SPAPR_CAP_NESTED_PAPR)) {
+ spapr->nested.capabilities_set = false;
+ spapr_unregister_nested_papr();
+ spapr_register_nested_papr();
+ spapr_nested_gsb_init();
+ } else {
+ spapr->nested.api = 0;
+ }
+}
+
+uint8_t spapr_nested_api(SpaprMachineState *spapr)
+{
+ return spapr->nested.api;
+}
#ifdef CONFIG_TCG
+
+bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry)
+{
+ uint64_t patb, pats;
+
+ assert(lpid != 0);
+
+ patb = spapr->nested.ptcr & PTCR_PATB;
+ pats = spapr->nested.ptcr & PTCR_PATS;
+
+ /* Check if partition table is properly aligned */
+ if (patb & MAKE_64BIT_MASK(0, pats + 12)) {
+ return false;
+ }
+
+ /* Calculate number of entries */
+ pats = 1ull << (pats + 12 - 4);
+ if (pats <= lpid) {
+ return false;
+ }
+
+ /* Grab entry */
+ patb += 16 * lpid;
+ entry->dw0 = ldq_phys(CPU(cpu)->as, patb);
+ entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8);
+ return true;
+}
+
+static
+SpaprMachineStateNestedGuest *spapr_get_nested_guest(SpaprMachineState *spapr,
+ target_ulong guestid)
+{
+ SpaprMachineStateNestedGuest *guest;
+
+ guest = g_hash_table_lookup(spapr->nested.guests, GINT_TO_POINTER(guestid));
+ return guest;
+}
+
+bool spapr_get_pate_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry)
+{
+ SpaprMachineStateNestedGuest *guest;
+ assert(lpid != 0);
+ guest = spapr_get_nested_guest(spapr, lpid);
+ if (!guest) {
+ return false;
+ }
+
+ entry->dw0 = guest->parttbl[0];
+ entry->dw1 = guest->parttbl[1];
+ return true;
+}
+
#define PRTS_MASK 0x1f
static target_ulong h_set_ptbl(PowerPCCPU *cpu,
@@ -25,7 +102,7 @@
return H_PARAMETER;
}
- spapr->nested_ptcr = ptcr; /* Save new partition table */
+ spapr->nested.ptcr = ptcr; /* Save new partition table */
return H_SUCCESS;
}
@@ -59,6 +136,7 @@
static void nested_save_state(struct nested_ppc_state *save, PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
+ SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
memcpy(save->gpr, env->gpr, sizeof(save->gpr));
@@ -85,13 +163,79 @@
save->pidr = env->spr[SPR_BOOKS_PID];
save->ppr = env->spr[SPR_PPR];
- save->tb_offset = env->tb_env->tb_offset;
+ if (spapr_nested_api(spapr) == NESTED_API_PAPR) {
+ save->amor = env->spr[SPR_AMOR];
+ save->dawr0 = env->spr[SPR_DAWR0];
+ save->dawrx0 = env->spr[SPR_DAWRX0];
+ save->ciabr = env->spr[SPR_CIABR];
+ save->purr = env->spr[SPR_PURR];
+ save->spurr = env->spr[SPR_SPURR];
+ save->ic = env->spr[SPR_IC];
+ save->vtb = env->spr[SPR_VTB];
+ save->hdar = env->spr[SPR_HDAR];
+ save->hdsisr = env->spr[SPR_HDSISR];
+ save->heir = env->spr[SPR_HEIR];
+ save->asdr = env->spr[SPR_ASDR];
+ save->dawr1 = env->spr[SPR_DAWR1];
+ save->dawrx1 = env->spr[SPR_DAWRX1];
+ save->dexcr = env->spr[SPR_DEXCR];
+ save->hdexcr = env->spr[SPR_HDEXCR];
+ save->hashkeyr = env->spr[SPR_HASHKEYR];
+ save->hashpkeyr = env->spr[SPR_HASHPKEYR];
+ memcpy(save->vsr, env->vsr, sizeof(save->vsr));
+ save->ebbhr = env->spr[SPR_EBBHR];
+ save->tar = env->spr[SPR_TAR];
+ save->ebbrr = env->spr[SPR_EBBRR];
+ save->bescr = env->spr[SPR_BESCR];
+ save->iamr = env->spr[SPR_IAMR];
+ save->amr = env->spr[SPR_AMR];
+ save->uamor = env->spr[SPR_UAMOR];
+ save->dscr = env->spr[SPR_DSCR];
+ save->fscr = env->spr[SPR_FSCR];
+ save->pspb = env->spr[SPR_PSPB];
+ save->ctrl = env->spr[SPR_CTRL];
+ save->vrsave = env->spr[SPR_VRSAVE];
+ save->dar = env->spr[SPR_DAR];
+ save->dsisr = env->spr[SPR_DSISR];
+ save->pmc1 = env->spr[SPR_POWER_PMC1];
+ save->pmc2 = env->spr[SPR_POWER_PMC2];
+ save->pmc3 = env->spr[SPR_POWER_PMC3];
+ save->pmc4 = env->spr[SPR_POWER_PMC4];
+ save->pmc5 = env->spr[SPR_POWER_PMC5];
+ save->pmc6 = env->spr[SPR_POWER_PMC6];
+ save->mmcr0 = env->spr[SPR_POWER_MMCR0];
+ save->mmcr1 = env->spr[SPR_POWER_MMCR1];
+ save->mmcr2 = env->spr[SPR_POWER_MMCR2];
+ save->mmcra = env->spr[SPR_POWER_MMCRA];
+ save->sdar = env->spr[SPR_POWER_SDAR];
+ save->siar = env->spr[SPR_POWER_SIAR];
+ save->sier = env->spr[SPR_POWER_SIER];
+ save->vscr = ppc_get_vscr(env);
+ save->fpscr = env->fpscr;
+ } else if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) {
+ save->tb_offset = env->tb_env->tb_offset;
+ }
+}
+
+static void nested_post_load_state(CPUPPCState *env, CPUState *cs)
+{
+ /*
+ * compute hflags and possible interrupts.
+ */
+ hreg_compute_hflags(env);
+ ppc_maybe_interrupt(env);
+ /*
+ * Nested HV does not tag TLB entries between L1 and L2, so must
+ * flush on transition.
+ */
+ tlb_flush(cs);
+ env->reserve_addr = -1; /* Reset the reservation */
}
static void nested_load_state(PowerPCCPU *cpu, struct nested_ppc_state *load)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
+ SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
memcpy(env->gpr, load->gpr, sizeof(env->gpr));
@@ -118,20 +262,58 @@
env->spr[SPR_BOOKS_PID] = load->pidr;
env->spr[SPR_PPR] = load->ppr;
- env->tb_env->tb_offset = load->tb_offset;
-
- /*
- * MSR updated, compute hflags and possible interrupts.
- */
- hreg_compute_hflags(env);
- ppc_maybe_interrupt(env);
-
- /*
- * Nested HV does not tag TLB entries between L1 and L2, so must
- * flush on transition.
- */
- tlb_flush(cs);
- env->reserve_addr = -1; /* Reset the reservation */
+ if (spapr_nested_api(spapr) == NESTED_API_PAPR) {
+ env->spr[SPR_AMOR] = load->amor;
+ env->spr[SPR_DAWR0] = load->dawr0;
+ env->spr[SPR_DAWRX0] = load->dawrx0;
+ env->spr[SPR_CIABR] = load->ciabr;
+ env->spr[SPR_PURR] = load->purr;
+ env->spr[SPR_SPURR] = load->purr;
+ env->spr[SPR_IC] = load->ic;
+ env->spr[SPR_VTB] = load->vtb;
+ env->spr[SPR_HDAR] = load->hdar;
+ env->spr[SPR_HDSISR] = load->hdsisr;
+ env->spr[SPR_HEIR] = load->heir;
+ env->spr[SPR_ASDR] = load->asdr;
+ env->spr[SPR_DAWR1] = load->dawr1;
+ env->spr[SPR_DAWRX1] = load->dawrx1;
+ env->spr[SPR_DEXCR] = load->dexcr;
+ env->spr[SPR_HDEXCR] = load->hdexcr;
+ env->spr[SPR_HASHKEYR] = load->hashkeyr;
+ env->spr[SPR_HASHPKEYR] = load->hashpkeyr;
+ memcpy(env->vsr, load->vsr, sizeof(env->vsr));
+ env->spr[SPR_EBBHR] = load->ebbhr;
+ env->spr[SPR_TAR] = load->tar;
+ env->spr[SPR_EBBRR] = load->ebbrr;
+ env->spr[SPR_BESCR] = load->bescr;
+ env->spr[SPR_IAMR] = load->iamr;
+ env->spr[SPR_AMR] = load->amr;
+ env->spr[SPR_UAMOR] = load->uamor;
+ env->spr[SPR_DSCR] = load->dscr;
+ env->spr[SPR_FSCR] = load->fscr;
+ env->spr[SPR_PSPB] = load->pspb;
+ env->spr[SPR_CTRL] = load->ctrl;
+ env->spr[SPR_VRSAVE] = load->vrsave;
+ env->spr[SPR_DAR] = load->dar;
+ env->spr[SPR_DSISR] = load->dsisr;
+ env->spr[SPR_POWER_PMC1] = load->pmc1;
+ env->spr[SPR_POWER_PMC2] = load->pmc2;
+ env->spr[SPR_POWER_PMC3] = load->pmc3;
+ env->spr[SPR_POWER_PMC4] = load->pmc4;
+ env->spr[SPR_POWER_PMC5] = load->pmc5;
+ env->spr[SPR_POWER_PMC6] = load->pmc6;
+ env->spr[SPR_POWER_MMCR0] = load->mmcr0;
+ env->spr[SPR_POWER_MMCR1] = load->mmcr1;
+ env->spr[SPR_POWER_MMCR2] = load->mmcr2;
+ env->spr[SPR_POWER_MMCRA] = load->mmcra;
+ env->spr[SPR_POWER_SDAR] = load->sdar;
+ env->spr[SPR_POWER_SIAR] = load->siar;
+ env->spr[SPR_POWER_SIER] = load->sier;
+ ppc_store_vscr(env, load->vscr);
+ ppc_store_fpscr(env, load->fpscr);
+ } else if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) {
+ env->tb_env->tb_offset = load->tb_offset;
+ }
}
/*
@@ -146,6 +328,7 @@
{
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
CPUPPCState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
struct nested_ppc_state l2_state;
target_ulong hv_ptr = args[0];
@@ -157,7 +340,7 @@
struct kvmppc_pt_regs *regs;
hwaddr len;
- if (spapr->nested_ptcr == 0) {
+ if (spapr->nested.ptcr == 0) {
return H_NOT_AVAILABLE;
}
@@ -244,6 +427,7 @@
* Switch to the nested guest environment and start the "hdec" timer.
*/
nested_load_state(cpu, &l2_state);
+ nested_post_load_state(env, cs);
hdec = hv_state.hdec_expiry - now;
cpu_ppc_hdecr_init(env);
@@ -272,9 +456,10 @@
return env->gpr[3];
}
-void spapr_exit_nested(PowerPCCPU *cpu, int excp)
+static void spapr_exit_nested_hv(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
struct nested_ppc_state l2_state;
target_ulong hv_ptr = spapr_cpu->nested_host_state->gpr[4];
@@ -284,8 +469,6 @@
struct kvmppc_pt_regs *regs;
hwaddr len;
- assert(spapr_cpu->in_nested);
-
nested_save_state(&l2_state, cpu);
hsrr0 = env->spr[SPR_HSRR0];
hsrr1 = env->spr[SPR_HSRR1];
@@ -298,6 +481,7 @@
*/
assert(env->spr[SPR_LPIDR] != 0);
nested_load_state(cpu, spapr_cpu->nested_host_state);
+ nested_post_load_state(env, cs);
env->gpr[3] = env->excp_vectors[excp]; /* hcall return value */
cpu_ppc_hdecr_exit(env);
@@ -375,21 +559,1347 @@
address_space_unmap(CPU(cpu)->as, regs, len, len, true);
}
-void spapr_register_nested(void)
+static bool spapr_nested_vcpu_check(SpaprMachineStateNestedGuest *guest,
+ target_ulong vcpuid, bool inoutbuf)
+{
+ struct SpaprMachineStateNestedGuestVcpu *vcpu;
+ /*
+ * Perform sanity checks for the provided vcpuid of a guest.
+ * For now, ensure its valid, allocated and enabled for use.
+ */
+
+ if (vcpuid >= PAPR_NESTED_GUEST_VCPU_MAX) {
+ return false;
+ }
+
+ if (!(vcpuid < guest->nr_vcpus)) {
+ return false;
+ }
+
+ vcpu = &guest->vcpus[vcpuid];
+ if (!vcpu->enabled) {
+ return false;
+ }
+
+ if (!inoutbuf) {
+ return true;
+ }
+
+ /* Check to see if the in/out buffers are registered */
+ if (vcpu->runbufin.addr && vcpu->runbufout.addr) {
+ return true;
+ }
+
+ return false;
+}
+
+static void *get_vcpu_state_ptr(SpaprMachineStateNestedGuest *guest,
+ target_ulong vcpuid)
+{
+ assert(spapr_nested_vcpu_check(guest, vcpuid, false));
+ return &guest->vcpus[vcpuid].state;
+}
+
+static void *get_vcpu_ptr(SpaprMachineStateNestedGuest *guest,
+ target_ulong vcpuid)
+{
+ assert(spapr_nested_vcpu_check(guest, vcpuid, false));
+ return &guest->vcpus[vcpuid];
+}
+
+static void *get_guest_ptr(SpaprMachineStateNestedGuest *guest,
+ target_ulong vcpuid)
+{
+ return guest; /* for GSBE_NESTED */
+}
+
+/*
+ * set=1 means the L1 is trying to set some state
+ * set=0 means the L1 is trying to get some state
+ */
+static void copy_state_8to8(void *a, void *b, bool set)
+{
+ /* set takes from the Big endian element_buf and sets internal buffer */
+
+ if (set) {
+ *(uint64_t *)a = be64_to_cpu(*(uint64_t *)b);
+ } else {
+ *(uint64_t *)b = cpu_to_be64(*(uint64_t *)a);
+ }
+}
+
+static void copy_state_4to4(void *a, void *b, bool set)
+{
+ if (set) {
+ *(uint32_t *)a = be32_to_cpu(*(uint32_t *)b);
+ } else {
+ *(uint32_t *)b = cpu_to_be32(*((uint32_t *)a));
+ }
+}
+
+static void copy_state_16to16(void *a, void *b, bool set)
+{
+ uint64_t *src, *dst;
+
+ if (set) {
+ src = b;
+ dst = a;
+
+ dst[1] = be64_to_cpu(src[0]);
+ dst[0] = be64_to_cpu(src[1]);
+ } else {
+ src = a;
+ dst = b;
+
+ dst[1] = cpu_to_be64(src[0]);
+ dst[0] = cpu_to_be64(src[1]);
+ }
+}
+
+static void copy_state_4to8(void *a, void *b, bool set)
+{
+ if (set) {
+ *(uint64_t *)a = (uint64_t) be32_to_cpu(*(uint32_t *)b);
+ } else {
+ *(uint32_t *)b = cpu_to_be32((uint32_t) (*((uint64_t *)a)));
+ }
+}
+
+static void copy_state_pagetbl(void *a, void *b, bool set)
+{
+ uint64_t *pagetbl;
+ uint64_t *buf; /* 3 double words */
+ uint64_t rts;
+
+ assert(set);
+
+ pagetbl = a;
+ buf = b;
+
+ *pagetbl = be64_to_cpu(buf[0]);
+ /* as per ISA section 6.7.6.1 */
+ *pagetbl |= PATE0_HR; /* Host Radix bit is 1 */
+
+ /* RTS */
+ rts = be64_to_cpu(buf[1]);
+ assert(rts == 52);
+ rts = rts - 31; /* since radix tree size = 2^(RTS+31) */
+ *pagetbl |= ((rts & 0x7) << 5); /* RTS2 is bit 56:58 */
+ *pagetbl |= (((rts >> 3) & 0x3) << 61); /* RTS1 is bit 1:2 */
+
+ /* RPDS {Size = 2^(RPDS+3) , RPDS >=5} */
+ *pagetbl |= 63 - clz64(be64_to_cpu(buf[2])) - 3;
+}
+
+static void copy_state_proctbl(void *a, void *b, bool set)
+{
+ uint64_t *proctbl;
+ uint64_t *buf; /* 2 double words */
+
+ assert(set);
+
+ proctbl = a;
+ buf = b;
+ /* PRTB: Process Table Base */
+ *proctbl = be64_to_cpu(buf[0]);
+ /* PRTS: Process Table Size = 2^(12+PRTS) */
+ if (be64_to_cpu(buf[1]) == (1ULL << 12)) {
+ *proctbl |= 0;
+ } else if (be64_to_cpu(buf[1]) == (1ULL << 24)) {
+ *proctbl |= 12;
+ } else {
+ g_assert_not_reached();
+ }
+}
+
+static void copy_state_runbuf(void *a, void *b, bool set)
+{
+ uint64_t *buf; /* 2 double words */
+ struct SpaprMachineStateNestedGuestVcpuRunBuf *runbuf;
+
+ assert(set);
+
+ runbuf = a;
+ buf = b;
+
+ runbuf->addr = be64_to_cpu(buf[0]);
+ assert(runbuf->addr);
+
+ /* per spec */
+ assert(be64_to_cpu(buf[1]) <= 16384);
+
+ /*
+ * This will also hit in the input buffer but should be fine for
+ * now. If not we can split this function.
+ */
+ assert(be64_to_cpu(buf[1]) >= VCPU_OUT_BUF_MIN_SZ);
+
+ runbuf->size = be64_to_cpu(buf[1]);
+}
+
+/* tell the L1 how big we want the output vcpu run buffer */
+static void out_buf_min_size(void *a, void *b, bool set)
+{
+ uint64_t *buf; /* 1 double word */
+
+ assert(!set);
+
+ buf = b;
+
+ buf[0] = cpu_to_be64(VCPU_OUT_BUF_MIN_SZ);
+}
+
+static void copy_logical_pvr(void *a, void *b, bool set)
+{
+ SpaprMachineStateNestedGuest *guest;
+ uint32_t *buf; /* 1 word */
+ uint32_t *pvr_logical_ptr;
+ uint32_t pvr_logical;
+ target_ulong pcr = 0;
+
+ pvr_logical_ptr = a;
+ buf = b;
+
+ if (!set) {
+ buf[0] = cpu_to_be32(*pvr_logical_ptr);
+ return;
+ }
+
+ pvr_logical = be32_to_cpu(buf[0]);
+
+ *pvr_logical_ptr = pvr_logical;
+
+ if (*pvr_logical_ptr) {
+ switch (*pvr_logical_ptr) {
+ case CPU_POWERPC_LOGICAL_3_10:
+ pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00;
+ break;
+ case CPU_POWERPC_LOGICAL_3_00:
+ pcr = PCR_COMPAT_3_00;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Could not set PCR for LPVR=0x%08x\n",
+ *pvr_logical_ptr);
+ return;
+ }
+ }
+
+ guest = container_of(pvr_logical_ptr,
+ struct SpaprMachineStateNestedGuest,
+ pvr_logical);
+ for (int i = 0; i < guest->nr_vcpus; i++) {
+ guest->vcpus[i].state.pcr = ~pcr | HVMASK_PCR;
+ }
+}
+
+static void copy_tb_offset(void *a, void *b, bool set)
+{
+ SpaprMachineStateNestedGuest *guest;
+ uint64_t *buf; /* 1 double word */
+ uint64_t *tb_offset_ptr;
+ uint64_t tb_offset;
+
+ tb_offset_ptr = a;
+ buf = b;
+
+ if (!set) {
+ buf[0] = cpu_to_be64(*tb_offset_ptr);
+ return;
+ }
+
+ tb_offset = be64_to_cpu(buf[0]);
+ /* need to copy this to the individual tb_offset for each vcpu */
+ guest = container_of(tb_offset_ptr,
+ struct SpaprMachineStateNestedGuest,
+ tb_offset);
+ for (int i = 0; i < guest->nr_vcpus; i++) {
+ guest->vcpus[i].tb_offset = tb_offset;
+ }
+}
+
+static void copy_state_hdecr(void *a, void *b, bool set)
+{
+ uint64_t *buf; /* 1 double word */
+ uint64_t *hdecr_expiry_tb;
+
+ hdecr_expiry_tb = a;
+ buf = b;
+
+ if (!set) {
+ buf[0] = cpu_to_be64(*hdecr_expiry_tb);
+ return;
+ }
+
+ *hdecr_expiry_tb = be64_to_cpu(buf[0]);
+}
+
+struct guest_state_element_type guest_state_element_types[] = {
+ GUEST_STATE_ELEMENT_NOP(GSB_HV_VCPU_IGNORED_ID, 0),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR0, gpr[0]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR1, gpr[1]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR2, gpr[2]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR3, gpr[3]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR4, gpr[4]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR5, gpr[5]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR6, gpr[6]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR7, gpr[7]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR8, gpr[8]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR9, gpr[9]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR10, gpr[10]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR11, gpr[11]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR12, gpr[12]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR13, gpr[13]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR14, gpr[14]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR15, gpr[15]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR16, gpr[16]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR17, gpr[17]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR18, gpr[18]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR19, gpr[19]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR20, gpr[20]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR21, gpr[21]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR22, gpr[22]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR23, gpr[23]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR24, gpr[24]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR25, gpr[25]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR26, gpr[26]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR27, gpr[27]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR28, gpr[28]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR29, gpr[29]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR30, gpr[30]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR31, gpr[31]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_NIA, nip),
+ GSE_ENV_DWM(GSB_VCPU_SPR_MSR, msr, HVMASK_MSR),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CTR, ctr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_LR, lr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_XER, xer),
+ GUEST_STATE_ELEMENT_ENV_WW(GSB_VCPU_SPR_CR, cr),
+ GUEST_STATE_ELEMENT_NOP_DW(GSB_VCPU_SPR_MMCR3),
+ GUEST_STATE_ELEMENT_NOP_DW(GSB_VCPU_SPR_SIER2),
+ GUEST_STATE_ELEMENT_NOP_DW(GSB_VCPU_SPR_SIER3),
+ GUEST_STATE_ELEMENT_NOP_W(GSB_VCPU_SPR_WORT),
+ GSE_ENV_DWM(GSB_VCPU_SPR_LPCR, lpcr, HVMASK_LPCR),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_AMOR, amor),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HFSCR, hfscr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAWR0, dawr0),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DAWRX0, dawrx0),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CIABR, ciabr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_PURR, purr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPURR, spurr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_IC, ic),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_VTB, vtb),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HDAR, hdar),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_HDSISR, hdsisr),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_HEIR, heir),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_ASDR, asdr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SRR0, srr0),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SRR1, srr1),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG0, sprg0),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG1, sprg1),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG2, sprg2),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG3, sprg3),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PIDR, pidr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CFAR, cfar),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_PPR, ppr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAWR1, dawr1),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DAWRX1, dawrx1),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DEXCR, dexcr),
+ GSE_ENV_DWM(GSB_VCPU_SPR_HDEXCR, hdexcr, HVMASK_HDEXCR),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HASHKEYR, hashkeyr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HASHPKEYR, hashpkeyr),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR0, vsr[0]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR1, vsr[1]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR2, vsr[2]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR3, vsr[3]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR4, vsr[4]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR5, vsr[5]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR6, vsr[6]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR7, vsr[7]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR8, vsr[8]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR9, vsr[9]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR10, vsr[10]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR11, vsr[11]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR12, vsr[12]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR13, vsr[13]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR14, vsr[14]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR15, vsr[15]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR16, vsr[16]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR17, vsr[17]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR18, vsr[18]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR19, vsr[19]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR20, vsr[20]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR21, vsr[21]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR22, vsr[22]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR23, vsr[23]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR24, vsr[24]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR25, vsr[25]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR26, vsr[26]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR27, vsr[27]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR28, vsr[28]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR29, vsr[29]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR30, vsr[30]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR31, vsr[31]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR32, vsr[32]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR33, vsr[33]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR34, vsr[34]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR35, vsr[35]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR36, vsr[36]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR37, vsr[37]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR38, vsr[38]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR39, vsr[39]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR40, vsr[40]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR41, vsr[41]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR42, vsr[42]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR43, vsr[43]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR44, vsr[44]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR45, vsr[45]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR46, vsr[46]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR47, vsr[47]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR48, vsr[48]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR49, vsr[49]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR50, vsr[50]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR51, vsr[51]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR52, vsr[52]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR53, vsr[53]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR54, vsr[54]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR55, vsr[55]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR56, vsr[56]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR57, vsr[57]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR58, vsr[58]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR59, vsr[59]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR60, vsr[60]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR61, vsr[61]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR62, vsr[62]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR63, vsr[63]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_EBBHR, ebbhr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_TAR, tar),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_EBBRR, ebbrr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_BESCR, bescr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_IAMR, iamr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_AMR, amr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_UAMOR, uamor),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DSCR, dscr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_FSCR, fscr),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PSPB, pspb),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CTRL, ctrl),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_VRSAVE, vrsave),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAR, dar),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DSISR, dsisr),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC1, pmc1),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC2, pmc2),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC3, pmc3),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC4, pmc4),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC5, pmc5),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC6, pmc6),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCR0, mmcr0),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCR1, mmcr1),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCR2, mmcr2),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCRA, mmcra),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SDAR , sdar),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SIAR , siar),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SIER , sier),
+ GUEST_STATE_ELEMENT_ENV_WW(GSB_VCPU_SPR_VSCR, vscr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_FPSCR, fpscr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_DEC_EXPIRE_TB, dec_expiry_tb),
+ GSBE_NESTED(GSB_PART_SCOPED_PAGETBL, 0x18, parttbl[0], copy_state_pagetbl),
+ GSBE_NESTED(GSB_PROCESS_TBL, 0x10, parttbl[1], copy_state_proctbl),
+ GSBE_NESTED(GSB_VCPU_LPVR, 0x4, pvr_logical, copy_logical_pvr),
+ GSBE_NESTED_MSK(GSB_TB_OFFSET, 0x8, tb_offset, copy_tb_offset,
+ HVMASK_TB_OFFSET),
+ GSBE_NESTED_VCPU(GSB_VCPU_IN_BUFFER, 0x10, runbufin, copy_state_runbuf),
+ GSBE_NESTED_VCPU(GSB_VCPU_OUT_BUFFER, 0x10, runbufout, copy_state_runbuf),
+ GSBE_NESTED_VCPU(GSB_VCPU_OUT_BUF_MIN_SZ, 0x8, runbufout, out_buf_min_size),
+ GSBE_NESTED_VCPU(GSB_VCPU_HDEC_EXPIRY_TB, 0x8, hdecr_expiry_tb,
+ copy_state_hdecr)
+};
+
+void spapr_nested_gsb_init(void)
+{
+ struct guest_state_element_type *type;
+
+ /* Init the guest state elements lookup table, flags for now */
+ for (int i = 0; i < ARRAY_SIZE(guest_state_element_types); i++) {
+ type = &guest_state_element_types[i];
+
+ assert(type->id <= GSB_LAST);
+ if (type->id >= GSB_VCPU_SPR_HDAR)
+ /* 0xf000 - 0xf005 Thread + RO */
+ type->flags = GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY;
+ else if (type->id >= GSB_VCPU_IN_BUFFER)
+ /* 0x0c00 - 0xf000 Thread + RW */
+ type->flags = 0;
+ else if (type->id >= GSB_VCPU_LPVR)
+ /* 0x0003 - 0x0bff Guest + RW */
+ type->flags = GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE;
+ else if (type->id >= GSB_HV_VCPU_STATE_SIZE)
+ /* 0x0001 - 0x0002 Guest + RO */
+ type->flags = GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY |
+ GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE;
+ }
+}
+
+static struct guest_state_element *guest_state_element_next(
+ struct guest_state_element *element,
+ int64_t *len,
+ int64_t *num_elements)
+{
+ uint16_t size;
+
+ /* size is of element->value[] only. Not whole guest_state_element */
+ size = be16_to_cpu(element->size);
+
+ if (len) {
+ *len -= size + offsetof(struct guest_state_element, value);
+ }
+
+ if (num_elements) {
+ *num_elements -= 1;
+ }
+
+ return (struct guest_state_element *)(element->value + size);
+}
+
+static
+struct guest_state_element_type *guest_state_element_type_find(uint16_t id)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(guest_state_element_types); i++)
+ if (id == guest_state_element_types[i].id) {
+ return &guest_state_element_types[i];
+ }
+
+ return NULL;
+}
+
+static void log_element(struct guest_state_element *element,
+ struct guest_state_request *gsr)
+{
+ qemu_log_mask(LOG_GUEST_ERROR, "h_guest_%s_state id:0x%04x size:0x%04x",
+ gsr->flags & GUEST_STATE_REQUEST_SET ? "set" : "get",
+ be16_to_cpu(element->id), be16_to_cpu(element->size));
+ qemu_log_mask(LOG_GUEST_ERROR, "buf:0x%016"PRIx64" ...\n",
+ be64_to_cpu(*(uint64_t *)element->value));
+}
+
+static bool guest_state_request_check(struct guest_state_request *gsr)
+{
+ int64_t num_elements, len = gsr->len;
+ struct guest_state_buffer *gsb = gsr->gsb;
+ struct guest_state_element *element;
+ struct guest_state_element_type *type;
+ uint16_t id, size;
+
+ /* gsb->num_elements = 0 == 32 bits long */
+ assert(len >= 4);
+
+ num_elements = be32_to_cpu(gsb->num_elements);
+ element = gsb->elements;
+ len -= sizeof(gsb->num_elements);
+
+ /* Walk the buffer to validate the length */
+ while (num_elements) {
+
+ id = be16_to_cpu(element->id);
+ size = be16_to_cpu(element->size);
+
+ if (false) {
+ log_element(element, gsr);
+ }
+ /* buffer size too small */
+ if (len < 0) {
+ return false;
+ }
+
+ type = guest_state_element_type_find(id);
+ if (!type) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Element ID %04x unknown\n", id);
+ log_element(element, gsr);
+ return false;
+ }
+
+ if (id == GSB_HV_VCPU_IGNORED_ID) {
+ goto next_element;
+ }
+
+ if (size != type->size) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Size mismatch. Element ID:%04x."
+ "Size Exp:%i Got:%i\n", id, type->size, size);
+ log_element(element, gsr);
+ return false;
+ }
+
+ if ((type->flags & GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY) &&
+ (gsr->flags & GUEST_STATE_REQUEST_SET)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Trying to set a read-only Element "
+ "ID:%04x.\n", id);
+ return false;
+ }
+
+ if (type->flags & GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE) {
+ /* guest wide element type */
+ if (!(gsr->flags & GUEST_STATE_REQUEST_GUEST_WIDE)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "trying to set a guest wide "
+ "Element ID:%04x.\n", id);
+ return false;
+ }
+ } else {
+ /* thread wide element type */
+ if (gsr->flags & GUEST_STATE_REQUEST_GUEST_WIDE) {
+ qemu_log_mask(LOG_GUEST_ERROR, "trying to set a thread wide "
+ "Element ID:%04x.\n", id);
+ return false;
+ }
+ }
+next_element:
+ element = guest_state_element_next(element, &len, &num_elements);
+
+ }
+ return true;
+}
+
+static bool is_gsr_invalid(struct guest_state_request *gsr,
+ struct guest_state_element *element,
+ struct guest_state_element_type *type)
+{
+ if ((gsr->flags & GUEST_STATE_REQUEST_SET) &&
+ (*(uint64_t *)(element->value) & ~(type->mask))) {
+ log_element(element, gsr);
+ qemu_log_mask(LOG_GUEST_ERROR, "L1 can't set reserved bits "
+ "(allowed mask: 0x%08"PRIx64")\n", type->mask);
+ return true;
+ }
+ return false;
+}
+
+static target_ulong h_guest_get_capabilities(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ CPUPPCState *env = &cpu->env;
+ target_ulong flags = args[0];
+
+ if (flags) { /* don't handle any flags capabilities for now */
+ return H_PARAMETER;
+ }
+
+ /* P10 capabilities */
+ if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0,
+ spapr->max_compat_pvr)) {
+ env->gpr[4] |= H_GUEST_CAPABILITIES_P10_MODE;
+ }
+
+ /* P9 capabilities */
+ if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0,
+ spapr->max_compat_pvr)) {
+ env->gpr[4] |= H_GUEST_CAPABILITIES_P9_MODE;
+ }
+
+ return H_SUCCESS;
+}
+
+static target_ulong h_guest_set_capabilities(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ CPUPPCState *env = &cpu->env;
+ target_ulong flags = args[0];
+ target_ulong capabilities = args[1];
+ env->gpr[4] = 0;
+
+ if (flags) { /* don't handle any flags capabilities for now */
+ return H_PARAMETER;
+ }
+
+ if (capabilities & H_GUEST_CAPABILITIES_COPY_MEM) {
+ env->gpr[4] = 1;
+ return H_P2; /* isn't supported */
+ }
+
+ /*
+ * If there are no capabilities configured, set the R5 to the index of
+ * the first supported Power Processor Mode
+ */
+ if (!capabilities) {
+ env->gpr[4] = 1;
+
+ /* set R5 to the first supported Power Processor Mode */
+ if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0,
+ spapr->max_compat_pvr)) {
+ env->gpr[5] = H_GUEST_CAP_P10_MODE_BMAP;
+ } else if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0,
+ spapr->max_compat_pvr)) {
+ env->gpr[5] = H_GUEST_CAP_P9_MODE_BMAP;
+ }
+
+ return H_P2;
+ }
+
+ /*
+ * If an invalid capability is set, R5 should contain the index of the
+ * invalid capability bit
+ */
+ if (capabilities & ~H_GUEST_CAP_VALID_MASK) {
+ env->gpr[4] = 1;
+
+ /* Set R5 to the index of the invalid capability */
+ env->gpr[5] = 63 - ctz64(capabilities);
+
+ return H_P2;
+ }
+
+ if (!spapr->nested.capabilities_set) {
+ spapr->nested.capabilities_set = true;
+ spapr->nested.pvr_base = env->spr[SPR_PVR];
+ return H_SUCCESS;
+ } else {
+ return H_STATE;
+ }
+}
+
+static void
+destroy_guest_helper(gpointer value)
+{
+ struct SpaprMachineStateNestedGuest *guest = value;
+ g_free(guest->vcpus);
+ g_free(guest);
+}
+
+static target_ulong h_guest_create(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ CPUPPCState *env = &cpu->env;
+ target_ulong flags = args[0];
+ target_ulong continue_token = args[1];
+ uint64_t guestid;
+ int nguests = 0;
+ struct SpaprMachineStateNestedGuest *guest;
+
+ if (flags) { /* don't handle any flags for now */
+ return H_UNSUPPORTED_FLAG;
+ }
+
+ if (continue_token != -1) {
+ return H_P2;
+ }
+
+ if (!spapr->nested.capabilities_set) {
+ return H_STATE;
+ }
+
+ if (!spapr->nested.guests) {
+ spapr->nested.guests = g_hash_table_new_full(NULL,
+ NULL,
+ NULL,
+ destroy_guest_helper);
+ }
+
+ nguests = g_hash_table_size(spapr->nested.guests);
+
+ if (nguests == PAPR_NESTED_GUEST_MAX) {
+ return H_NO_MEM;
+ }
+
+ /* Lookup for available guestid */
+ for (guestid = 1; guestid < PAPR_NESTED_GUEST_MAX; guestid++) {
+ if (!(g_hash_table_lookup(spapr->nested.guests,
+ GINT_TO_POINTER(guestid)))) {
+ break;
+ }
+ }
+
+ if (guestid == PAPR_NESTED_GUEST_MAX) {
+ return H_NO_MEM;
+ }
+
+ guest = g_try_new0(struct SpaprMachineStateNestedGuest, 1);
+ if (!guest) {
+ return H_NO_MEM;
+ }
+
+ guest->pvr_logical = spapr->nested.pvr_base;
+ g_hash_table_insert(spapr->nested.guests, GINT_TO_POINTER(guestid), guest);
+ env->gpr[4] = guestid;
+
+ return H_SUCCESS;
+}
+
+static target_ulong h_guest_delete(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ target_ulong flags = args[0];
+ target_ulong guestid = args[1];
+ struct SpaprMachineStateNestedGuest *guest;
+
+ /*
+ * handle flag deleteAllGuests, if set:
+ * guestid is ignored and all guests are deleted
+ *
+ */
+ if (flags & ~H_GUEST_DELETE_ALL_FLAG) {
+ return H_UNSUPPORTED_FLAG; /* other flag bits reserved */
+ } else if (flags & H_GUEST_DELETE_ALL_FLAG) {
+ g_hash_table_destroy(spapr->nested.guests);
+ return H_SUCCESS;
+ }
+
+ guest = g_hash_table_lookup(spapr->nested.guests, GINT_TO_POINTER(guestid));
+ if (!guest) {
+ return H_P2;
+ }
+
+ g_hash_table_remove(spapr->nested.guests, GINT_TO_POINTER(guestid));
+
+ return H_SUCCESS;
+}
+
+static target_ulong h_guest_create_vcpu(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ target_ulong flags = args[0];
+ target_ulong guestid = args[1];
+ target_ulong vcpuid = args[2];
+ SpaprMachineStateNestedGuest *guest;
+
+ if (flags) { /* don't handle any flags for now */
+ return H_UNSUPPORTED_FLAG;
+ }
+
+ guest = spapr_get_nested_guest(spapr, guestid);
+ if (!guest) {
+ return H_P2;
+ }
+
+ if (vcpuid < guest->nr_vcpus) {
+ qemu_log_mask(LOG_UNIMP, "vcpuid " TARGET_FMT_ld " already in use.",
+ vcpuid);
+ return H_IN_USE;
+ }
+ /* linear vcpuid allocation only */
+ assert(vcpuid == guest->nr_vcpus);
+
+ if (guest->nr_vcpus >= PAPR_NESTED_GUEST_VCPU_MAX) {
+ return H_P3;
+ }
+
+ SpaprMachineStateNestedGuestVcpu *vcpus, *curr_vcpu;
+ vcpus = g_try_renew(struct SpaprMachineStateNestedGuestVcpu,
+ guest->vcpus,
+ guest->nr_vcpus + 1);
+ if (!vcpus) {
+ return H_NO_MEM;
+ }
+ guest->vcpus = vcpus;
+ curr_vcpu = &vcpus[guest->nr_vcpus];
+ memset(curr_vcpu, 0, sizeof(SpaprMachineStateNestedGuestVcpu));
+
+ curr_vcpu->enabled = true;
+ guest->nr_vcpus++;
+
+ return H_SUCCESS;
+}
+
+static target_ulong getset_state(SpaprMachineStateNestedGuest *guest,
+ uint64_t vcpuid,
+ struct guest_state_request *gsr)
+{
+ void *ptr;
+ uint16_t id;
+ struct guest_state_element *element;
+ struct guest_state_element_type *type;
+ int64_t lenleft, num_elements;
+
+ lenleft = gsr->len;
+
+ if (!guest_state_request_check(gsr)) {
+ return H_P3;
+ }
+
+ num_elements = be32_to_cpu(gsr->gsb->num_elements);
+ element = gsr->gsb->elements;
+ /* Process the elements */
+ while (num_elements) {
+ type = NULL;
+ /* log_element(element, gsr); */
+
+ id = be16_to_cpu(element->id);
+ if (id == GSB_HV_VCPU_IGNORED_ID) {
+ goto next_element;
+ }
+
+ type = guest_state_element_type_find(id);
+ assert(type);
+
+ /* Get pointer to guest data to get/set */
+ if (type->location && type->copy) {
+ ptr = type->location(guest, vcpuid);
+ assert(ptr);
+ if (!~(type->mask) && is_gsr_invalid(gsr, element, type)) {
+ return H_INVALID_ELEMENT_VALUE;
+ }
+ type->copy(ptr + type->offset, element->value,
+ gsr->flags & GUEST_STATE_REQUEST_SET ? true : false);
+ }
+
+next_element:
+ element = guest_state_element_next(element, &lenleft, &num_elements);
+ }
+
+ return H_SUCCESS;
+}
+
+static target_ulong map_and_getset_state(PowerPCCPU *cpu,
+ SpaprMachineStateNestedGuest *guest,
+ uint64_t vcpuid,
+ struct guest_state_request *gsr)
+{
+ target_ulong rc;
+ int64_t len;
+ bool is_write;
+
+ len = gsr->len;
+ /* only get_state would require write access to the provided buffer */
+ is_write = (gsr->flags & GUEST_STATE_REQUEST_SET) ? false : true;
+ gsr->gsb = address_space_map(CPU(cpu)->as, gsr->buf, (uint64_t *)&len,
+ is_write, MEMTXATTRS_UNSPECIFIED);
+ if (!gsr->gsb) {
+ rc = H_P3;
+ goto out1;
+ }
+
+ if (len != gsr->len) {
+ rc = H_P3;
+ goto out1;
+ }
+
+ rc = getset_state(guest, vcpuid, gsr);
+
+out1:
+ address_space_unmap(CPU(cpu)->as, gsr->gsb, len, is_write, len);
+ return rc;
+}
+
+static target_ulong h_guest_getset_state(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong *args,
+ bool set)
+{
+ target_ulong flags = args[0];
+ target_ulong lpid = args[1];
+ target_ulong vcpuid = args[2];
+ target_ulong buf = args[3];
+ target_ulong buflen = args[4];
+ struct guest_state_request gsr;
+ SpaprMachineStateNestedGuest *guest;
+
+ guest = spapr_get_nested_guest(spapr, lpid);
+ if (!guest) {
+ return H_P2;
+ }
+ gsr.buf = buf;
+ assert(buflen <= GSB_MAX_BUF_SIZE);
+ gsr.len = buflen;
+ gsr.flags = 0;
+ if (flags & H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) {
+ gsr.flags |= GUEST_STATE_REQUEST_GUEST_WIDE;
+ }
+ if (flags & !H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) {
+ return H_PARAMETER; /* flag not supported yet */
+ }
+
+ if (set) {
+ gsr.flags |= GUEST_STATE_REQUEST_SET;
+ }
+ return map_and_getset_state(cpu, guest, vcpuid, &gsr);
+}
+
+static target_ulong h_guest_set_state(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ return h_guest_getset_state(cpu, spapr, args, true);
+}
+
+static target_ulong h_guest_get_state(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ return h_guest_getset_state(cpu, spapr, args, false);
+}
+
+static void exit_nested_store_l2(PowerPCCPU *cpu, int excp,
+ SpaprMachineStateNestedGuestVcpu *vcpu)
+{
+ CPUPPCState *env = &cpu->env;
+ SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
+ target_ulong now, hdar, hdsisr, asdr;
+
+ assert(sizeof(env->gpr) == sizeof(vcpu->state.gpr)); /* sanity check */
+
+ now = cpu_ppc_load_tbl(env); /* L2 timebase */
+ now -= vcpu->tb_offset; /* L1 timebase */
+ vcpu->state.dec_expiry_tb = now - cpu_ppc_load_decr(env);
+ cpu_ppc_store_decr(env, spapr_cpu->nested_host_state->dec_expiry_tb - now);
+ /* backup hdar, hdsisr, asdr if reqd later below */
+ hdar = vcpu->state.hdar;
+ hdsisr = vcpu->state.hdsisr;
+ asdr = vcpu->state.asdr;
+
+ nested_save_state(&vcpu->state, cpu);
+
+ if (excp == POWERPC_EXCP_MCHECK ||
+ excp == POWERPC_EXCP_RESET ||
+ excp == POWERPC_EXCP_SYSCALL) {
+ vcpu->state.nip = env->spr[SPR_SRR0];
+ vcpu->state.msr = env->spr[SPR_SRR1] & env->msr_mask;
+ } else {
+ vcpu->state.nip = env->spr[SPR_HSRR0];
+ vcpu->state.msr = env->spr[SPR_HSRR1] & env->msr_mask;
+ }
+
+ /* hdar, hdsisr, asdr should be retained unless certain exceptions */
+ if ((excp != POWERPC_EXCP_HDSI) && (excp != POWERPC_EXCP_HISI)) {
+ vcpu->state.asdr = asdr;
+ } else if (excp != POWERPC_EXCP_HDSI) {
+ vcpu->state.hdar = hdar;
+ vcpu->state.hdsisr = hdsisr;
+ }
+}
+
+static int get_exit_ids(uint64_t srr0, uint16_t ids[16])
+{
+ int nr;
+
+ switch (srr0) {
+ case 0xc00:
+ nr = 10;
+ ids[0] = GSB_VCPU_GPR3;
+ ids[1] = GSB_VCPU_GPR4;
+ ids[2] = GSB_VCPU_GPR5;
+ ids[3] = GSB_VCPU_GPR6;
+ ids[4] = GSB_VCPU_GPR7;
+ ids[5] = GSB_VCPU_GPR8;
+ ids[6] = GSB_VCPU_GPR9;
+ ids[7] = GSB_VCPU_GPR10;
+ ids[8] = GSB_VCPU_GPR11;
+ ids[9] = GSB_VCPU_GPR12;
+ break;
+ case 0xe00:
+ nr = 5;
+ ids[0] = GSB_VCPU_SPR_HDAR;
+ ids[1] = GSB_VCPU_SPR_HDSISR;
+ ids[2] = GSB_VCPU_SPR_ASDR;
+ ids[3] = GSB_VCPU_SPR_NIA;
+ ids[4] = GSB_VCPU_SPR_MSR;
+ break;
+ case 0xe20:
+ nr = 4;
+ ids[0] = GSB_VCPU_SPR_HDAR;
+ ids[1] = GSB_VCPU_SPR_ASDR;
+ ids[2] = GSB_VCPU_SPR_NIA;
+ ids[3] = GSB_VCPU_SPR_MSR;
+ break;
+ case 0xe40:
+ nr = 3;
+ ids[0] = GSB_VCPU_SPR_HEIR;
+ ids[1] = GSB_VCPU_SPR_NIA;
+ ids[2] = GSB_VCPU_SPR_MSR;
+ break;
+ case 0xf80:
+ nr = 3;
+ ids[0] = GSB_VCPU_SPR_HFSCR;
+ ids[1] = GSB_VCPU_SPR_NIA;
+ ids[2] = GSB_VCPU_SPR_MSR;
+ break;
+ default:
+ nr = 0;
+ break;
+ }
+
+ return nr;
+}
+
+static void exit_process_output_buffer(PowerPCCPU *cpu,
+ SpaprMachineStateNestedGuest *guest,
+ target_ulong vcpuid,
+ target_ulong *r3)
+{
+ SpaprMachineStateNestedGuestVcpu *vcpu = &guest->vcpus[vcpuid];
+ struct guest_state_request gsr;
+ struct guest_state_buffer *gsb;
+ struct guest_state_element *element;
+ struct guest_state_element_type *type;
+ int exit_id_count = 0;
+ uint16_t exit_cause_ids[16];
+ hwaddr len;
+
+ len = vcpu->runbufout.size;
+ gsb = address_space_map(CPU(cpu)->as, vcpu->runbufout.addr, &len, true,
+ MEMTXATTRS_UNSPECIFIED);
+ if (!gsb || len != vcpu->runbufout.size) {
+ address_space_unmap(CPU(cpu)->as, gsb, len, true, len);
+ *r3 = H_P2;
+ return;
+ }
+
+ exit_id_count = get_exit_ids(*r3, exit_cause_ids);
+
+ /* Create a buffer of elements to send back */
+ gsb->num_elements = cpu_to_be32(exit_id_count);
+ element = gsb->elements;
+ for (int i = 0; i < exit_id_count; i++) {
+ type = guest_state_element_type_find(exit_cause_ids[i]);
+ assert(type);
+ element->id = cpu_to_be16(exit_cause_ids[i]);
+ element->size = cpu_to_be16(type->size);
+ element = guest_state_element_next(element, NULL, NULL);
+ }
+ gsr.gsb = gsb;
+ gsr.len = VCPU_OUT_BUF_MIN_SZ;
+ gsr.flags = 0; /* get + never guest wide */
+ getset_state(guest, vcpuid, &gsr);
+
+ address_space_unmap(CPU(cpu)->as, gsb, len, true, len);
+ return;
+}
+
+static
+void spapr_exit_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu, int excp)
+{
+ CPUPPCState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
+ SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
+ target_ulong r3_return = env->excp_vectors[excp]; /* hcall return value */
+ target_ulong lpid = 0, vcpuid = 0;
+ struct SpaprMachineStateNestedGuestVcpu *vcpu = NULL;
+ struct SpaprMachineStateNestedGuest *guest = NULL;
+
+ lpid = spapr_cpu->nested_host_state->gpr[5];
+ vcpuid = spapr_cpu->nested_host_state->gpr[6];
+ guest = spapr_get_nested_guest(spapr, lpid);
+ assert(guest);
+ spapr_nested_vcpu_check(guest, vcpuid, false);
+ vcpu = &guest->vcpus[vcpuid];
+
+ exit_nested_store_l2(cpu, excp, vcpu);
+ /* do the output buffer for run_vcpu*/
+ exit_process_output_buffer(cpu, guest, vcpuid, &r3_return);
+
+ assert(env->spr[SPR_LPIDR] != 0);
+ nested_load_state(cpu, spapr_cpu->nested_host_state);
+ cpu_ppc_decrease_tb_by_offset(env, vcpu->tb_offset);
+ env->gpr[3] = H_SUCCESS;
+ env->gpr[4] = r3_return;
+ nested_post_load_state(env, cs);
+ cpu_ppc_hdecr_exit(env);
+
+ spapr_cpu->in_nested = false;
+ g_free(spapr_cpu->nested_host_state);
+ spapr_cpu->nested_host_state = NULL;
+}
+
+void spapr_exit_nested(PowerPCCPU *cpu, int excp)
+{
+ SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
+ SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
+
+ assert(spapr_cpu->in_nested);
+ if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) {
+ spapr_exit_nested_hv(cpu, excp);
+ } else if (spapr_nested_api(spapr) == NESTED_API_PAPR) {
+ spapr_exit_nested_papr(spapr, cpu, excp);
+ } else {
+ g_assert_not_reached();
+ }
+}
+
+static void nested_papr_load_l2(PowerPCCPU *cpu,
+ CPUPPCState *env,
+ SpaprMachineStateNestedGuestVcpu *vcpu,
+ target_ulong now)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ target_ulong lpcr, lpcr_mask, hdec;
+ lpcr_mask = LPCR_DPFD | LPCR_ILE | LPCR_AIL | LPCR_LD | LPCR_MER;
+
+ assert(vcpu);
+ assert(sizeof(env->gpr) == sizeof(vcpu->state.gpr));
+ nested_load_state(cpu, &vcpu->state);
+ lpcr = (env->spr[SPR_LPCR] & ~lpcr_mask) |
+ (vcpu->state.lpcr & lpcr_mask);
+ lpcr |= LPCR_HR | LPCR_UPRT | LPCR_GTSE | LPCR_HVICE | LPCR_HDICE;
+ lpcr &= ~LPCR_LPES0;
+ env->spr[SPR_LPCR] = lpcr & pcc->lpcr_mask;
+
+ hdec = vcpu->hdecr_expiry_tb - now;
+ cpu_ppc_store_decr(env, vcpu->state.dec_expiry_tb - now);
+ cpu_ppc_hdecr_init(env);
+ cpu_ppc_store_hdecr(env, hdec);
+
+ cpu_ppc_increase_tb_by_offset(env, vcpu->tb_offset);
+}
+
+static void nested_papr_run_vcpu(PowerPCCPU *cpu,
+ uint64_t lpid,
+ SpaprMachineStateNestedGuestVcpu *vcpu)
+{
+ SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
+ CPUPPCState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
+ SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
+ target_ulong now = cpu_ppc_load_tbl(env);
+
+ assert(env->spr[SPR_LPIDR] == 0);
+ assert(spapr->nested.api); /* ensure API version is initialized */
+ spapr_cpu->nested_host_state = g_try_new(struct nested_ppc_state, 1);
+ assert(spapr_cpu->nested_host_state);
+ nested_save_state(spapr_cpu->nested_host_state, cpu);
+ spapr_cpu->nested_host_state->dec_expiry_tb = now - cpu_ppc_load_decr(env);
+ nested_papr_load_l2(cpu, env, vcpu, now);
+ env->spr[SPR_LPIDR] = lpid; /* post load l2 */
+
+ spapr_cpu->in_nested = true;
+ nested_post_load_state(env, cs);
+}
+
+static target_ulong h_guest_run_vcpu(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ CPUPPCState *env = &cpu->env;
+ target_ulong flags = args[0];
+ target_ulong lpid = args[1];
+ target_ulong vcpuid = args[2];
+ struct SpaprMachineStateNestedGuestVcpu *vcpu;
+ struct guest_state_request gsr;
+ SpaprMachineStateNestedGuest *guest;
+ target_ulong rc;
+
+ if (flags) /* don't handle any flags for now */
+ return H_PARAMETER;
+
+ guest = spapr_get_nested_guest(spapr, lpid);
+ if (!guest) {
+ return H_P2;
+ }
+ if (!spapr_nested_vcpu_check(guest, vcpuid, true)) {
+ return H_P3;
+ }
+
+ if (guest->parttbl[0] == 0) {
+ /* At least need a partition scoped radix tree */
+ return H_NOT_AVAILABLE;
+ }
+
+ vcpu = &guest->vcpus[vcpuid];
+
+ /* Read run_vcpu input buffer to update state */
+ gsr.buf = vcpu->runbufin.addr;
+ gsr.len = vcpu->runbufin.size;
+ gsr.flags = GUEST_STATE_REQUEST_SET; /* Thread wide + writing */
+ rc = map_and_getset_state(cpu, guest, vcpuid, &gsr);
+ if (rc == H_SUCCESS) {
+ nested_papr_run_vcpu(cpu, lpid, vcpu);
+ } else {
+ env->gpr[3] = rc;
+ }
+ return env->gpr[3];
+}
+
+void spapr_register_nested_hv(void)
{
spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested);
spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate);
spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_guest);
}
+
+void spapr_unregister_nested_hv(void)
+{
+ spapr_unregister_hypercall(KVMPPC_H_SET_PARTITION_TABLE);
+ spapr_unregister_hypercall(KVMPPC_H_ENTER_NESTED);
+ spapr_unregister_hypercall(KVMPPC_H_TLB_INVALIDATE);
+ spapr_unregister_hypercall(KVMPPC_H_COPY_TOFROM_GUEST);
+}
+
+void spapr_register_nested_papr(void)
+{
+ spapr_register_hypercall(H_GUEST_GET_CAPABILITIES,
+ h_guest_get_capabilities);
+ spapr_register_hypercall(H_GUEST_SET_CAPABILITIES,
+ h_guest_set_capabilities);
+ spapr_register_hypercall(H_GUEST_CREATE, h_guest_create);
+ spapr_register_hypercall(H_GUEST_DELETE, h_guest_delete);
+ spapr_register_hypercall(H_GUEST_CREATE_VCPU, h_guest_create_vcpu);
+ spapr_register_hypercall(H_GUEST_SET_STATE, h_guest_set_state);
+ spapr_register_hypercall(H_GUEST_GET_STATE, h_guest_get_state);
+ spapr_register_hypercall(H_GUEST_RUN_VCPU, h_guest_run_vcpu);
+}
+
+void spapr_unregister_nested_papr(void)
+{
+ spapr_unregister_hypercall(H_GUEST_GET_CAPABILITIES);
+ spapr_unregister_hypercall(H_GUEST_SET_CAPABILITIES);
+ spapr_unregister_hypercall(H_GUEST_CREATE);
+ spapr_unregister_hypercall(H_GUEST_DELETE);
+ spapr_unregister_hypercall(H_GUEST_CREATE_VCPU);
+ spapr_unregister_hypercall(H_GUEST_SET_STATE);
+ spapr_unregister_hypercall(H_GUEST_GET_STATE);
+ spapr_unregister_hypercall(H_GUEST_RUN_VCPU);
+}
+
#else
void spapr_exit_nested(PowerPCCPU *cpu, int excp)
{
g_assert_not_reached();
}
-void spapr_register_nested(void)
+void spapr_register_nested_hv(void)
{
/* DO NOTHING */
}
+
+void spapr_unregister_nested_hv(void)
+{
+ /* DO NOTHING */
+}
+
+bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry)
+{
+ return false;
+}
+
+bool spapr_get_pate_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry)
+{
+ return false;
+}
+
+void spapr_register_nested_papr(void)
+{
+ /* DO NOTHING */
+}
+
+void spapr_unregister_nested_papr(void)
+{
+ /* DO NOTHING */
+}
+
+void spapr_nested_gsb_init(void)
+{
+ /* DO NOTHING */
+}
+
#endif
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index 62804cc..b1dcb38 100644
--- a/hw/s390x/s390-virtio-ccw.c
+++ b/hw/s390x/s390-virtio-ccw.c
@@ -312,12 +312,12 @@
static void s390_cpu_plug(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
+ ERRP_GUARD();
MachineState *ms = MACHINE(hotplug_dev);
S390CPU *cpu = S390_CPU(dev);
- ERRP_GUARD();
g_assert(!ms->possible_cpus->cpus[cpu->env.core_id].cpu);
- ms->possible_cpus->cpus[cpu->env.core_id].cpu = OBJECT(dev);
+ ms->possible_cpus->cpus[cpu->env.core_id].cpu = CPU(dev);
if (s390_has_topology()) {
s390_topology_setup_cpu(ms, cpu, errp);
diff --git a/hw/scsi/vhost-scsi.c b/hw/scsi/vhost-scsi.c
index 58a0033..ae26bc1 100644
--- a/hw/scsi/vhost-scsi.c
+++ b/hw/scsi/vhost-scsi.c
@@ -220,6 +220,7 @@
static void vhost_scsi_realize(DeviceState *dev, Error **errp)
{
+ ERRP_GUARD();
VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(dev);
VHostSCSICommon *vsc = VHOST_SCSI_COMMON(dev);
Error *err = NULL;
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index eda9b58..cff6d5a 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -360,8 +360,13 @@
pci_dev->config[0x09] = 0x00; // programming i/f
pci_dev->config[0x0D] = 0x0a; // latency_timer
- memory_region_init_alias(&s->bar0, OBJECT(s), "bar0",
- pci_address_space_io(pci_dev), 0, 0x1000000);
+ /*
+ * BAR0 is accessed by OpenBSD but not for ebus device access: allow any
+ * memory access to this region to succeed which allows the OpenBSD kernel
+ * to boot.
+ */
+ memory_region_init_io(&s->bar0, OBJECT(s), &unassigned_io_ops, s,
+ "bar0", 0x1000000);
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
memory_region_init_alias(&s->bar1, OBJECT(s), "bar1",
pci_address_space_io(pci_dev), 0, 0x8000);
diff --git a/hw/vfio/ap.c b/hw/vfio/ap.c
index e157aa1..7c4caa5 100644
--- a/hw/vfio/ap.c
+++ b/hw/vfio/ap.c
@@ -155,6 +155,7 @@
static void vfio_ap_realize(DeviceState *dev, Error **errp)
{
+ ERRP_GUARD();
int ret;
Error *err = NULL;
VFIOAPDevice *vapdev = VFIO_AP_DEVICE(dev);
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index 059bfdc..011ceaa 100644
--- a/hw/vfio/common.c
+++ b/hw/vfio/common.c
@@ -39,7 +39,6 @@
#include "sysemu/runstate.h"
#include "trace.h"
#include "qapi/error.h"
-#include "migration/migration.h"
#include "migration/misc.h"
#include "migration/blocker.h"
#include "migration/qemu-file.h"
@@ -128,7 +127,7 @@
error_setg(&multiple_devices_migration_blocker,
"Multiple VFIO devices migration is supported only if all of "
"them support P2P migration");
- ret = migrate_add_blocker(&multiple_devices_migration_blocker, errp);
+ ret = migrate_add_blocker_normal(&multiple_devices_migration_blocker, errp);
return ret;
}
@@ -150,14 +149,8 @@
static void vfio_set_migration_error(int err)
{
- MigrationState *ms = migrate_get_current();
-
- if (migration_is_setup_or_active(ms->state)) {
- WITH_QEMU_LOCK_GUARD(&ms->qemu_file_lock) {
- if (ms->to_dst_file) {
- qemu_file_set_error(ms->to_dst_file, err);
- }
- }
+ if (migration_is_setup_or_active()) {
+ migration_file_set_error(err);
}
}
@@ -180,10 +173,8 @@
static bool vfio_devices_all_dirty_tracking(VFIOContainerBase *bcontainer)
{
VFIODevice *vbasedev;
- MigrationState *ms = migrate_get_current();
- if (ms->state != MIGRATION_STATUS_ACTIVE &&
- ms->state != MIGRATION_STATUS_DEVICE) {
+ if (!migration_is_active() && !migration_is_device()) {
return false;
}
@@ -225,7 +216,7 @@
{
VFIODevice *vbasedev;
- if (!migration_is_active(migrate_get_current())) {
+ if (!migration_is_active()) {
return false;
}
diff --git a/hw/vfio/container.c b/hw/vfio/container.c
index bd25b9f..77bdec2 100644
--- a/hw/vfio/container.c
+++ b/hw/vfio/container.c
@@ -32,7 +32,6 @@
#include "sysemu/reset.h"
#include "trace.h"
#include "qapi/error.h"
-#include "migration/migration.h"
#include "pci.h"
VFIOGroupList vfio_group_list =
@@ -621,10 +620,15 @@
goto free_container_exit;
}
+ ret = vfio_cpr_register_container(bcontainer, errp);
+ if (ret) {
+ goto free_container_exit;
+ }
+
ret = vfio_ram_block_discard_disable(container, true);
if (ret) {
error_setg_errno(errp, -ret, "Cannot set discarding of RAM broken");
- goto free_container_exit;
+ goto unregister_container_exit;
}
assert(bcontainer->ops->setup);
@@ -667,6 +671,9 @@
enable_discards_exit:
vfio_ram_block_discard_disable(container, false);
+unregister_container_exit:
+ vfio_cpr_unregister_container(bcontainer);
+
free_container_exit:
g_free(container);
@@ -710,6 +717,7 @@
vfio_container_destroy(bcontainer);
trace_vfio_disconnect_container(container->fd);
+ vfio_cpr_unregister_container(bcontainer);
close(container->fd);
g_free(container);
@@ -719,6 +727,7 @@
static VFIOGroup *vfio_get_group(int groupid, AddressSpace *as, Error **errp)
{
+ ERRP_GUARD();
VFIOGroup *group;
char path[32];
struct vfio_group_status status = { .argsz = sizeof(status) };
diff --git a/hw/vfio/cpr.c b/hw/vfio/cpr.c
new file mode 100644
index 0000000..392c2dd
--- /dev/null
+++ b/hw/vfio/cpr.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2021-2024 Oracle and/or its affiliates.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/vfio/vfio-common.h"
+#include "migration/misc.h"
+#include "qapi/error.h"
+#include "sysemu/runstate.h"
+
+static int vfio_cpr_reboot_notifier(NotifierWithReturn *notifier,
+ MigrationEvent *e, Error **errp)
+{
+ if (e->type == MIG_EVENT_PRECOPY_SETUP &&
+ !runstate_check(RUN_STATE_SUSPENDED) && !vm_get_suspended()) {
+
+ error_setg(errp,
+ "VFIO device only supports cpr-reboot for runstate suspended");
+
+ return -1;
+ }
+ return 0;
+}
+
+int vfio_cpr_register_container(VFIOContainerBase *bcontainer, Error **errp)
+{
+ migration_add_notifier_mode(&bcontainer->cpr_reboot_notifier,
+ vfio_cpr_reboot_notifier,
+ MIG_MODE_CPR_REBOOT);
+ return 0;
+}
+
+void vfio_cpr_unregister_container(VFIOContainerBase *bcontainer)
+{
+ migration_remove_notifier(&bcontainer->cpr_reboot_notifier);
+}
diff --git a/hw/vfio/helpers.c b/hw/vfio/helpers.c
index 6789870..47b4096 100644
--- a/hw/vfio/helpers.c
+++ b/hw/vfio/helpers.c
@@ -110,6 +110,7 @@
int vfio_set_irq_signaling(VFIODevice *vbasedev, int index, int subindex,
int action, int fd, Error **errp)
{
+ ERRP_GUARD();
struct vfio_irq_set *irq_set;
int argsz, ret = 0;
const char *name;
@@ -613,6 +614,7 @@
int vfio_device_get_name(VFIODevice *vbasedev, Error **errp)
{
+ ERRP_GUARD();
struct stat st;
if (vbasedev->fd < 0) {
@@ -644,6 +646,7 @@
void vfio_device_set_fd(VFIODevice *vbasedev, const char *str, Error **errp)
{
+ ERRP_GUARD();
int fd = monitor_fd_param(monitor_cur(), str, errp);
if (fd < 0) {
diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c
index 7baf49e..bafddb8 100644
--- a/hw/vfio/iommufd.c
+++ b/hw/vfio/iommufd.c
@@ -412,6 +412,11 @@
goto err_listener_register;
}
+ ret = vfio_cpr_register_container(bcontainer, errp);
+ if (ret) {
+ goto err_listener_register;
+ }
+
/*
* TODO: examine RAM_BLOCK_DISCARD stuff, should we do group level
* for discarding incompatibility check as well?
@@ -462,6 +467,7 @@
iommufd_cdev_ram_block_discard_disable(false);
}
+ vfio_cpr_unregister_container(bcontainer);
iommufd_cdev_detach_container(vbasedev, container);
iommufd_cdev_container_destroy(container);
vfio_put_address_space(space);
diff --git a/hw/vfio/meson.build b/hw/vfio/meson.build
index bb98493..bba776f 100644
--- a/hw/vfio/meson.build
+++ b/hw/vfio/meson.build
@@ -5,6 +5,7 @@
'container-base.c',
'container.c',
'migration.c',
+ 'cpr.c',
))
vfio_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr.c'))
vfio_ss.add(when: 'CONFIG_IOMMUFD', if_true: files(
diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c
index 50140ed..1149c6b 100644
--- a/hw/vfio/migration.c
+++ b/hw/vfio/migration.c
@@ -17,14 +17,12 @@
#include "sysemu/runstate.h"
#include "hw/vfio/vfio-common.h"
-#include "migration/migration.h"
-#include "migration/options.h"
+#include "migration/misc.h"
#include "migration/savevm.h"
#include "migration/vmstate.h"
#include "migration/qemu-file.h"
#include "migration/register.h"
#include "migration/blocker.h"
-#include "migration/misc.h"
#include "qapi/error.h"
#include "exec/ramlist.h"
#include "exec/ram_addr.h"
@@ -505,6 +503,12 @@
return vfio_device_state_is_precopy(vbasedev);
}
+/*
+ * Note about migration rate limiting: VFIO migration buffer size is currently
+ * limited to 1MB, so there is no need to check if migration rate exceeded (as
+ * in the worst case it will exceed by 1MB). However, if the buffer size is
+ * later changed to a bigger value, migration rate should be enforced here.
+ */
static int vfio_save_iterate(QEMUFile *f, void *opaque)
{
VFIODevice *vbasedev = opaque;
@@ -529,11 +533,7 @@
trace_vfio_save_iterate(vbasedev->name, migration->precopy_init_size,
migration->precopy_dirty_size);
- /*
- * A VFIO device's pre-copy dirty_bytes is not guaranteed to reach zero.
- * Return 1 so following handlers will not be potentially blocked.
- */
- return 1;
+ return !migration->precopy_init_size && !migration->precopy_dirty_size;
}
static int vfio_save_complete_precopy(QEMUFile *f, void *opaque)
@@ -713,9 +713,7 @@
* Migration should be aborted in this case, but vm_state_notify()
* currently does not support reporting failures.
*/
- if (migrate_get_current()->to_dst_file) {
- qemu_file_set_error(migrate_get_current()->to_dst_file, ret);
- }
+ migration_file_set_error(ret);
}
trace_vfio_vmstate_change_prepare(vbasedev->name, running,
@@ -745,9 +743,7 @@
* Migration should be aborted in this case, but vm_state_notify()
* currently does not support reporting failures.
*/
- if (migrate_get_current()->to_dst_file) {
- qemu_file_set_error(migrate_get_current()->to_dst_file, ret);
- }
+ migration_file_set_error(ret);
}
trace_vfio_vmstate_change(vbasedev->name, running, RunState_str(state),
@@ -889,7 +885,7 @@
vbasedev->migration_blocker = error_copy(err);
error_free(err);
- return migrate_add_blocker(&vbasedev->migration_blocker, errp);
+ return migrate_add_blocker_normal(&vbasedev->migration_blocker, errp);
}
/* ---------------------------------------------------------------------- */
diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
index 84b1a7b..496fd1e 100644
--- a/hw/vfio/pci-quirks.c
+++ b/hw/vfio/pci-quirks.c
@@ -1538,6 +1538,7 @@
static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp)
{
+ ERRP_GUARD();
PCIDevice *pdev = &vdev->pdev;
int ret, pos;
bool c8_conflict = false, d4_conflict = false;
@@ -1630,6 +1631,7 @@
#define VMD_SHADOW_CAP_LEN 24
static int vfio_add_vmd_shadow_cap(VFIOPCIDevice *vdev, Error **errp)
{
+ ERRP_GUARD();
uint8_t membar_phys[16];
int ret, pos = 0xE8;
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index a1522a0..64780d1 100644
--- a/hw/vfio/pci.c
+++ b/hw/vfio/pci.c
@@ -2136,6 +2136,7 @@
static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos, Error **errp)
{
+ ERRP_GUARD();
PCIDevice *pdev = &vdev->pdev;
uint8_t cap_id, next, size;
int ret;
@@ -2942,6 +2943,7 @@
static void vfio_realize(PCIDevice *pdev, Error **errp)
{
+ ERRP_GUARD();
VFIOPCIDevice *vdev = VFIO_PCI(pdev);
VFIODevice *vbasedev = &vdev->vbasedev;
char *tmp, *subsys;
diff --git a/hw/vfio/platform.c b/hw/vfio/platform.c
index a8d9b7d..dcd2365 100644
--- a/hw/vfio/platform.c
+++ b/hw/vfio/platform.c
@@ -576,6 +576,7 @@
*/
static void vfio_platform_realize(DeviceState *dev, Error **errp)
{
+ ERRP_GUARD();
VFIOPlatformDevice *vdev = VFIO_PLATFORM_DEVICE(dev);
SysBusDevice *sbdev = SYS_BUS_DEVICE(dev);
VFIODevice *vbasedev = &vdev->vbasedev;
diff --git a/hw/virtio/vhost-user-scmi.c b/hw/virtio/vhost-user-scmi.c
index 918bb7d..300847e 100644
--- a/hw/virtio/vhost-user-scmi.c
+++ b/hw/virtio/vhost-user-scmi.c
@@ -56,9 +56,9 @@
goto err_host_notifiers;
}
- vhost_ack_features(&scmi->vhost_dev, feature_bits, vdev->guest_features);
+ vhost_ack_features(vhost_dev, feature_bits, vdev->guest_features);
- ret = vhost_dev_start(&scmi->vhost_dev, vdev, true);
+ ret = vhost_dev_start(vhost_dev, vdev, true);
if (ret < 0) {
error_report("Error starting vhost-user-scmi: %d", ret);
goto err_guest_notifiers;
@@ -71,7 +71,7 @@
* enabling/disabling irqfd.
*/
for (i = 0; i < scmi->vhost_dev.nvqs; i++) {
- vhost_virtqueue_mask(&scmi->vhost_dev, vdev, i, false);
+ vhost_virtqueue_mask(vhost_dev, vdev, i, false);
}
return 0;
diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
index 9d654ef..cdf9af4 100644
--- a/hw/virtio/vhost-user.c
+++ b/hw/virtio/vhost-user.c
@@ -26,7 +26,6 @@
#include "qemu/sockets.h"
#include "sysemu/runstate.h"
#include "sysemu/cryptodev.h"
-#include "migration/migration.h"
#include "migration/postcopy-ram.h"
#include "trace.h"
#include "exec/ramblock.h"
diff --git a/hw/virtio/vhost-vsock.c b/hw/virtio/vhost-vsock.c
index d5ca0b5..3d4a5a9 100644
--- a/hw/virtio/vhost-vsock.c
+++ b/hw/virtio/vhost-vsock.c
@@ -121,6 +121,7 @@
static void vhost_vsock_device_realize(DeviceState *dev, Error **errp)
{
+ ERRP_GUARD();
VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(dev);
VirtIODevice *vdev = VIRTIO_DEVICE(dev);
VHostVSock *vsock = VHOST_VSOCK(dev);
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
index 2c9ac79..2e4e040 100644
--- a/hw/virtio/vhost.c
+++ b/hw/virtio/vhost.c
@@ -2199,6 +2199,7 @@
int vhost_save_backend_state(struct vhost_dev *dev, QEMUFile *f, Error **errp)
{
+ ERRP_GUARD();
/* Maximum chunk size in which to transfer the state */
const size_t chunk_size = 1 * 1024 * 1024;
g_autofree void *transfer_buf = NULL;
@@ -2291,6 +2292,7 @@
int vhost_load_backend_state(struct vhost_dev *dev, QEMUFile *f, Error **errp)
{
+ ERRP_GUARD();
size_t transfer_buf_size = 0;
g_autofree void *transfer_buf = NULL;
g_autoptr(GError) g_err = NULL;
diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c
index 89f853f..609e39a 100644
--- a/hw/virtio/virtio-balloon.c
+++ b/hw/virtio/virtio-balloon.c
@@ -31,8 +31,6 @@
#include "trace.h"
#include "qemu/error-report.h"
#include "migration/misc.h"
-#include "migration/migration.h"
-#include "migration/options.h"
#include "hw/virtio/virtio-bus.h"
#include "hw/virtio/virtio-access.h"
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index e42ac6e..eaaf864 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -2095,7 +2095,7 @@
bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
uint8_t *config;
uint32_t size;
- VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
+ VirtIODevice *vdev = virtio_bus_get_device(bus);
/*
* Virtio capabilities present without
diff --git a/hw/xen/xen-mapcache.c b/hw/xen/xen-mapcache.c
index 4f956d0..7f59080 100644
--- a/hw/xen/xen-mapcache.c
+++ b/hw/xen/xen-mapcache.c
@@ -476,11 +476,37 @@
g_free(entry);
}
-void xen_invalidate_map_cache_entry(uint8_t *buffer)
+typedef struct XenMapCacheData {
+ Coroutine *co;
+ uint8_t *buffer;
+} XenMapCacheData;
+
+static void xen_invalidate_map_cache_entry_bh(void *opaque)
{
+ XenMapCacheData *data = opaque;
+
mapcache_lock();
- xen_invalidate_map_cache_entry_unlocked(buffer);
+ xen_invalidate_map_cache_entry_unlocked(data->buffer);
mapcache_unlock();
+
+ aio_co_wake(data->co);
+}
+
+void coroutine_mixed_fn xen_invalidate_map_cache_entry(uint8_t *buffer)
+{
+ if (qemu_in_coroutine()) {
+ XenMapCacheData data = {
+ .co = qemu_coroutine_self(),
+ .buffer = buffer,
+ };
+ aio_bh_schedule_oneshot(qemu_get_current_aio_context(),
+ xen_invalidate_map_cache_entry_bh, &data);
+ qemu_coroutine_yield();
+ } else {
+ mapcache_lock();
+ xen_invalidate_map_cache_entry_unlocked(buffer);
+ mapcache_unlock();
+ }
}
void xen_invalidate_map_cache(void)
diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c
index a8edabd..3635d1b 100644
--- a/hw/xen/xen_pt.c
+++ b/hw/xen/xen_pt.c
@@ -711,7 +711,7 @@
uint8_t intx;
int rc;
- if (machine_irq && !xen_host_pci_device_closed(&s->real_device)) {
+ if (machine_irq && !xen_host_pci_device_closed(host_dev)) {
intx = xen_pt_pci_intx(s);
rc = xc_domain_unbind_pt_irq(xen_xc, xen_domid, machine_irq,
PT_IRQ_TYPE_PCI,
@@ -760,8 +760,8 @@
memory_listener_unregister(&s->io_listener);
s->listener_set = false;
}
- if (!xen_host_pci_device_closed(&s->real_device)) {
- xen_host_pci_device_put(&s->real_device);
+ if (!xen_host_pci_device_closed(host_dev)) {
+ xen_host_pci_device_put(host_dev);
}
}
/* init */
diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c
index ba4cd78..3edaeab 100644
--- a/hw/xen/xen_pt_config_init.c
+++ b/hw/xen/xen_pt_config_init.c
@@ -292,7 +292,10 @@
uint32_t *data)
{
/* read PCI_HEADER_TYPE */
- *data = reg->init_val | 0x80;
+ *data = reg->init_val;
+ if ((PCI_DEVICE(s)->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
+ *data |= PCI_HEADER_TYPE_MULTI_FUNCTION;
+ }
return 0;
}
@@ -677,7 +680,7 @@
.size = 1,
.init_val = 0x00,
.ro_mask = 0xFF,
- .emu_mask = 0x00,
+ .emu_mask = PCI_HEADER_TYPE_MULTI_FUNCTION,
.init = xen_pt_header_type_reg_init,
.u.b.read = xen_pt_byte_reg_read,
.u.b.write = xen_pt_byte_reg_write,
diff --git a/include/hw/boards.h b/include/hw/boards.h
index bcfde8a..8b8f6d5 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -120,7 +120,7 @@
uint64_t arch_id;
int64_t vcpus_count;
CpuInstanceProperties props;
- Object *cpu;
+ CPUState *cpu;
const char *type;
} CPUArchId;
diff --git a/include/hw/gpio/pcf8574.h b/include/hw/gpio/pcf8574.h
new file mode 100644
index 0000000..3291d7d
--- /dev/null
+++ b/include/hw/gpio/pcf8574.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * NXP PCF8574 8-port I2C GPIO expansion chip.
+ *
+ * Copyright (c) 2024 KNS Group (YADRO).
+ * Written by Dmitrii Sharikhin <d.sharikhin@yadro.com>
+ */
+
+#ifndef _HW_GPIO_PCF8574
+#define _HW_GPIO_PCF8574
+
+#define TYPE_PCF8574 "pcf8574"
+
+#endif /* _HW_GPIO_PCF8574 */
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index af4cd7a..8589f32 100644
--- a/include/hw/ppc/pnv_chip.h
+++ b/include/hw/ppc/pnv_chip.h
@@ -147,7 +147,7 @@
DeviceRealize parent_realize;
- uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
+ uint32_t (*chip_pir)(PnvChip *chip, uint32_t core_id, uint32_t thread_id);
void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
index 4db2122..c6d62fd 100644
--- a/include/hw/ppc/pnv_core.h
+++ b/include/hw/ppc/pnv_core.h
@@ -36,6 +36,7 @@
/*< public >*/
PowerPCCPU **threads;
uint32_t pir;
+ uint32_t hwid;
uint64_t hrmor;
PnvChip *chip;
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 5b5ba9e..4aaf23d 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -12,6 +12,7 @@
#include "hw/ppc/spapr_xive.h" /* For SpaprXive */
#include "hw/ppc/xics.h" /* For ICSState */
#include "hw/ppc/spapr_tpm_proxy.h"
+#include "hw/ppc/spapr_nested.h" /* For SpaprMachineStateNested */
struct SpaprVioBus;
struct SpaprPhbState;
@@ -80,8 +81,10 @@
#define SPAPR_CAP_RPT_INVALIDATE 0x0B
/* Support for AIL modes */
#define SPAPR_CAP_AIL_MODE_3 0x0C
+/* Nested PAPR */
+#define SPAPR_CAP_NESTED_PAPR 0x0D
/* Num Caps */
-#define SPAPR_CAP_NUM (SPAPR_CAP_AIL_MODE_3 + 1)
+#define SPAPR_CAP_NUM (SPAPR_CAP_NESTED_PAPR + 1)
/*
* Capability Values
@@ -213,7 +216,7 @@
uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */
/* Nested HV support (TCG only) */
- uint64_t nested_ptcr;
+ SpaprMachineStateNested nested;
Notifier epow_notifier;
QTAILQ_HEAD(, SpaprEventLogEntry) pending_events;
@@ -363,6 +366,9 @@
#define H_NOOP -63
#define H_UNSUPPORTED -67
#define H_OVERLAP -68
+#define H_STATE -75
+#define H_IN_USE -77
+#define H_INVALID_ELEMENT_VALUE -81
#define H_UNSUPPORTED_FLAG -256
#define H_MULTI_THREADS_ACTIVE -9005
@@ -582,8 +588,16 @@
#define H_RPT_INVALIDATE 0x448
#define H_SCM_FLUSH 0x44C
#define H_WATCHDOG 0x45C
+#define H_GUEST_GET_CAPABILITIES 0x460
+#define H_GUEST_SET_CAPABILITIES 0x464
+#define H_GUEST_CREATE 0x470
+#define H_GUEST_CREATE_VCPU 0x474
+#define H_GUEST_GET_STATE 0x478
+#define H_GUEST_SET_STATE 0x47C
+#define H_GUEST_RUN_VCPU 0x480
+#define H_GUEST_DELETE 0x488
-#define MAX_HCALL_OPCODE H_WATCHDOG
+#define MAX_HCALL_OPCODE H_GUEST_DELETE
/* The hcalls above are standardized in PAPR and implemented by pHyp
* as well.
@@ -631,6 +645,7 @@
target_ulong *args);
void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
+void spapr_unregister_hypercall(target_ulong opcode);
target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
target_ulong *args);
@@ -984,6 +999,7 @@
extern const VMStateDescription vmstate_spapr_cap_ibs;
extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize;
extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv;
+extern const VMStateDescription vmstate_spapr_cap_nested_papr;
extern const VMStateDescription vmstate_spapr_cap_large_decr;
extern const VMStateDescription vmstate_spapr_cap_ccf_assist;
extern const VMStateDescription vmstate_spapr_cap_fwnmi;
@@ -1028,5 +1044,10 @@
/* H_WATCHDOG */
void spapr_watchdog_init(SpaprMachineState *spapr);
+void spapr_register_nested_hv(void);
+void spapr_unregister_nested_hv(void);
+void spapr_nested_reset(SpaprMachineState *spapr);
+void spapr_register_nested_papr(void);
+void spapr_unregister_nested_papr(void);
#endif /* HW_SPAPR_H */
diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h
index d312a5d..93ef14a 100644
--- a/include/hw/ppc/spapr_nested.h
+++ b/include/hw/ppc/spapr_nested.h
@@ -3,6 +3,348 @@
#include "target/ppc/cpu.h"
+/* Guest State Buffer Element IDs */
+#define GSB_HV_VCPU_IGNORED_ID 0x0000 /* An element whose value is ignored */
+#define GSB_HV_VCPU_STATE_SIZE 0x0001 /* HV internal format VCPU state size */
+#define GSB_VCPU_OUT_BUF_MIN_SZ 0x0002 /* Min size of the Run VCPU o/p buffer */
+#define GSB_VCPU_LPVR 0x0003 /* Logical PVR */
+#define GSB_TB_OFFSET 0x0004 /* Timebase Offset */
+#define GSB_PART_SCOPED_PAGETBL 0x0005 /* Partition Scoped Page Table */
+#define GSB_PROCESS_TBL 0x0006 /* Process Table */
+ /* RESERVED 0x0007 - 0x0BFF */
+#define GSB_VCPU_IN_BUFFER 0x0C00 /* Run VCPU Input Buffer */
+#define GSB_VCPU_OUT_BUFFER 0x0C01 /* Run VCPU Out Buffer */
+#define GSB_VCPU_VPA 0x0C02 /* HRA to Guest VCPU VPA */
+ /* RESERVED 0x0C03 - 0x0FFF */
+#define GSB_VCPU_GPR0 0x1000
+#define GSB_VCPU_GPR1 0x1001
+#define GSB_VCPU_GPR2 0x1002
+#define GSB_VCPU_GPR3 0x1003
+#define GSB_VCPU_GPR4 0x1004
+#define GSB_VCPU_GPR5 0x1005
+#define GSB_VCPU_GPR6 0x1006
+#define GSB_VCPU_GPR7 0x1007
+#define GSB_VCPU_GPR8 0x1008
+#define GSB_VCPU_GPR9 0x1009
+#define GSB_VCPU_GPR10 0x100A
+#define GSB_VCPU_GPR11 0x100B
+#define GSB_VCPU_GPR12 0x100C
+#define GSB_VCPU_GPR13 0x100D
+#define GSB_VCPU_GPR14 0x100E
+#define GSB_VCPU_GPR15 0x100F
+#define GSB_VCPU_GPR16 0x1010
+#define GSB_VCPU_GPR17 0x1011
+#define GSB_VCPU_GPR18 0x1012
+#define GSB_VCPU_GPR19 0x1013
+#define GSB_VCPU_GPR20 0x1014
+#define GSB_VCPU_GPR21 0x1015
+#define GSB_VCPU_GPR22 0x1016
+#define GSB_VCPU_GPR23 0x1017
+#define GSB_VCPU_GPR24 0x1018
+#define GSB_VCPU_GPR25 0x1019
+#define GSB_VCPU_GPR26 0x101A
+#define GSB_VCPU_GPR27 0x101B
+#define GSB_VCPU_GPR28 0x101C
+#define GSB_VCPU_GPR29 0x101D
+#define GSB_VCPU_GPR30 0x101E
+#define GSB_VCPU_GPR31 0x101F
+#define GSB_VCPU_HDEC_EXPIRY_TB 0x1020
+#define GSB_VCPU_SPR_NIA 0x1021
+#define GSB_VCPU_SPR_MSR 0x1022
+#define GSB_VCPU_SPR_LR 0x1023
+#define GSB_VCPU_SPR_XER 0x1024
+#define GSB_VCPU_SPR_CTR 0x1025
+#define GSB_VCPU_SPR_CFAR 0x1026
+#define GSB_VCPU_SPR_SRR0 0x1027
+#define GSB_VCPU_SPR_SRR1 0x1028
+#define GSB_VCPU_SPR_DAR 0x1029
+#define GSB_VCPU_DEC_EXPIRE_TB 0x102A
+#define GSB_VCPU_SPR_VTB 0x102B
+#define GSB_VCPU_SPR_LPCR 0x102C
+#define GSB_VCPU_SPR_HFSCR 0x102D
+#define GSB_VCPU_SPR_FSCR 0x102E
+#define GSB_VCPU_SPR_FPSCR 0x102F
+#define GSB_VCPU_SPR_DAWR0 0x1030
+#define GSB_VCPU_SPR_DAWR1 0x1031
+#define GSB_VCPU_SPR_CIABR 0x1032
+#define GSB_VCPU_SPR_PURR 0x1033
+#define GSB_VCPU_SPR_SPURR 0x1034
+#define GSB_VCPU_SPR_IC 0x1035
+#define GSB_VCPU_SPR_SPRG0 0x1036
+#define GSB_VCPU_SPR_SPRG1 0x1037
+#define GSB_VCPU_SPR_SPRG2 0x1038
+#define GSB_VCPU_SPR_SPRG3 0x1039
+#define GSB_VCPU_SPR_PPR 0x103A
+#define GSB_VCPU_SPR_MMCR0 0x103B
+#define GSB_VCPU_SPR_MMCR1 0x103C
+#define GSB_VCPU_SPR_MMCR2 0x103D
+#define GSB_VCPU_SPR_MMCR3 0x103E
+#define GSB_VCPU_SPR_MMCRA 0x103F
+#define GSB_VCPU_SPR_SIER 0x1040
+#define GSB_VCPU_SPR_SIER2 0x1041
+#define GSB_VCPU_SPR_SIER3 0x1042
+#define GSB_VCPU_SPR_BESCR 0x1043
+#define GSB_VCPU_SPR_EBBHR 0x1044
+#define GSB_VCPU_SPR_EBBRR 0x1045
+#define GSB_VCPU_SPR_AMR 0x1046
+#define GSB_VCPU_SPR_IAMR 0x1047
+#define GSB_VCPU_SPR_AMOR 0x1048
+#define GSB_VCPU_SPR_UAMOR 0x1049
+#define GSB_VCPU_SPR_SDAR 0x104A
+#define GSB_VCPU_SPR_SIAR 0x104B
+#define GSB_VCPU_SPR_DSCR 0x104C
+#define GSB_VCPU_SPR_TAR 0x104D
+#define GSB_VCPU_SPR_DEXCR 0x104E
+#define GSB_VCPU_SPR_HDEXCR 0x104F
+#define GSB_VCPU_SPR_HASHKEYR 0x1050
+#define GSB_VCPU_SPR_HASHPKEYR 0x1051
+#define GSB_VCPU_SPR_CTRL 0x1052
+ /* RESERVED 0x1053 - 0x1FFF */
+#define GSB_VCPU_SPR_CR 0x2000
+#define GSB_VCPU_SPR_PIDR 0x2001
+#define GSB_VCPU_SPR_DSISR 0x2002
+#define GSB_VCPU_SPR_VSCR 0x2003
+#define GSB_VCPU_SPR_VRSAVE 0x2004
+#define GSB_VCPU_SPR_DAWRX0 0x2005
+#define GSB_VCPU_SPR_DAWRX1 0x2006
+#define GSB_VCPU_SPR_PMC1 0x2007
+#define GSB_VCPU_SPR_PMC2 0x2008
+#define GSB_VCPU_SPR_PMC3 0x2009
+#define GSB_VCPU_SPR_PMC4 0x200A
+#define GSB_VCPU_SPR_PMC5 0x200B
+#define GSB_VCPU_SPR_PMC6 0x200C
+#define GSB_VCPU_SPR_WORT 0x200D
+#define GSB_VCPU_SPR_PSPB 0x200E
+ /* RESERVED 0x200F - 0x2FFF */
+#define GSB_VCPU_SPR_VSR0 0x3000
+#define GSB_VCPU_SPR_VSR1 0x3001
+#define GSB_VCPU_SPR_VSR2 0x3002
+#define GSB_VCPU_SPR_VSR3 0x3003
+#define GSB_VCPU_SPR_VSR4 0x3004
+#define GSB_VCPU_SPR_VSR5 0x3005
+#define GSB_VCPU_SPR_VSR6 0x3006
+#define GSB_VCPU_SPR_VSR7 0x3007
+#define GSB_VCPU_SPR_VSR8 0x3008
+#define GSB_VCPU_SPR_VSR9 0x3009
+#define GSB_VCPU_SPR_VSR10 0x300A
+#define GSB_VCPU_SPR_VSR11 0x300B
+#define GSB_VCPU_SPR_VSR12 0x300C
+#define GSB_VCPU_SPR_VSR13 0x300D
+#define GSB_VCPU_SPR_VSR14 0x300E
+#define GSB_VCPU_SPR_VSR15 0x300F
+#define GSB_VCPU_SPR_VSR16 0x3010
+#define GSB_VCPU_SPR_VSR17 0x3011
+#define GSB_VCPU_SPR_VSR18 0x3012
+#define GSB_VCPU_SPR_VSR19 0x3013
+#define GSB_VCPU_SPR_VSR20 0x3014
+#define GSB_VCPU_SPR_VSR21 0x3015
+#define GSB_VCPU_SPR_VSR22 0x3016
+#define GSB_VCPU_SPR_VSR23 0x3017
+#define GSB_VCPU_SPR_VSR24 0x3018
+#define GSB_VCPU_SPR_VSR25 0x3019
+#define GSB_VCPU_SPR_VSR26 0x301A
+#define GSB_VCPU_SPR_VSR27 0x301B
+#define GSB_VCPU_SPR_VSR28 0x301C
+#define GSB_VCPU_SPR_VSR29 0x301D
+#define GSB_VCPU_SPR_VSR30 0x301E
+#define GSB_VCPU_SPR_VSR31 0x301F
+#define GSB_VCPU_SPR_VSR32 0x3020
+#define GSB_VCPU_SPR_VSR33 0x3021
+#define GSB_VCPU_SPR_VSR34 0x3022
+#define GSB_VCPU_SPR_VSR35 0x3023
+#define GSB_VCPU_SPR_VSR36 0x3024
+#define GSB_VCPU_SPR_VSR37 0x3025
+#define GSB_VCPU_SPR_VSR38 0x3026
+#define GSB_VCPU_SPR_VSR39 0x3027
+#define GSB_VCPU_SPR_VSR40 0x3028
+#define GSB_VCPU_SPR_VSR41 0x3029
+#define GSB_VCPU_SPR_VSR42 0x302A
+#define GSB_VCPU_SPR_VSR43 0x302B
+#define GSB_VCPU_SPR_VSR44 0x302C
+#define GSB_VCPU_SPR_VSR45 0x302D
+#define GSB_VCPU_SPR_VSR46 0x302E
+#define GSB_VCPU_SPR_VSR47 0x302F
+#define GSB_VCPU_SPR_VSR48 0x3030
+#define GSB_VCPU_SPR_VSR49 0x3031
+#define GSB_VCPU_SPR_VSR50 0x3032
+#define GSB_VCPU_SPR_VSR51 0x3033
+#define GSB_VCPU_SPR_VSR52 0x3034
+#define GSB_VCPU_SPR_VSR53 0x3035
+#define GSB_VCPU_SPR_VSR54 0x3036
+#define GSB_VCPU_SPR_VSR55 0x3037
+#define GSB_VCPU_SPR_VSR56 0x3038
+#define GSB_VCPU_SPR_VSR57 0x3039
+#define GSB_VCPU_SPR_VSR58 0x303A
+#define GSB_VCPU_SPR_VSR59 0x303B
+#define GSB_VCPU_SPR_VSR60 0x303C
+#define GSB_VCPU_SPR_VSR61 0x303D
+#define GSB_VCPU_SPR_VSR62 0x303E
+#define GSB_VCPU_SPR_VSR63 0x303F
+ /* RESERVED 0x3040 - 0xEFFF */
+#define GSB_VCPU_SPR_HDAR 0xF000
+#define GSB_VCPU_SPR_HDSISR 0xF001
+#define GSB_VCPU_SPR_HEIR 0xF002
+#define GSB_VCPU_SPR_ASDR 0xF003
+/* End of list of Guest State Buffer Element IDs */
+#define GSB_LAST GSB_VCPU_SPR_ASDR
+
+typedef struct SpaprMachineStateNested {
+ uint64_t ptcr;
+ uint8_t api;
+#define NESTED_API_KVM_HV 1
+#define NESTED_API_PAPR 2
+ bool capabilities_set;
+ uint32_t pvr_base;
+ GHashTable *guests;
+} SpaprMachineStateNested;
+
+typedef struct SpaprMachineStateNestedGuest {
+ uint32_t pvr_logical;
+ unsigned long nr_vcpus;
+ uint64_t parttbl[2];
+ uint64_t tb_offset;
+ struct SpaprMachineStateNestedGuestVcpu *vcpus;
+} SpaprMachineStateNestedGuest;
+
+/* Nested PAPR API related macros */
+#define H_GUEST_CAPABILITIES_COPY_MEM 0x8000000000000000
+#define H_GUEST_CAPABILITIES_P9_MODE 0x4000000000000000
+#define H_GUEST_CAPABILITIES_P10_MODE 0x2000000000000000
+#define H_GUEST_CAP_VALID_MASK (H_GUEST_CAPABILITIES_P10_MODE | \
+ H_GUEST_CAPABILITIES_P9_MODE)
+#define H_GUEST_CAP_COPY_MEM_BMAP 0
+#define H_GUEST_CAP_P9_MODE_BMAP 1
+#define H_GUEST_CAP_P10_MODE_BMAP 2
+#define PAPR_NESTED_GUEST_MAX 4096
+#define H_GUEST_DELETE_ALL_FLAG 0x8000000000000000ULL
+#define PAPR_NESTED_GUEST_VCPU_MAX 2048
+#define VCPU_OUT_BUF_MIN_SZ 0x80ULL
+#define HVMASK_DEFAULT 0xffffffffffffffff
+#define HVMASK_LPCR 0x0070000003820800
+#define HVMASK_MSR 0xEBFFFFFFFFBFEFFF
+#define HVMASK_HDEXCR 0x00000000FFFFFFFF
+#define HVMASK_TB_OFFSET 0x000000FFFFFFFFFF
+#define GSB_MAX_BUF_SIZE (1024 * 1024)
+#define H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE 0x8000000000000000
+#define GUEST_STATE_REQUEST_GUEST_WIDE 0x1
+#define GUEST_STATE_REQUEST_SET 0x2
+
+/*
+ * As per ISA v3.1B, following bits are reserved:
+ * 0:2
+ * 4:57 (ISA mentions bit 58 as well but it should be used for P10)
+ * 61:63 (hence, haven't included PCR bits for v2.06 and v2.05
+ * in LOW BITS)
+ */
+#define PCR_LOW_BITS (PCR_COMPAT_3_10 | PCR_COMPAT_3_00)
+#define HVMASK_PCR (~PCR_LOW_BITS)
+
+#define GUEST_STATE_ELEMENT(i, sz, s, f, ptr, c) { \
+ .id = (i), \
+ .size = (sz), \
+ .location = ptr, \
+ .offset = offsetof(struct s, f), \
+ .copy = (c) \
+}
+
+#define GSBE_NESTED(i, sz, f, c) { \
+ .id = (i), \
+ .size = (sz), \
+ .location = get_guest_ptr, \
+ .offset = offsetof(struct SpaprMachineStateNestedGuest, f),\
+ .copy = (c), \
+ .mask = HVMASK_DEFAULT \
+}
+
+#define GSBE_NESTED_MSK(i, sz, f, c, m) { \
+ .id = (i), \
+ .size = (sz), \
+ .location = get_guest_ptr, \
+ .offset = offsetof(struct SpaprMachineStateNestedGuest, f),\
+ .copy = (c), \
+ .mask = (m) \
+}
+
+#define GSBE_NESTED_VCPU(i, sz, f, c) { \
+ .id = (i), \
+ .size = (sz), \
+ .location = get_vcpu_ptr, \
+ .offset = offsetof(struct SpaprMachineStateNestedGuestVcpu, f),\
+ .copy = (c), \
+ .mask = HVMASK_DEFAULT \
+}
+
+#define GUEST_STATE_ELEMENT_NOP(i, sz) { \
+ .id = (i), \
+ .size = (sz), \
+ .location = NULL, \
+ .offset = 0, \
+ .copy = NULL, \
+ .mask = HVMASK_DEFAULT \
+}
+
+#define GUEST_STATE_ELEMENT_NOP_DW(i) \
+ GUEST_STATE_ELEMENT_NOP(i, 8)
+#define GUEST_STATE_ELEMENT_NOP_W(i) \
+ GUEST_STATE_ELEMENT_NOP(i, 4)
+
+#define GUEST_STATE_ELEMENT_BASE(i, s, c) { \
+ .id = (i), \
+ .size = (s), \
+ .location = get_vcpu_state_ptr, \
+ .offset = 0, \
+ .copy = (c), \
+ .mask = HVMASK_DEFAULT \
+ }
+
+#define GUEST_STATE_ELEMENT_OFF(i, s, f, c) { \
+ .id = (i), \
+ .size = (s), \
+ .location = get_vcpu_state_ptr, \
+ .offset = offsetof(struct nested_ppc_state, f), \
+ .copy = (c), \
+ .mask = HVMASK_DEFAULT \
+ }
+
+#define GUEST_STATE_ELEMENT_MSK(i, s, f, c, m) { \
+ .id = (i), \
+ .size = (s), \
+ .location = get_vcpu_state_ptr, \
+ .offset = offsetof(struct nested_ppc_state, f), \
+ .copy = (c), \
+ .mask = (m) \
+ }
+
+#define GUEST_STATE_ELEMENT_ENV_QW(i, f) \
+ GUEST_STATE_ELEMENT_OFF(i, 16, f, copy_state_16to16)
+#define GUEST_STATE_ELEMENT_ENV_DW(i, f) \
+ GUEST_STATE_ELEMENT_OFF(i, 8, f, copy_state_8to8)
+#define GUEST_STATE_ELEMENT_ENV_W(i, f) \
+ GUEST_STATE_ELEMENT_OFF(i, 4, f, copy_state_4to8)
+#define GUEST_STATE_ELEMENT_ENV_WW(i, f) \
+ GUEST_STATE_ELEMENT_OFF(i, 4, f, copy_state_4to4)
+#define GSE_ENV_DWM(i, f, m) \
+ GUEST_STATE_ELEMENT_MSK(i, 8, f, copy_state_8to8, m)
+
+struct guest_state_element {
+ uint16_t id;
+ uint16_t size;
+ uint8_t value[];
+} QEMU_PACKED;
+
+struct guest_state_buffer {
+ uint32_t num_elements;
+ struct guest_state_element elements[];
+} QEMU_PACKED;
+
+/* Actual buffer plus some metadata about the request */
+struct guest_state_request {
+ struct guest_state_buffer *gsb;
+ int64_t buf;
+ int64_t len;
+ uint16_t flags;
+};
+
/*
* Register state for entering a nested guest with H_ENTER_NESTED.
* New member must be added at the end.
@@ -93,9 +435,90 @@
uint64_t ppr;
int64_t tb_offset;
+ /* Nested PAPR API */
+ uint64_t amor;
+ uint64_t dawr0;
+ uint64_t dawrx0;
+ uint64_t ciabr;
+ uint64_t purr;
+ uint64_t spurr;
+ uint64_t ic;
+ uint64_t vtb;
+ uint64_t hdar;
+ uint64_t hdsisr;
+ uint64_t heir;
+ uint64_t asdr;
+ uint64_t dawr1;
+ uint64_t dawrx1;
+ uint64_t dexcr;
+ uint64_t hdexcr;
+ uint64_t hashkeyr;
+ uint64_t hashpkeyr;
+ ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
+ uint64_t ebbhr;
+ uint64_t tar;
+ uint64_t ebbrr;
+ uint64_t bescr;
+ uint64_t iamr;
+ uint64_t amr;
+ uint64_t uamor;
+ uint64_t dscr;
+ uint64_t fscr;
+ uint64_t pspb;
+ uint64_t ctrl;
+ uint64_t vrsave;
+ uint64_t dar;
+ uint64_t dsisr;
+ uint64_t pmc1;
+ uint64_t pmc2;
+ uint64_t pmc3;
+ uint64_t pmc4;
+ uint64_t pmc5;
+ uint64_t pmc6;
+ uint64_t mmcr0;
+ uint64_t mmcr1;
+ uint64_t mmcr2;
+ uint64_t mmcra;
+ uint64_t sdar;
+ uint64_t siar;
+ uint64_t sier;
+ uint32_t vscr;
+ uint64_t fpscr;
+ int64_t dec_expiry_tb;
};
-void spapr_register_nested(void);
-void spapr_exit_nested(PowerPCCPU *cpu, int excp);
+struct SpaprMachineStateNestedGuestVcpuRunBuf {
+ uint64_t addr;
+ uint64_t size;
+};
+typedef struct SpaprMachineStateNestedGuestVcpu {
+ bool enabled;
+ struct nested_ppc_state state;
+ struct SpaprMachineStateNestedGuestVcpuRunBuf runbufin;
+ struct SpaprMachineStateNestedGuestVcpuRunBuf runbufout;
+ int64_t tb_offset;
+ uint64_t hdecr_expiry_tb;
+} SpaprMachineStateNestedGuestVcpu;
+
+struct guest_state_element_type {
+ uint16_t id;
+ int size;
+#define GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE 0x1
+#define GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY 0x2
+ uint16_t flags;
+ void *(*location)(SpaprMachineStateNestedGuest *, target_ulong);
+ size_t offset;
+ void (*copy)(void *, void *, bool);
+ uint64_t mask;
+};
+
+void spapr_exit_nested(PowerPCCPU *cpu, int excp);
+typedef struct SpaprMachineState SpaprMachineState;
+bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry);
+uint8_t spapr_nested_api(SpaprMachineState *spapr);
+void spapr_nested_gsb_init(void);
+bool spapr_get_pate_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry);
#endif /* HW_SPAPR_NESTED_H */
diff --git a/include/hw/qdev-properties-system.h b/include/hw/qdev-properties-system.h
index 626be87..438f653 100644
--- a/include/hw/qdev-properties-system.h
+++ b/include/hw/qdev-properties-system.h
@@ -9,6 +9,7 @@
extern const PropertyInfo qdev_prop_multifd_compression;
extern const PropertyInfo qdev_prop_mig_mode;
extern const PropertyInfo qdev_prop_granule_mode;
+extern const PropertyInfo qdev_prop_zero_page_detection;
extern const PropertyInfo qdev_prop_losttickpolicy;
extern const PropertyInfo qdev_prop_blockdev_on_error;
extern const PropertyInfo qdev_prop_bios_chs_trans;
@@ -50,6 +51,9 @@
MigMode)
#define DEFINE_PROP_GRANULE_MODE(_n, _s, _f, _d) \
DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_granule_mode, GranuleMode)
+#define DEFINE_PROP_ZERO_PAGE_DETECTION(_n, _s, _f, _d) \
+ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_zero_page_detection, \
+ ZeroPageDetection)
#define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \
DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_losttickpolicy, \
LostTickPolicy)
diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
index 4a6c262..b9da6c0 100644
--- a/include/hw/vfio/vfio-common.h
+++ b/include/hw/vfio/vfio-common.h
@@ -205,6 +205,9 @@
int vfio_kvm_device_add_fd(int fd, Error **errp);
int vfio_kvm_device_del_fd(int fd, Error **errp);
+int vfio_cpr_register_container(VFIOContainerBase *bcontainer, Error **errp);
+void vfio_cpr_unregister_container(VFIOContainerBase *bcontainer);
+
extern const MemoryRegionOps vfio_region_ops;
typedef QLIST_HEAD(VFIOGroupList, VFIOGroup) VFIOGroupList;
typedef QLIST_HEAD(VFIODeviceList, VFIODevice) VFIODeviceList;
diff --git a/include/hw/vfio/vfio-container-base.h b/include/hw/vfio/vfio-container-base.h
index b2813b0..3582d5f 100644
--- a/include/hw/vfio/vfio-container-base.h
+++ b/include/hw/vfio/vfio-container-base.h
@@ -49,6 +49,7 @@
QLIST_ENTRY(VFIOContainerBase) next;
QLIST_HEAD(, VFIODevice) device_list;
GList *iova_ranges;
+ NotifierWithReturn cpr_reboot_notifier;
} VFIOContainerBase;
typedef struct VFIOGuestIOMMU {
diff --git a/include/hw/virtio/virtio-gpu.h b/include/hw/virtio/virtio-gpu.h
index b28e7ef..ed44cda 100644
--- a/include/hw/virtio/virtio-gpu.h
+++ b/include/hw/virtio/virtio-gpu.h
@@ -81,6 +81,7 @@
uint32_t resource_id;
struct virtio_gpu_update_cursor cursor;
QEMUCursor *current_cursor;
+ struct virtio_gpu_framebuffer fb;
};
struct virtio_gpu_requested_state {
diff --git a/include/hw/virtio/virtio-net.h b/include/hw/virtio/virtio-net.h
index eaee8f4..060c23c 100644
--- a/include/hw/virtio/virtio-net.h
+++ b/include/hw/virtio/virtio-net.h
@@ -225,6 +225,8 @@
VirtioNetRssData rss_data;
struct NetRxPkt *rx_pkt;
struct EBPFRSSContext ebpf_rss;
+ uint32_t nr_ebpf_rss_fds;
+ char **ebpf_rss_fds;
};
size_t virtio_net_handle_ctrl_iov(VirtIODevice *vdev,
diff --git a/include/migration/client-options.h b/include/migration/client-options.h
new file mode 100644
index 0000000..59f4b55
--- /dev/null
+++ b/include/migration/client-options.h
@@ -0,0 +1,25 @@
+/*
+ * QEMU public migration capabilities
+ *
+ * Copyright (c) 2012-2023 Red Hat Inc
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef QEMU_MIGRATION_CLIENT_OPTIONS_H
+#define QEMU_MIGRATION_CLIENT_OPTIONS_H
+
+/* capabilities */
+
+bool migrate_background_snapshot(void);
+bool migrate_dirty_limit(void);
+bool migrate_postcopy_ram(void);
+bool migrate_switchover_ack(void);
+
+/* parameters */
+
+MigMode migrate_mode(void);
+uint64_t migrate_vcpu_dirty_limit_period(void);
+
+#endif
diff --git a/include/migration/misc.h b/include/migration/misc.h
index 5d1aa59..c9e200f 100644
--- a/include/migration/misc.h
+++ b/include/migration/misc.h
@@ -17,6 +17,7 @@
#include "qemu/notify.h"
#include "qapi/qapi-types-migration.h"
#include "qapi/qapi-types-net.h"
+#include "migration/client-options.h"
/* migration/ram.c */
@@ -59,8 +60,10 @@
void migration_object_init(void);
void migration_shutdown(void);
bool migration_is_idle(void);
-bool migration_is_active(MigrationState *);
-bool migrate_mode_is_cpr(MigrationState *);
+bool migration_is_active(void);
+bool migration_is_device(void);
+bool migration_thread_is_self(void);
+bool migration_is_setup_or_active(void);
typedef enum MigrationEventType {
MIG_EVENT_PRECOPY_SETUP,
@@ -99,16 +102,15 @@
MigrationNotifyFunc func, MigMode mode);
void migration_remove_notifier(NotifierWithReturn *notify);
-int migration_call_notifiers(MigrationState *s, MigrationEventType type,
- Error **errp);
-bool migration_in_setup(MigrationState *);
-bool migration_has_finished(MigrationState *);
-bool migration_has_failed(MigrationState *);
-/* ...and after the device transmission */
+bool migration_is_running(void);
+void migration_file_set_error(int err);
+
/* True if incoming migration entered POSTCOPY_INCOMING_DISCARD */
bool migration_in_incoming_postcopy(void);
+
/* True if incoming migration entered POSTCOPY_INCOMING_ADVISE */
bool migration_incoming_postcopy_advised(void);
+
/* True if background snapshot is active */
bool migration_in_bg_snapshot(void);
diff --git a/include/migration/register.h b/include/migration/register.h
index 9ab1f79..d7b70a8 100644
--- a/include/migration/register.h
+++ b/include/migration/register.h
@@ -16,30 +16,130 @@
#include "hw/vmstate-if.h"
+/**
+ * struct SaveVMHandlers: handler structure to finely control
+ * migration of complex subsystems and devices, such as RAM, block and
+ * VFIO.
+ */
typedef struct SaveVMHandlers {
- /* This runs inside the BQL. */
- SaveStateHandler *save_state;
- /*
- * save_prepare is called early, even before migration starts, and can be
- * used to perform early checks.
+ /* The following handlers run inside the BQL. */
+
+ /**
+ * @save_state
+ *
+ * Saves state section on the source using the latest state format
+ * version.
+ *
+ * Legacy method. Should be deprecated when all users are ported
+ * to VMStateDescription.
+ *
+ * @f: QEMUFile where to send the data
+ * @opaque: data pointer passed to register_savevm_live()
+ */
+ void (*save_state)(QEMUFile *f, void *opaque);
+
+ /**
+ * @save_prepare
+ *
+ * Called early, even before migration starts, and can be used to
+ * perform early checks.
+ *
+ * @opaque: data pointer passed to register_savevm_live()
+ * @errp: pointer to Error*, to store an error if it happens.
+ *
+ * Returns zero to indicate success and negative for error
*/
int (*save_prepare)(void *opaque, Error **errp);
+
+ /**
+ * @save_setup
+ *
+ * Initializes the data structures on the source and transmits
+ * first section containing information on the device
+ *
+ * @f: QEMUFile where to send the data
+ * @opaque: data pointer passed to register_savevm_live()
+ *
+ * Returns zero to indicate success and negative for error
+ */
int (*save_setup)(QEMUFile *f, void *opaque);
+
+ /**
+ * @save_cleanup
+ *
+ * Uninitializes the data structures on the source
+ *
+ * @opaque: data pointer passed to register_savevm_live()
+ */
void (*save_cleanup)(void *opaque);
+
+ /**
+ * @save_live_complete_postcopy
+ *
+ * Called at the end of postcopy for all postcopyable devices.
+ *
+ * @f: QEMUFile where to send the data
+ * @opaque: data pointer passed to register_savevm_live()
+ *
+ * Returns zero to indicate success and negative for error
+ */
int (*save_live_complete_postcopy)(QEMUFile *f, void *opaque);
+
+ /**
+ * @save_live_complete_precopy
+ *
+ * Transmits the last section for the device containing any
+ * remaining data at the end of a precopy phase. When postcopy is
+ * enabled, devices that support postcopy will skip this step,
+ * where the final data will be flushed at the end of postcopy via
+ * @save_live_complete_postcopy instead.
+ *
+ * @f: QEMUFile where to send the data
+ * @opaque: data pointer passed to register_savevm_live()
+ *
+ * Returns zero to indicate success and negative for error
+ */
int (*save_live_complete_precopy)(QEMUFile *f, void *opaque);
/* This runs both outside and inside the BQL. */
+
+ /**
+ * @is_active
+ *
+ * Will skip a state section if not active
+ *
+ * @opaque: data pointer passed to register_savevm_live()
+ *
+ * Returns true if state section is active else false
+ */
bool (*is_active)(void *opaque);
+
+ /**
+ * @has_postcopy
+ *
+ * Checks if a device supports postcopy
+ *
+ * @opaque: data pointer passed to register_savevm_live()
+ *
+ * Returns true for postcopy support else false
+ */
bool (*has_postcopy)(void *opaque);
- /* is_active_iterate
- * If it is not NULL then qemu_savevm_state_iterate will skip iteration if
- * it returns false. For example, it is needed for only-postcopy-states,
- * which needs to be handled by qemu_savevm_state_setup and
- * qemu_savevm_state_pending, but do not need iterations until not in
- * postcopy stage.
+ /**
+ * @is_active_iterate
+ *
+ * As #SaveVMHandlers.is_active(), will skip an inactive state
+ * section in qemu_savevm_state_iterate.
+ *
+ * For example, it is needed for only-postcopy-states, which needs
+ * to be handled by qemu_savevm_state_setup() and
+ * qemu_savevm_state_pending(), but do not need iterations until
+ * not in postcopy stage.
+ *
+ * @opaque: data pointer passed to register_savevm_live()
+ *
+ * Returns true if state section is active else false
*/
bool (*is_active_iterate)(void *opaque);
@@ -48,44 +148,155 @@
* use data that is local to the migration thread or protected
* by other locks.
*/
+
+ /**
+ * @save_live_iterate
+ *
+ * Should send a chunk of data until the point that stream
+ * bandwidth limits tell it to stop. Each call generates one
+ * section.
+ *
+ * @f: QEMUFile where to send the data
+ * @opaque: data pointer passed to register_savevm_live()
+ *
+ * Returns 0 to indicate that there is still more data to send,
+ * 1 that there is no more data to send and
+ * negative to indicate an error.
+ */
int (*save_live_iterate)(QEMUFile *f, void *opaque);
/* This runs outside the BQL! */
- /* Note for save_live_pending:
- * must_precopy:
- * - must be migrated in precopy or in stopped state
- * - i.e. must be migrated before target start
+
+ /**
+ * @state_pending_estimate
*
- * can_postcopy:
- * - can migrate in postcopy or in stopped state
- * - i.e. can migrate after target start
- * - some can also be migrated during precopy (RAM)
- * - some must be migrated after source stops (block-dirty-bitmap)
+ * This estimates the remaining data to transfer
*
- * Sum of can_postcopy and must_postcopy is the whole amount of
+ * Sum of @can_postcopy and @must_postcopy is the whole amount of
* pending data.
+ *
+ * @opaque: data pointer passed to register_savevm_live()
+ * @must_precopy: amount of data that must be migrated in precopy
+ * or in stopped state, i.e. that must be migrated
+ * before target start.
+ * @can_postcopy: amount of data that can be migrated in postcopy
+ * or in stopped state, i.e. after target start.
+ * Some can also be migrated during precopy (RAM).
+ * Some must be migrated after source stops
+ * (block-dirty-bitmap)
*/
- /* This estimates the remaining data to transfer */
void (*state_pending_estimate)(void *opaque, uint64_t *must_precopy,
uint64_t *can_postcopy);
- /* This calculate the exact remaining data to transfer */
+
+ /**
+ * @state_pending_exact
+ *
+ * This calculates the exact remaining data to transfer
+ *
+ * Sum of @can_postcopy and @must_postcopy is the whole amount of
+ * pending data.
+ *
+ * @opaque: data pointer passed to register_savevm_live()
+ * @must_precopy: amount of data that must be migrated in precopy
+ * or in stopped state, i.e. that must be migrated
+ * before target start.
+ * @can_postcopy: amount of data that can be migrated in postcopy
+ * or in stopped state, i.e. after target start.
+ * Some can also be migrated during precopy (RAM).
+ * Some must be migrated after source stops
+ * (block-dirty-bitmap)
+ */
void (*state_pending_exact)(void *opaque, uint64_t *must_precopy,
uint64_t *can_postcopy);
- LoadStateHandler *load_state;
+
+ /**
+ * @load_state
+ *
+ * Load sections generated by any of the save functions that
+ * generate sections.
+ *
+ * Legacy method. Should be deprecated when all users are ported
+ * to VMStateDescription.
+ *
+ * @f: QEMUFile where to receive the data
+ * @opaque: data pointer passed to register_savevm_live()
+ * @version_id: the maximum version_id supported
+ *
+ * Returns zero to indicate success and negative for error
+ */
+ int (*load_state)(QEMUFile *f, void *opaque, int version_id);
+
+ /**
+ * @load_setup
+ *
+ * Initializes the data structures on the destination.
+ *
+ * @f: QEMUFile where to receive the data
+ * @opaque: data pointer passed to register_savevm_live()
+ *
+ * Returns zero to indicate success and negative for error
+ */
int (*load_setup)(QEMUFile *f, void *opaque);
+
+ /**
+ * @load_cleanup
+ *
+ * Uninitializes the data structures on the destination.
+ *
+ * @opaque: data pointer passed to register_savevm_live()
+ *
+ * Returns zero to indicate success and negative for error
+ */
int (*load_cleanup)(void *opaque);
- /* Called when postcopy migration wants to resume from failure */
+
+ /**
+ * @resume_prepare
+ *
+ * Called when postcopy migration wants to resume from failure
+ *
+ * @s: Current migration state
+ * @opaque: data pointer passed to register_savevm_live()
+ *
+ * Returns zero to indicate success and negative for error
+ */
int (*resume_prepare)(MigrationState *s, void *opaque);
- /* Checks if switchover ack should be used. Called only in dest */
+
+ /**
+ * @switchover_ack_needed
+ *
+ * Checks if switchover ack should be used. Called only on
+ * destination.
+ *
+ * @opaque: data pointer passed to register_savevm_live()
+ *
+ * Returns true if switchover ack should be used and false
+ * otherwise
+ */
bool (*switchover_ack_needed)(void *opaque);
} SaveVMHandlers;
+/**
+ * register_savevm_live: Register a set of custom migration handlers
+ *
+ * @idstr: state section identifier
+ * @instance_id: instance id
+ * @version_id: version id supported
+ * @ops: SaveVMHandlers structure
+ * @opaque: data pointer passed to SaveVMHandlers handlers
+ */
int register_savevm_live(const char *idstr,
uint32_t instance_id,
int version_id,
const SaveVMHandlers *ops,
void *opaque);
+/**
+ * unregister_savevm: Unregister custom migration handlers
+ *
+ * @obj: object associated with state section
+ * @idstr: state section identifier
+ * @opaque: data pointer passed to register_savevm_live()
+ */
void unregister_savevm(VMStateIf *obj, const char *idstr, void *opaque);
#endif
diff --git a/include/qapi/error.h b/include/qapi/error.h
index f21a231..71f8fb2 100644
--- a/include/qapi/error.h
+++ b/include/qapi/error.h
@@ -207,7 +207,7 @@
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
- * - It should not be passed to error_prepend() or
+ * - It should not be passed to error_prepend(), error_vprepend(), or
* error_append_hint(), because that doesn't work with &error_fatal.
* ERRP_GUARD() lifts these restrictions.
*
diff --git a/include/qemu/help-texts.h b/include/qemu/help-texts.h
index d0359f8..353ab2a 100644
--- a/include/qemu/help-texts.h
+++ b/include/qemu/help-texts.h
@@ -2,7 +2,7 @@
#define QEMU_HELP_TEXTS_H
/* Copyright string for -version arguments, About dialogs, etc */
-#define QEMU_COPYRIGHT "Copyright (c) 2003-2023 " \
+#define QEMU_COPYRIGHT "Copyright (c) 2003-2024 " \
"Fabrice Bellard and the QEMU Project developers"
/* Bug reporting information for --help arguments, About dialogs, etc */
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index a028dba..50c277c 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -151,8 +151,6 @@
/*
* Function types
*/
-typedef void SaveStateHandler(QEMUFile *f, void *opaque);
-typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
typedef void (*qemu_irq_handler)(void *opaque, int n, int level);
#endif /* QEMU_TYPEDEFS_H */
diff --git a/io/channel-file.c b/io/channel-file.c
index d4706fa..a6ad777 100644
--- a/io/channel-file.c
+++ b/io/channel-file.c
@@ -242,11 +242,6 @@
{
QIOChannelFile *fioc = QIO_CHANNEL_FILE(ioc);
- if (qemu_fdatasync(fioc->fd) < 0) {
- error_setg_errno(errp, errno,
- "Unable to synchronize file data with storage device");
- return -1;
- }
if (qemu_close(fioc->fd) < 0) {
error_setg_errno(errp, errno,
"Unable to close file");
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 4dbca05..60cf55b 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -4204,7 +4204,14 @@
* may well have higher alignment requirements, fill locally and
* memcpy to the destination afterward.
*/
- struct target_elf_prpsinfo psinfo;
+ struct target_elf_prpsinfo psinfo = {
+ .pr_pid = getpid(),
+ .pr_ppid = getppid(),
+ .pr_pgrp = getpgrp(),
+ .pr_sid = getsid(0),
+ .pr_uid = getuid(),
+ .pr_gid = getgid(),
+ };
char *base_filename;
size_t len;
@@ -4217,13 +4224,6 @@
}
}
- psinfo.pr_pid = getpid();
- psinfo.pr_ppid = getppid();
- psinfo.pr_pgrp = getpgrp();
- psinfo.pr_sid = getsid(0);
- psinfo.pr_uid = getuid();
- psinfo.pr_gid = getgid();
-
base_filename = g_path_get_basename(ts->bprm->filename);
/*
* Using strncpy here is fine: at max-length,
@@ -4522,7 +4522,9 @@
ret = -errno;
mmap_unlock();
cpu_list_unlock();
- close(fd);
+ if (fd >= 0) {
+ close(fd);
+ }
return ret;
}
#endif /* USE_ELF_CORE_DUMP */
diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c
index 42ecb4b..92beb68 100644
--- a/linux-user/i386/cpu_loop.c
+++ b/linux-user/i386/cpu_loop.c
@@ -323,8 +323,8 @@
static void target_cpu_free(void *obj)
{
- CPUArchState *env = cpu_env(obj);
- target_munmap(env->gdt.base, sizeof(uint64_t) * TARGET_GDT_ENTRIES);
+ target_munmap(cpu_env(obj)->gdt.base,
+ sizeof(uint64_t) * TARGET_GDT_ENTRIES);
g_free(obj);
}
diff --git a/linux-user/ioctls.h b/linux-user/ioctls.h
index 071f7ca..1aec9d5 100644
--- a/linux-user/ioctls.h
+++ b/linux-user/ioctls.h
@@ -134,6 +134,12 @@
IOCTL(FICLONE, IOC_W, TYPE_INT)
IOCTL(FICLONERANGE, IOC_W, MK_PTR(MK_STRUCT(STRUCT_file_clone_range)))
#endif
+#ifdef FIFREEZE
+ IOCTL(FIFREEZE, IOC_W | IOC_R, TYPE_INT)
+#endif
+#ifdef FITHAW
+ IOCTL(FITHAW, IOC_W | IOC_R, TYPE_INT)
+#endif
IOCTL(FIGETBSZ, IOC_R, MK_PTR(TYPE_LONG))
#ifdef CONFIG_FIEMAP
diff --git a/linux-user/signal.c b/linux-user/signal.c
index cc7dd78..1aebf3f 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -623,7 +623,6 @@
void force_sig(int sig)
{
CPUState *cpu = thread_cpu;
- CPUArchState *env = cpu_env(cpu);
target_siginfo_t info = {};
info.si_signo = sig;
@@ -631,7 +630,7 @@
info.si_code = TARGET_SI_KERNEL;
info._sifields._kill._pid = 0;
info._sifields._kill._uid = 0;
- queue_signal(env, info.si_signo, QEMU_SI_KILL, &info);
+ queue_signal(cpu_env(cpu), info.si_signo, QEMU_SI_KILL, &info);
}
/*
@@ -641,14 +640,13 @@
void force_sig_fault(int sig, int code, abi_ulong addr)
{
CPUState *cpu = thread_cpu;
- CPUArchState *env = cpu_env(cpu);
target_siginfo_t info = {};
info.si_signo = sig;
info.si_errno = 0;
info.si_code = code;
info._sifields._sigfault._addr = addr;
- queue_signal(env, sig, QEMU_SI_FAULT, &info);
+ queue_signal(cpu_env(cpu), sig, QEMU_SI_FAULT, &info);
}
/* Force a SIGSEGV if we couldn't write to memory trying to set
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 597bdf0..e12d969 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -6450,16 +6450,28 @@
case PR_SET_NO_NEW_PRIVS:
case PR_GET_IO_FLUSHER:
case PR_SET_IO_FLUSHER:
+ case PR_SET_CHILD_SUBREAPER:
+ case PR_GET_SPECULATION_CTRL:
+ case PR_SET_SPECULATION_CTRL:
/* Some prctl options have no pointer arguments and we can pass on. */
return get_errno(prctl(option, arg2, arg3, arg4, arg5));
case PR_GET_CHILD_SUBREAPER:
- case PR_SET_CHILD_SUBREAPER:
- case PR_GET_SPECULATION_CTRL:
- case PR_SET_SPECULATION_CTRL:
+ {
+ int val;
+ ret = get_errno(prctl(PR_GET_CHILD_SUBREAPER, &val,
+ arg3, arg4, arg5));
+ if (!is_error(ret) && put_user_s32(val, arg2)) {
+ return -TARGET_EFAULT;
+ }
+ return ret;
+ }
+
case PR_GET_TID_ADDRESS:
- /* TODO */
- return -TARGET_EINVAL;
+ {
+ TaskState *ts = env_cpu(env)->opaque;
+ return put_user_ual(ts->child_tidptr, arg2);
+ }
case PR_GET_FPEXC:
case PR_SET_FPEXC:
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 77ba343..744fda5 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -943,6 +943,9 @@
#define TARGET_FICLONE TARGET_IOW(0x94, 9, abi_int)
#define TARGET_FICLONERANGE TARGET_IOW(0x94, 13, struct file_clone_range)
+#define TARGET_FIFREEZE TARGET_IOWR('X', 119, abi_int)
+#define TARGET_FITHAW TARGET_IOWR('X', 120, abi_int)
+
/*
* Note that the ioctl numbers for FS_IOC_<GET|SET><FLAGS|VERSION>
* claim type "long" but the actual type used by the kernel is "int".
diff --git a/meson.build b/meson.build
index f9dbe76..b375248 100644
--- a/meson.build
+++ b/meson.build
@@ -66,7 +66,7 @@
cxx = meson.get_compiler('cpp')
endif
if host_os == 'darwin' and \
- add_languages('objc', required: get_option('cocoa'), native: false)
+ add_languages('objc', required: true, native: false)
all_languages += ['objc']
objc = meson.get_compiler('objc')
endif
@@ -2006,19 +2006,23 @@
endif
# libbpf
-libbpf = dependency('libbpf', required: get_option('bpf'), method: 'pkg-config')
+bpf_version = '1.1.0'
+libbpf = dependency('libbpf', version: '>=' + bpf_version, required: get_option('bpf'), method: 'pkg-config')
if libbpf.found() and not cc.links('''
#include <bpf/libbpf.h>
+ #include <linux/bpf.h>
int main(void)
{
+ // check flag availability
+ int flag = BPF_F_MMAPABLE;
bpf_object__destroy_skeleton(NULL);
return 0;
}''', dependencies: libbpf)
libbpf = not_found
if get_option('bpf').enabled()
- error('libbpf skeleton test failed')
+ error('libbpf skeleton/mmaping test failed')
else
- warning('libbpf skeleton test failed, disabling')
+ warning('libbpf skeleton/mmaping test failed, disabling')
endif
endif
@@ -3808,6 +3812,7 @@
entitlement = find_program('scripts/entitlement.sh')
endif
+traceable = []
emulators = {}
foreach target : target_dirs
config_target = config_target_mak[target]
@@ -3976,29 +3981,11 @@
emulators += {exe['name']: emulator}
endif
- if stap.found()
- foreach stp: [
- {'ext': '.stp-build', 'fmt': 'stap', 'bin': meson.current_build_dir() / exe['name'], 'install': false},
- {'ext': '.stp', 'fmt': 'stap', 'bin': get_option('prefix') / get_option('bindir') / exe['name'], 'install': true},
- {'ext': '-simpletrace.stp', 'fmt': 'simpletrace-stap', 'bin': '', 'install': true},
- {'ext': '-log.stp', 'fmt': 'log-stap', 'bin': '', 'install': true},
- ]
- custom_target(exe['name'] + stp['ext'],
- input: trace_events_all,
- output: exe['name'] + stp['ext'],
- install: stp['install'],
- install_dir: get_option('datadir') / 'systemtap/tapset',
- command: [
- tracetool, '--group=all', '--format=' + stp['fmt'],
- '--binary=' + stp['bin'],
- '--target-name=' + target_name,
- '--target-type=' + target_type,
- '--probe-prefix=qemu.' + target_type + '.' + target_name,
- '@INPUT@', '@OUTPUT@'
- ],
- depend_files: tracetool_depends)
- endforeach
- endif
+ traceable += [{
+ 'exe': exe['name'],
+ 'probe-prefix': 'qemu.' + target_type + '.' + target_name,
+ }]
+
endforeach
endforeach
@@ -4033,6 +4020,14 @@
install: true)
subdir('storage-daemon')
+
+ foreach exe: [ 'qemu-img', 'qemu-io', 'qemu-nbd', 'qemu-storage-daemon']
+ traceable += [{
+ 'exe': exe,
+ 'probe-prefix': 'qemu.' + exe.substring(5).replace('-', '_')
+ }]
+ endforeach
+
subdir('contrib/rdmacm-mux')
subdir('contrib/elf2dmp')
@@ -4065,6 +4060,32 @@
endif
endif
+if stap.found()
+ foreach t: traceable
+ foreach stp: [
+ {'ext': '.stp-build', 'fmt': 'stap', 'bin': meson.current_build_dir() / t['exe'], 'install': false},
+ {'ext': '.stp', 'fmt': 'stap', 'bin': get_option('prefix') / get_option('bindir') / t['exe'], 'install': true},
+ {'ext': '-simpletrace.stp', 'fmt': 'simpletrace-stap', 'bin': '', 'install': true},
+ {'ext': '-log.stp', 'fmt': 'log-stap', 'bin': '', 'install': true},
+ ]
+ cmd = [
+ tracetool, '--group=all', '--format=' + stp['fmt'],
+ '--binary=' + stp['bin'],
+ '--probe-prefix=' + t['probe-prefix'],
+ '@INPUT@', '@OUTPUT@'
+ ]
+
+ custom_target(t['exe'] + stp['ext'],
+ input: trace_events_all,
+ output: t['exe'] + stp['ext'],
+ install: stp['install'],
+ install_dir: get_option('datadir') / 'systemtap/tapset',
+ command: cmd,
+ depend_files: tracetool_depends)
+ endforeach
+ endforeach
+endif
+
subdir('scripts')
subdir('tools')
subdir('pc-bios')
diff --git a/migration/colo.c b/migration/colo.c
index 315e31f..84632a6 100644
--- a/migration/colo.c
+++ b/migration/colo.c
@@ -63,9 +63,9 @@
return runstate_check(RUN_STATE_COLO) || !runstate_is_running();
}
-static void colo_checkpoint_notify(void *opaque)
+static void colo_checkpoint_notify(void)
{
- MigrationState *s = opaque;
+ MigrationState *s = migrate_get_current();
int64_t next_notify_time;
qemu_event_set(&s->colo_checkpoint_event);
@@ -74,10 +74,15 @@
timer_mod(s->colo_delay_timer, next_notify_time);
}
+static void colo_checkpoint_notify_timer(void *opaque)
+{
+ colo_checkpoint_notify();
+}
+
void colo_checkpoint_delay_set(void)
{
if (migration_in_colo_state()) {
- colo_checkpoint_notify(migrate_get_current());
+ colo_checkpoint_notify();
}
}
@@ -162,7 +167,7 @@
* kick COLO thread which might wait at
* qemu_sem_wait(&s->colo_checkpoint_sem).
*/
- colo_checkpoint_notify(s);
+ colo_checkpoint_notify();
/*
* Wake up COLO thread which may blocked in recv() or send(),
@@ -518,7 +523,7 @@
static void colo_compare_notify_checkpoint(Notifier *notifier, void *data)
{
- colo_checkpoint_notify(data);
+ colo_checkpoint_notify();
}
static void colo_process_checkpoint(MigrationState *s)
@@ -642,7 +647,7 @@
bql_unlock();
qemu_event_init(&s->colo_checkpoint_event, false);
s->colo_delay_timer = timer_new_ms(QEMU_CLOCK_HOST,
- colo_checkpoint_notify, s);
+ colo_checkpoint_notify_timer, NULL);
qemu_sem_init(&s->colo_exit_sem, 0);
colo_process_checkpoint(s);
diff --git a/migration/file.c b/migration/file.c
index 164b079..b0b963e 100644
--- a/migration/file.c
+++ b/migration/file.c
@@ -159,7 +159,7 @@
int file_write_ramblock_iov(QIOChannel *ioc, const struct iovec *iov,
int niov, RAMBlock *block, Error **errp)
{
- ssize_t ret = -1;
+ ssize_t ret = 0;
int i, slice_idx, slice_num;
uintptr_t base, next, offset;
size_t len;
@@ -191,7 +191,7 @@
*/
offset = (uintptr_t) iov[slice_idx].iov_base - (uintptr_t) block->host;
if (offset >= block->used_length) {
- error_setg(errp, "offset " RAM_ADDR_FMT
+ error_setg(errp, "offset %" PRIxPTR
"outside of ramblock %s range", offset, block->idstr);
ret = -1;
break;
diff --git a/migration/meson.build b/migration/meson.build
index 92b1cc4..1eeb915 100644
--- a/migration/meson.build
+++ b/migration/meson.build
@@ -22,6 +22,7 @@
'migration.c',
'multifd.c',
'multifd-zlib.c',
+ 'multifd-zero-page.c',
'ram-compress.c',
'options.c',
'postcopy-ram.c',
diff --git a/migration/migration-hmp-cmds.c b/migration/migration-hmp-cmds.c
index 99b49df..7e96ae6 100644
--- a/migration/migration-hmp-cmds.c
+++ b/migration/migration-hmp-cmds.c
@@ -344,6 +344,11 @@
monitor_printf(mon, "%s: %s\n",
MigrationParameter_str(MIGRATION_PARAMETER_MULTIFD_COMPRESSION),
MultiFDCompression_str(params->multifd_compression));
+ assert(params->has_zero_page_detection);
+ monitor_printf(mon, "%s: %s\n",
+ MigrationParameter_str(MIGRATION_PARAMETER_ZERO_PAGE_DETECTION),
+ qapi_enum_lookup(&ZeroPageDetection_lookup,
+ params->zero_page_detection));
monitor_printf(mon, "%s: %" PRIu64 " bytes\n",
MigrationParameter_str(MIGRATION_PARAMETER_XBZRLE_CACHE_SIZE),
params->xbzrle_cache_size);
@@ -634,6 +639,10 @@
p->has_multifd_zstd_level = true;
visit_type_uint8(v, param, &p->multifd_zstd_level, &err);
break;
+ case MIGRATION_PARAMETER_ZERO_PAGE_DETECTION:
+ p->has_zero_page_detection = true;
+ visit_type_ZeroPageDetection(v, param, &p->zero_page_detection, &err);
+ break;
case MIGRATION_PARAMETER_XBZRLE_CACHE_SIZE:
p->has_xbzrle_cache_size = true;
if (!visit_type_size(v, param, &cache_size, &err)) {
diff --git a/migration/migration.c b/migration/migration.c
index a49fcd5..644e073 100644
--- a/migration/migration.c
+++ b/migration/migration.c
@@ -1081,9 +1081,11 @@
* Return true if we're already in the middle of a migration
* (i.e. any of the active or setup states)
*/
-bool migration_is_setup_or_active(int state)
+bool migration_is_setup_or_active(void)
{
- switch (state) {
+ MigrationState *s = current_migration;
+
+ switch (s->state) {
case MIGRATION_STATUS_ACTIVE:
case MIGRATION_STATUS_POSTCOPY_ACTIVE:
case MIGRATION_STATUS_POSTCOPY_PAUSED:
@@ -1101,9 +1103,11 @@
}
}
-bool migration_is_running(int state)
+bool migration_is_running(void)
{
- switch (state) {
+ MigrationState *s = current_migration;
+
+ switch (s->state) {
case MIGRATION_STATUS_ACTIVE:
case MIGRATION_STATUS_POSTCOPY_ACTIVE:
case MIGRATION_STATUS_POSTCOPY_PAUSED:
@@ -1404,7 +1408,7 @@
qemu_fclose(tmp);
}
- assert(!migration_is_active(s));
+ assert(!migration_is_active());
if (s->state == MIGRATION_STATUS_CANCELLING) {
migrate_set_state(&s->state, MIGRATION_STATUS_CANCELLING,
@@ -1475,7 +1479,7 @@
do {
old_state = s->state;
- if (!migration_is_running(old_state)) {
+ if (!migration_is_running()) {
break;
}
/* If the migration is paused, kick it out of the pause */
@@ -1544,16 +1548,6 @@
return ret;
}
-bool migration_in_setup(MigrationState *s)
-{
- return s->state == MIGRATION_STATUS_SETUP;
-}
-
-bool migration_has_finished(MigrationState *s)
-{
- return s->state == MIGRATION_STATUS_COMPLETED;
-}
-
bool migration_has_failed(MigrationState *s)
{
return (s->state == MIGRATION_STATUS_CANCELLED ||
@@ -1601,10 +1595,8 @@
bool migration_in_bg_snapshot(void)
{
- MigrationState *s = migrate_get_current();
-
return migrate_background_snapshot() &&
- migration_is_setup_or_active(s->state);
+ migration_is_setup_or_active();
}
bool migration_is_idle(void)
@@ -1637,12 +1629,28 @@
return false;
}
-bool migration_is_active(MigrationState *s)
+bool migration_is_active(void)
{
+ MigrationState *s = current_migration;
+
return (s->state == MIGRATION_STATUS_ACTIVE ||
s->state == MIGRATION_STATUS_POSTCOPY_ACTIVE);
}
+bool migration_is_device(void)
+{
+ MigrationState *s = current_migration;
+
+ return s->state == MIGRATION_STATUS_DEVICE;
+}
+
+bool migration_thread_is_self(void)
+{
+ MigrationState *s = current_migration;
+
+ return qemu_thread_is_self(&s->thread);
+}
+
bool migrate_mode_is_cpr(MigrationState *s)
{
return s->parameters.mode == MIG_MODE_CPR_REBOOT;
@@ -1960,7 +1968,7 @@
return true;
}
- if (migration_is_running(s->state)) {
+ if (migration_is_running()) {
error_setg(errp, QERR_MIGRATION_ACTIVE);
return false;
}
@@ -2297,7 +2305,7 @@
trace_source_return_path_thread_entry();
rcu_register_thread();
- while (migration_is_setup_or_active(ms->state)) {
+ while (migration_is_setup_or_active()) {
trace_source_return_path_thread_loop_top();
header_type = qemu_get_be16(rp);
@@ -3020,6 +3028,17 @@
}
}
+void migration_file_set_error(int err)
+{
+ MigrationState *s = current_migration;
+
+ WITH_QEMU_LOCK_GUARD(&s->qemu_file_lock) {
+ if (s->to_dst_file) {
+ qemu_file_set_error(s->to_dst_file, err);
+ }
+ }
+}
+
static MigThrError migration_detect_error(MigrationState *s)
{
int ret;
@@ -3461,7 +3480,7 @@
trace_migration_thread_setup_complete();
- while (migration_is_active(s)) {
+ while (migration_is_active()) {
if (urgent || !migration_rate_exceeded(s->to_dst_file)) {
MigIterateState iter_state = migration_iteration_run(s);
if (iter_state == MIG_ITERATE_SKIP) {
@@ -3607,7 +3626,7 @@
migration_bh_schedule(bg_migration_vm_start_bh, s);
bql_unlock();
- while (migration_is_active(s)) {
+ while (migration_is_active()) {
MigIterateState iter_state = bg_migration_iteration_run(s);
if (iter_state == MIG_ITERATE_SKIP) {
continue;
diff --git a/migration/migration.h b/migration/migration.h
index 65c0b61..8045e39 100644
--- a/migration/migration.h
+++ b/migration/migration.h
@@ -26,6 +26,7 @@
#include "qom/object.h"
#include "postcopy-ram.h"
#include "sysemu/runstate.h"
+#include "migration/misc.h"
struct PostcopyBlocktimeContext;
@@ -479,8 +480,8 @@
void migrate_fd_connect(MigrationState *s, Error *error_in);
-bool migration_is_setup_or_active(int state);
-bool migration_is_running(int state);
+int migration_call_notifiers(MigrationState *s, MigrationEventType type,
+ Error **errp);
int migrate_init(MigrationState *s, Error **errp);
bool migration_is_blocked(Error **errp);
@@ -488,6 +489,8 @@
bool migration_in_postcopy(void);
bool migration_postcopy_is_alive(int state);
MigrationState *migrate_get_current(void);
+bool migration_has_failed(MigrationState *);
+bool migrate_mode_is_cpr(MigrationState *);
uint64_t ram_get_total_transferred_pages(void);
diff --git a/migration/multifd-zero-page.c b/migration/multifd-zero-page.c
new file mode 100644
index 0000000..1ba38be
--- /dev/null
+++ b/migration/multifd-zero-page.c
@@ -0,0 +1,87 @@
+/*
+ * Multifd zero page detection implementation.
+ *
+ * Copyright (c) 2024 Bytedance Inc
+ *
+ * Authors:
+ * Hao Xiang <hao.xiang@bytedance.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/cutils.h"
+#include "exec/ramblock.h"
+#include "migration.h"
+#include "multifd.h"
+#include "options.h"
+#include "ram.h"
+
+static bool multifd_zero_page_enabled(void)
+{
+ return migrate_zero_page_detection() == ZERO_PAGE_DETECTION_MULTIFD;
+}
+
+static void swap_page_offset(ram_addr_t *pages_offset, int a, int b)
+{
+ ram_addr_t temp;
+
+ if (a == b) {
+ return;
+ }
+
+ temp = pages_offset[a];
+ pages_offset[a] = pages_offset[b];
+ pages_offset[b] = temp;
+}
+
+/**
+ * multifd_send_zero_page_detect: Perform zero page detection on all pages.
+ *
+ * Sorts normal pages before zero pages in p->pages->offset and updates
+ * p->pages->normal_num.
+ *
+ * @param p A pointer to the send params.
+ */
+void multifd_send_zero_page_detect(MultiFDSendParams *p)
+{
+ MultiFDPages_t *pages = p->pages;
+ RAMBlock *rb = pages->block;
+ int i = 0;
+ int j = pages->num - 1;
+
+ if (!multifd_zero_page_enabled()) {
+ pages->normal_num = pages->num;
+ return;
+ }
+
+ /*
+ * Sort the page offset array by moving all normal pages to
+ * the left and all zero pages to the right of the array.
+ */
+ while (i <= j) {
+ uint64_t offset = pages->offset[i];
+
+ if (!buffer_is_zero(rb->host + offset, p->page_size)) {
+ i++;
+ continue;
+ }
+
+ swap_page_offset(pages->offset, i, j);
+ ram_release_page(rb->idstr, offset);
+ j--;
+ }
+
+ pages->normal_num = i;
+}
+
+void multifd_recv_zero_page_process(MultiFDRecvParams *p)
+{
+ for (int i = 0; i < p->zero_num; i++) {
+ void *page = p->host + p->zero[i];
+ if (!buffer_is_zero(page, p->page_size)) {
+ memset(page, 0, p->page_size);
+ }
+ }
+}
diff --git a/migration/multifd-zlib.c b/migration/multifd-zlib.c
index 6120faa..99821cd 100644
--- a/migration/multifd-zlib.c
+++ b/migration/multifd-zlib.c
@@ -75,7 +75,7 @@
err_free_zbuff:
g_free(z->zbuff);
err_deflate_end:
- deflateEnd(&z->zs);
+ deflateEnd(zs);
err_free_z:
g_free(z);
error_setg(errp, "multifd %u: %s", p->id, err_msg);
@@ -123,13 +123,15 @@
int ret;
uint32_t i;
- multifd_send_prepare_header(p);
+ if (!multifd_send_prepare_common(p)) {
+ goto out;
+ }
- for (i = 0; i < pages->num; i++) {
+ for (i = 0; i < pages->normal_num; i++) {
uint32_t available = z->zbuff_len - out_size;
int flush = Z_NO_FLUSH;
- if (i == pages->num - 1) {
+ if (i == pages->normal_num - 1) {
flush = Z_SYNC_FLUSH;
}
@@ -172,10 +174,10 @@
p->iov[p->iovs_num].iov_len = out_size;
p->iovs_num++;
p->next_packet_size = out_size;
+
+out:
p->flags |= MULTIFD_FLAG_ZLIB;
-
multifd_send_fill_packet(p);
-
return 0;
}
@@ -261,6 +263,14 @@
p->id, flags, MULTIFD_FLAG_ZLIB);
return -1;
}
+
+ multifd_recv_zero_page_process(p);
+
+ if (!p->normal_num) {
+ assert(in_size == 0);
+ return 0;
+ }
+
ret = qio_channel_read_all(p->c, (void *)z->zbuff, in_size, errp);
if (ret != 0) {
@@ -310,6 +320,7 @@
p->id, out_size, expected_size);
return -1;
}
+
return 0;
}
diff --git a/migration/multifd-zstd.c b/migration/multifd-zstd.c
index cac2368..0211225 100644
--- a/migration/multifd-zstd.c
+++ b/migration/multifd-zstd.c
@@ -118,16 +118,18 @@
int ret;
uint32_t i;
- multifd_send_prepare_header(p);
+ if (!multifd_send_prepare_common(p)) {
+ goto out;
+ }
z->out.dst = z->zbuff;
z->out.size = z->zbuff_len;
z->out.pos = 0;
- for (i = 0; i < pages->num; i++) {
+ for (i = 0; i < pages->normal_num; i++) {
ZSTD_EndDirective flush = ZSTD_e_continue;
- if (i == pages->num - 1) {
+ if (i == pages->normal_num - 1) {
flush = ZSTD_e_flush;
}
z->in.src = p->pages->block->host + pages->offset[i];
@@ -161,10 +163,10 @@
p->iov[p->iovs_num].iov_len = z->out.pos;
p->iovs_num++;
p->next_packet_size = z->out.pos;
+
+out:
p->flags |= MULTIFD_FLAG_ZSTD;
-
multifd_send_fill_packet(p);
-
return 0;
}
@@ -257,6 +259,14 @@
p->id, flags, MULTIFD_FLAG_ZSTD);
return -1;
}
+
+ multifd_recv_zero_page_process(p);
+
+ if (!p->normal_num) {
+ assert(in_size == 0);
+ return 0;
+ }
+
ret = qio_channel_read_all(p->c, (void *)z->zbuff, in_size, errp);
if (ret != 0) {
diff --git a/migration/multifd.c b/migration/multifd.c
index d4a44da..0179422 100644
--- a/migration/multifd.c
+++ b/migration/multifd.c
@@ -11,6 +11,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/cutils.h"
#include "qemu/rcu.h"
#include "exec/target_page.h"
#include "sysemu/sysemu.h"
@@ -111,11 +112,16 @@
static void multifd_set_file_bitmap(MultiFDSendParams *p)
{
MultiFDPages_t *pages = p->pages;
+ uint32_t zero_num = p->pages->num - p->pages->normal_num;
assert(pages->block);
- for (int i = 0; i < p->pages->num; i++) {
- ramblock_set_file_bmap_atomic(pages->block, pages->offset[i]);
+ for (int i = 0; i < p->pages->normal_num; i++) {
+ ramblock_set_file_bmap_atomic(pages->block, pages->offset[i], true);
+ }
+
+ for (int i = p->pages->num; i < zero_num; i++) {
+ ramblock_set_file_bmap_atomic(pages->block, pages->offset[i], false);
}
}
@@ -153,13 +159,13 @@
{
MultiFDPages_t *pages = p->pages;
- for (int i = 0; i < pages->num; i++) {
+ for (int i = 0; i < pages->normal_num; i++) {
p->iov[p->iovs_num].iov_base = pages->block->host + pages->offset[i];
p->iov[p->iovs_num].iov_len = p->page_size;
p->iovs_num++;
}
- p->next_packet_size = pages->num * p->page_size;
+ p->next_packet_size = pages->normal_num * p->page_size;
}
/**
@@ -178,6 +184,8 @@
bool use_zero_copy_send = migrate_zero_copy_send();
int ret;
+ multifd_send_zero_page_detect(p);
+
if (!multifd_use_packets()) {
multifd_send_prepare_iovs(p);
multifd_set_file_bitmap(p);
@@ -261,6 +269,13 @@
p->id, flags, MULTIFD_FLAG_NOCOMP);
return -1;
}
+
+ multifd_recv_zero_page_process(p);
+
+ if (!p->normal_num) {
+ return 0;
+ }
+
for (int i = 0; i < p->normal_num; i++) {
p->iov[i].iov_base = p->host + p->normal[i];
p->iov[i].iov_len = p->page_size;
@@ -295,6 +310,7 @@
* overwritten later when reused.
*/
pages->num = 0;
+ pages->normal_num = 0;
pages->block = NULL;
}
@@ -386,11 +402,13 @@
MultiFDPacket_t *packet = p->packet;
MultiFDPages_t *pages = p->pages;
uint64_t packet_num;
+ uint32_t zero_num = pages->num - pages->normal_num;
int i;
packet->flags = cpu_to_be32(p->flags);
packet->pages_alloc = cpu_to_be32(p->pages->allocated);
- packet->normal_pages = cpu_to_be32(pages->num);
+ packet->normal_pages = cpu_to_be32(pages->normal_num);
+ packet->zero_pages = cpu_to_be32(zero_num);
packet->next_packet_size = cpu_to_be32(p->next_packet_size);
packet_num = qatomic_fetch_inc(&multifd_send_state->packet_num);
@@ -408,10 +426,11 @@
}
p->packets_sent++;
- p->total_normal_pages += pages->num;
+ p->total_normal_pages += pages->normal_num;
+ p->total_zero_pages += zero_num;
- trace_multifd_send(p->id, packet_num, pages->num, p->flags,
- p->next_packet_size);
+ trace_multifd_send(p->id, packet_num, pages->normal_num, zero_num,
+ p->flags, p->next_packet_size);
}
static int multifd_recv_unfill_packet(MultiFDRecvParams *p, Error **errp)
@@ -452,20 +471,29 @@
p->normal_num = be32_to_cpu(packet->normal_pages);
if (p->normal_num > packet->pages_alloc) {
error_setg(errp, "multifd: received packet "
- "with %u pages and expected maximum pages are %u",
+ "with %u normal pages and expected maximum pages are %u",
p->normal_num, packet->pages_alloc) ;
return -1;
}
+ p->zero_num = be32_to_cpu(packet->zero_pages);
+ if (p->zero_num > packet->pages_alloc - p->normal_num) {
+ error_setg(errp, "multifd: received packet "
+ "with %u zero pages and expected maximum zero pages are %u",
+ p->zero_num, packet->pages_alloc - p->normal_num) ;
+ return -1;
+ }
+
p->next_packet_size = be32_to_cpu(packet->next_packet_size);
p->packet_num = be64_to_cpu(packet->packet_num);
p->packets_recved++;
p->total_normal_pages += p->normal_num;
+ p->total_zero_pages += p->zero_num;
- trace_multifd_recv(p->id, p->packet_num, p->normal_num, p->flags,
- p->next_packet_size);
+ trace_multifd_recv(p->id, p->packet_num, p->normal_num, p->zero_num,
+ p->flags, p->next_packet_size);
- if (p->normal_num == 0) {
+ if (p->normal_num == 0 && p->zero_num == 0) {
return 0;
}
@@ -491,6 +519,18 @@
p->normal[i] = offset;
}
+ for (i = 0; i < p->zero_num; i++) {
+ uint64_t offset = be64_to_cpu(packet->offset[p->normal_num + i]);
+
+ if (offset > (p->block->used_length - p->page_size)) {
+ error_setg(errp, "multifd: offset too long %" PRIu64
+ " (max " RAM_ADDR_FMT ")",
+ offset, p->block->used_length);
+ return -1;
+ }
+ p->zero[i] = offset;
+ }
+
return 0;
}
@@ -710,16 +750,26 @@
if (p->c) {
migration_ioc_unregister_yank(p->c);
/*
- * An explicit close() on the channel here is normally not
- * required, but can be helpful for "file:" iochannels, where it
- * will include fdatasync() to make sure the data is flushed to the
- * disk backend.
+ * The object_unref() cannot guarantee the fd will always be
+ * released because finalize() of the iochannel is only
+ * triggered on the last reference and it's not guaranteed
+ * that we always hold the last refcount when reaching here.
*
- * The object_unref() cannot guarantee that because: (1) finalize()
- * of the iochannel is only triggered on the last reference, and
- * it's not guaranteed that we always hold the last refcount when
- * reaching here, and, (2) even if finalize() is invoked, it only
- * does a close(fd) without data flush.
+ * Closing the fd explicitly has the benefit that if there is any
+ * registered I/O handler callbacks on such fd, that will get a
+ * POLLNVAL event and will further trigger the cleanup to finally
+ * release the IOC.
+ *
+ * FIXME: It should logically be guaranteed that all multifd
+ * channels have no I/O handler callback registered when reaching
+ * here, because migration thread will wait for all multifd channel
+ * establishments to complete during setup. Since
+ * migrate_fd_cleanup() will be scheduled in main thread too, all
+ * previous callbacks should guarantee to be completed when
+ * reaching here. See multifd_send_state.channels_created and its
+ * usage. In the future, we could replace this with an assert
+ * making sure we're the last reference, or simply drop it if above
+ * is more clear to be justified.
*/
qio_channel_close(p->c, &error_abort);
object_unref(OBJECT(p->c));
@@ -908,6 +958,8 @@
stat64_add(&mig_stats.multifd_bytes,
p->next_packet_size + p->packet_len);
+ stat64_add(&mig_stats.normal_pages, pages->normal_num);
+ stat64_add(&mig_stats.zero_pages, pages->num - pages->normal_num);
multifd_pages_reset(p->pages);
p->next_packet_size = 0;
@@ -955,7 +1007,8 @@
rcu_unregister_thread();
migration_threads_remove(thread);
- trace_multifd_send_thread_end(p->id, p->packets_sent, p->total_normal_pages);
+ trace_multifd_send_thread_end(p->id, p->packets_sent, p->total_normal_pages,
+ p->total_zero_pages);
return NULL;
}
@@ -1306,6 +1359,8 @@
p->iov = NULL;
g_free(p->normal);
p->normal = NULL;
+ g_free(p->zero);
+ p->zero = NULL;
multifd_recv_state->ops->recv_cleanup(p);
}
@@ -1439,7 +1494,7 @@
flags = p->flags;
/* recv methods don't know how to handle the SYNC flag */
p->flags &= ~MULTIFD_FLAG_SYNC;
- has_data = !!p->normal_num;
+ has_data = p->normal_num || p->zero_num;
qemu_mutex_unlock(&p->mutex);
} else {
/*
@@ -1497,7 +1552,9 @@
}
rcu_unregister_thread();
- trace_multifd_recv_thread_end(p->id, p->packets_recved, p->total_normal_pages);
+ trace_multifd_recv_thread_end(p->id, p->packets_recved,
+ p->total_normal_pages,
+ p->total_zero_pages);
return NULL;
}
@@ -1549,6 +1606,7 @@
p->name = g_strdup_printf("multifdrecv_%d", i);
p->iov = g_new0(struct iovec, page_count);
p->normal = g_new0(ram_addr_t, page_count);
+ p->zero = g_new0(ram_addr_t, page_count);
p->page_count = page_count;
p->page_size = qemu_target_page_size();
}
@@ -1623,3 +1681,17 @@
QEMU_THREAD_JOINABLE);
qatomic_inc(&multifd_recv_state->count);
}
+
+bool multifd_send_prepare_common(MultiFDSendParams *p)
+{
+ multifd_send_zero_page_detect(p);
+
+ if (!p->pages->normal_num) {
+ p->next_packet_size = 0;
+ return false;
+ }
+
+ multifd_send_prepare_header(p);
+
+ return true;
+}
diff --git a/migration/multifd.h b/migration/multifd.h
index 7447c2b..c9d9b09 100644
--- a/migration/multifd.h
+++ b/migration/multifd.h
@@ -55,14 +55,24 @@
/* size of the next packet that contains pages */
uint32_t next_packet_size;
uint64_t packet_num;
- uint64_t unused[4]; /* Reserved for future use */
+ /* zero pages */
+ uint32_t zero_pages;
+ uint32_t unused32[1]; /* Reserved for future use */
+ uint64_t unused64[3]; /* Reserved for future use */
char ramblock[256];
+ /*
+ * This array contains the pointers to:
+ * - normal pages (initial normal_pages entries)
+ * - zero pages (following zero_pages entries)
+ */
uint64_t offset[];
} __attribute__((packed)) MultiFDPacket_t;
typedef struct {
/* number of used pages */
uint32_t num;
+ /* number of normal pages */
+ uint32_t normal_num;
/* number of allocated pages */
uint32_t allocated;
/* offset of each page */
@@ -136,6 +146,8 @@
uint64_t packets_sent;
/* non zero pages sent through this channel */
uint64_t total_normal_pages;
+ /* zero pages sent through this channel */
+ uint64_t total_zero_pages;
/* buffers to send */
struct iovec *iov;
/* number of iovs used */
@@ -194,12 +206,18 @@
uint8_t *host;
/* non zero pages recv through this channel */
uint64_t total_normal_pages;
+ /* zero pages recv through this channel */
+ uint64_t total_zero_pages;
/* buffers to recv */
struct iovec *iov;
/* Pages that are not zero */
ram_addr_t *normal;
/* num of non zero pages */
uint32_t normal_num;
+ /* Pages that are zero */
+ ram_addr_t *zero;
+ /* num of zero pages */
+ uint32_t zero_num;
/* used for de-compression methods */
void *compress_data;
} MultiFDRecvParams;
@@ -221,6 +239,9 @@
void multifd_register_ops(int method, MultiFDMethods *ops);
void multifd_send_fill_packet(MultiFDSendParams *p);
+bool multifd_send_prepare_common(MultiFDSendParams *p);
+void multifd_send_zero_page_detect(MultiFDSendParams *p);
+void multifd_recv_zero_page_process(MultiFDRecvParams *p);
static inline void multifd_send_prepare_header(MultiFDSendParams *p)
{
diff --git a/migration/options.c b/migration/options.c
index 40eb930..bfd7753 100644
--- a/migration/options.c
+++ b/migration/options.c
@@ -179,6 +179,9 @@
DEFINE_PROP_MIG_MODE("mode", MigrationState,
parameters.mode,
MIG_MODE_NORMAL),
+ DEFINE_PROP_ZERO_PAGE_DETECTION("zero-page-detection", MigrationState,
+ parameters.zero_page_detection,
+ ZERO_PAGE_DETECTION_MULTIFD),
/* Migration capabilities */
DEFINE_PROP_MIG_CAP("x-xbzrle", MIGRATION_CAPABILITY_XBZRLE),
@@ -478,9 +481,9 @@
*/
bool migrate_caps_check(bool *old_caps, bool *new_caps, Error **errp)
{
+ ERRP_GUARD();
MigrationIncomingState *mis = migration_incoming_get_current();
- ERRP_GUARD();
#ifndef CONFIG_LIVE_BLOCK_MIGRATION
if (new_caps[MIGRATION_CAPABILITY_BLOCK]) {
error_setg(errp, "QEMU compiled without old-style (blk/-b, inc/-i) "
@@ -681,7 +684,7 @@
MigrationState *s = migrate_get_current();
bool new_caps[MIGRATION_CAPABILITY__MAX];
- if (migration_is_running(s->state)) {
+ if (migration_is_running()) {
error_setg(errp, QERR_MIGRATION_ACTIVE);
return false;
}
@@ -725,7 +728,7 @@
MigrationCapabilityStatusList *cap;
bool new_caps[MIGRATION_CAPABILITY__MAX];
- if (migration_is_running(s->state) || migration_in_colo_state()) {
+ if (migration_is_running() || migration_in_colo_state()) {
error_setg(errp, QERR_MIGRATION_ACTIVE);
return;
}
@@ -924,6 +927,13 @@
return s->parameters.tls_hostname;
}
+uint64_t migrate_vcpu_dirty_limit_period(void)
+{
+ MigrationState *s = migrate_get_current();
+
+ return s->parameters.x_vcpu_dirty_limit_period;
+}
+
uint64_t migrate_xbzrle_cache_size(void)
{
MigrationState *s = migrate_get_current();
@@ -931,6 +941,13 @@
return s->parameters.xbzrle_cache_size;
}
+ZeroPageDetection migrate_zero_page_detection(void)
+{
+ MigrationState *s = migrate_get_current();
+
+ return s->parameters.zero_page_detection;
+}
+
/* parameter setters */
void migrate_set_block_incremental(bool value)
@@ -1041,6 +1058,8 @@
params->vcpu_dirty_limit = s->parameters.vcpu_dirty_limit;
params->has_mode = true;
params->mode = s->parameters.mode;
+ params->has_zero_page_detection = true;
+ params->zero_page_detection = s->parameters.zero_page_detection;
return params;
}
@@ -1077,6 +1096,7 @@
params->has_x_vcpu_dirty_limit_period = true;
params->has_vcpu_dirty_limit = true;
params->has_mode = true;
+ params->has_zero_page_detection = true;
}
/*
@@ -1085,6 +1105,8 @@
*/
bool migrate_params_check(MigrationParameters *params, Error **errp)
{
+ ERRP_GUARD();
+
if (params->has_compress_level &&
(params->compress_level > 9)) {
error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "compress_level",
@@ -1391,6 +1413,10 @@
if (params->has_mode) {
dest->mode = params->mode;
}
+
+ if (params->has_zero_page_detection) {
+ dest->zero_page_detection = params->zero_page_detection;
+ }
}
static void migrate_params_apply(MigrateSetParameters *params, Error **errp)
@@ -1541,6 +1567,10 @@
if (params->has_mode) {
s->parameters.mode = params->mode;
}
+
+ if (params->has_zero_page_detection) {
+ s->parameters.zero_page_detection = params->zero_page_detection;
+ }
}
void qmp_migrate_set_parameters(MigrateSetParameters *params, Error **errp)
diff --git a/migration/options.h b/migration/options.h
index 6ddd8da..ab8199e 100644
--- a/migration/options.h
+++ b/migration/options.h
@@ -16,6 +16,7 @@
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
+#include "migration/client-options.h"
/* migration properties */
@@ -24,12 +25,10 @@
/* capabilities */
bool migrate_auto_converge(void);
-bool migrate_background_snapshot(void);
bool migrate_block(void);
bool migrate_colo(void);
bool migrate_compress(void);
bool migrate_dirty_bitmaps(void);
-bool migrate_dirty_limit(void);
bool migrate_events(void);
bool migrate_mapped_ram(void);
bool migrate_ignore_shared(void);
@@ -38,11 +37,9 @@
bool migrate_pause_before_switchover(void);
bool migrate_postcopy_blocktime(void);
bool migrate_postcopy_preempt(void);
-bool migrate_postcopy_ram(void);
bool migrate_rdma_pin_all(void);
bool migrate_release_ram(void);
bool migrate_return_path(void);
-bool migrate_switchover_ack(void);
bool migrate_validate_uuid(void);
bool migrate_xbzrle(void);
bool migrate_zero_blocks(void);
@@ -84,7 +81,6 @@
uint64_t migrate_max_bandwidth(void);
uint64_t migrate_avail_switchover_bandwidth(void);
uint64_t migrate_max_postcopy_bandwidth(void);
-MigMode migrate_mode(void);
int migrate_multifd_channels(void);
MultiFDCompression migrate_multifd_compression(void);
int migrate_multifd_zlib_level(void);
@@ -94,6 +90,7 @@
const char *migrate_tls_creds(void);
const char *migrate_tls_hostname(void);
uint64_t migrate_xbzrle_cache_size(void);
+ZeroPageDetection migrate_zero_page_detection(void);
/* parameters setters */
diff --git a/migration/postcopy-ram.c b/migration/postcopy-ram.c
index 0273dc6..eccff49 100644
--- a/migration/postcopy-ram.c
+++ b/migration/postcopy-ram.c
@@ -283,10 +283,10 @@
static bool ufd_check_and_apply(int ufd, MigrationIncomingState *mis,
Error **errp)
{
+ ERRP_GUARD();
uint64_t asked_features = 0;
static uint64_t supported_features;
- ERRP_GUARD();
/*
* it's not possible to
* request UFFD_API twice per one fd
@@ -371,6 +371,7 @@
*/
bool postcopy_ram_supported_by_host(MigrationIncomingState *mis, Error **errp)
{
+ ERRP_GUARD();
long pagesize = qemu_real_host_page_size();
int ufd = -1;
bool ret = false; /* Error unless we change it */
@@ -380,7 +381,6 @@
uint64_t feature_mask;
RAMBlock *block;
- ERRP_GUARD();
if (qemu_target_page_size() > pagesize) {
error_setg(errp, "Target page size bigger than host page size");
goto out;
diff --git a/migration/qemu-file.c b/migration/qemu-file.c
index b10c882..a10882d 100644
--- a/migration/qemu-file.c
+++ b/migration/qemu-file.c
@@ -63,6 +63,8 @@
*/
int qemu_file_shutdown(QEMUFile *f)
{
+ Error *err = NULL;
+
/*
* We must set qemufile error before the real shutdown(), otherwise
* there can be a race window where we thought IO all went though
@@ -91,7 +93,8 @@
return -ENOSYS;
}
- if (qio_channel_shutdown(f->ioc, QIO_CHANNEL_SHUTDOWN_BOTH, NULL) < 0) {
+ if (qio_channel_shutdown(f->ioc, QIO_CHANNEL_SHUTDOWN_BOTH, &err) < 0) {
+ error_report_err(err);
return -EIO;
}
diff --git a/migration/ram.c b/migration/ram.c
index 003c28e..8deb849 100644
--- a/migration/ram.c
+++ b/migration/ram.c
@@ -1140,6 +1140,10 @@
QEMUFile *file = pss->pss_channel;
int len = 0;
+ if (migrate_zero_page_detection() == ZERO_PAGE_DETECTION_NONE) {
+ return 0;
+ }
+
if (!buffer_is_zero(p, TARGET_PAGE_SIZE)) {
return 0;
}
@@ -1284,7 +1288,6 @@
if (!multifd_queue_page(block, offset)) {
return -1;
}
- stat64_add(&mig_stats.normal_pages, 1);
return 1;
}
@@ -2076,7 +2079,6 @@
*/
static int ram_save_target_page_legacy(RAMState *rs, PageSearchStatus *pss)
{
- RAMBlock *block = pss->block;
ram_addr_t offset = ((ram_addr_t)pss->page) << TARGET_PAGE_BITS;
int res;
@@ -2092,17 +2094,33 @@
return 1;
}
+ return ram_save_page(rs, pss);
+}
+
+/**
+ * ram_save_target_page_multifd: send one target page to multifd workers
+ *
+ * Returns 1 if the page was queued, -1 otherwise.
+ *
+ * @rs: current RAM state
+ * @pss: data about the page we want to send
+ */
+static int ram_save_target_page_multifd(RAMState *rs, PageSearchStatus *pss)
+{
+ RAMBlock *block = pss->block;
+ ram_addr_t offset = ((ram_addr_t)pss->page) << TARGET_PAGE_BITS;
+
/*
- * Do not use multifd in postcopy as one whole host page should be
- * placed. Meanwhile postcopy requires atomic update of pages, so even
- * if host page size == guest page size the dest guest during run may
- * still see partially copied pages which is data corruption.
+ * While using multifd live migration, we still need to handle zero
+ * page checking on the migration main thread.
*/
- if (migrate_multifd() && !migration_in_postcopy()) {
- return ram_save_multifd_page(block, offset);
+ if (migrate_zero_page_detection() == ZERO_PAGE_DETECTION_LEGACY) {
+ if (save_zero_page(rs, pss, offset)) {
+ return 1;
+ }
}
- return ram_save_page(rs, pss);
+ return ram_save_multifd_page(block, offset);
}
/* Should be called before sending a host page */
@@ -2909,10 +2927,9 @@
RAMBlock *block;
ram_addr_t offset;
size_t used_len, start, npages;
- MigrationState *s = migrate_get_current();
/* This function is currently expected to be used during live migration */
- if (!migration_is_setup_or_active(s->state)) {
+ if (!migration_is_setup_or_active()) {
return;
}
@@ -3110,7 +3127,12 @@
}
migration_ops = g_malloc0(sizeof(MigrationOps));
- migration_ops->ram_save_target_page = ram_save_target_page_legacy;
+
+ if (migrate_multifd()) {
+ migration_ops->ram_save_target_page = ram_save_target_page_multifd;
+ } else {
+ migration_ops->ram_save_target_page = ram_save_target_page_legacy;
+ }
bql_unlock();
ret = multifd_send_sync_main();
@@ -3150,9 +3172,13 @@
}
}
-void ramblock_set_file_bmap_atomic(RAMBlock *block, ram_addr_t offset)
+void ramblock_set_file_bmap_atomic(RAMBlock *block, ram_addr_t offset, bool set)
{
- set_bit_atomic(offset >> TARGET_PAGE_BITS, block->file_bmap);
+ if (set) {
+ set_bit_atomic(offset >> TARGET_PAGE_BITS, block->file_bmap);
+ } else {
+ clear_bit_atomic(offset >> TARGET_PAGE_BITS, block->file_bmap);
+ }
}
/**
@@ -3263,7 +3289,7 @@
out:
if (ret >= 0
- && migration_is_setup_or_active(migrate_get_current()->state)) {
+ && migration_is_setup_or_active()) {
if (migrate_multifd() && migrate_multifd_flush_after_each_section() &&
!migrate_mapped_ram()) {
ret = multifd_send_sync_main();
@@ -4214,6 +4240,12 @@
i++;
addr = qemu_get_be64(f);
+ ret = qemu_file_get_error(f);
+ if (ret) {
+ error_report("Getting RAM address failed");
+ break;
+ }
+
flags = addr & ~TARGET_PAGE_MASK;
addr &= TARGET_PAGE_MASK;
diff --git a/migration/ram.h b/migration/ram.h
index b9ac0da..08feeca 100644
--- a/migration/ram.h
+++ b/migration/ram.h
@@ -75,7 +75,8 @@
bool ramblock_page_is_discarded(RAMBlock *rb, ram_addr_t start);
void postcopy_preempt_shutdown_file(MigrationState *s);
void *postcopy_preempt_thread(void *opaque);
-void ramblock_set_file_bmap_atomic(RAMBlock *block, ram_addr_t offset);
+void ramblock_set_file_bmap_atomic(RAMBlock *block, ram_addr_t offset,
+ bool set);
/* ram cache */
int colo_init_ram_cache(void);
diff --git a/migration/rdma.c b/migration/rdma.c
index a355dce..855753c 100644
--- a/migration/rdma.c
+++ b/migration/rdma.c
@@ -3357,7 +3357,7 @@
goto err_rdma_dest_wait;
}
- isock->host = rdma->host;
+ isock->host = g_strdup(rdma->host);
isock->port = g_strdup_printf("%d", rdma->port);
/*
diff --git a/migration/savevm.c b/migration/savevm.c
index dc1fb9c..388d7af 100644
--- a/migration/savevm.c
+++ b/migration/savevm.c
@@ -1317,7 +1317,7 @@
MigrationState *ms = migrate_get_current();
SaveStateEntry *se;
Error *local_err = NULL;
- int ret;
+ int ret = 0;
json_writer_int64(ms->vmdesc, "page_size", qemu_target_page_size());
json_writer_start_array(ms->vmdesc, "devices");
@@ -1351,6 +1351,10 @@
}
}
+ if (ret) {
+ return;
+ }
+
if (precopy_notify(PRECOPY_NOTIFY_SETUP, &local_err)) {
error_report_err(local_err);
}
@@ -1390,7 +1394,8 @@
int qemu_savevm_state_iterate(QEMUFile *f, bool postcopy)
{
SaveStateEntry *se;
- int ret = 1;
+ bool all_finished = true;
+ int ret;
trace_savevm_state_iterate();
QTAILQ_FOREACH(se, &savevm_state.handlers, entry) {
@@ -1431,16 +1436,12 @@
"%d(%s): %d",
se->section_id, se->idstr, ret);
qemu_file_set_error(f, ret);
- }
- if (ret <= 0) {
- /* Do not proceed to the next vmstate before this one reported
- completion of the current stage. This serializes the migration
- and reduces the probability that a faster changing state is
- synchronized over and over again. */
- break;
+ return ret;
+ } else if (!ret) {
+ all_finished = false;
}
}
- return ret;
+ return all_finished;
}
static bool should_send_vmdesc(void)
@@ -1705,7 +1706,7 @@
MigrationState *ms = migrate_get_current();
MigrationStatus status;
- if (migration_is_running(ms->state)) {
+ if (migration_is_running()) {
error_setg(errp, QERR_MIGRATION_ACTIVE);
return -EINVAL;
}
diff --git a/migration/trace-events b/migration/trace-events
index bf1a069..f0e1cb8 100644
--- a/migration/trace-events
+++ b/migration/trace-events
@@ -128,21 +128,21 @@
# multifd.c
multifd_new_send_channel_async(uint8_t id) "channel %u"
multifd_new_send_channel_async_error(uint8_t id, void *err) "channel=%u err=%p"
-multifd_recv(uint8_t id, uint64_t packet_num, uint32_t used, uint32_t flags, uint32_t next_packet_size) "channel %u packet_num %" PRIu64 " pages %u flags 0x%x next packet size %u"
+multifd_recv(uint8_t id, uint64_t packet_num, uint32_t normal, uint32_t zero, uint32_t flags, uint32_t next_packet_size) "channel %u packet_num %" PRIu64 " normal pages %u zero pages %u flags 0x%x next packet size %u"
multifd_recv_new_channel(uint8_t id) "channel %u"
multifd_recv_sync_main(long packet_num) "packet num %ld"
multifd_recv_sync_main_signal(uint8_t id) "channel %u"
multifd_recv_sync_main_wait(uint8_t id) "iter %u"
multifd_recv_terminate_threads(bool error) "error %d"
-multifd_recv_thread_end(uint8_t id, uint64_t packets, uint64_t pages) "channel %u packets %" PRIu64 " pages %" PRIu64
+multifd_recv_thread_end(uint8_t id, uint64_t packets, uint64_t normal_pages, uint64_t zero_pages) "channel %u packets %" PRIu64 " normal pages %" PRIu64 " zero pages %" PRIu64
multifd_recv_thread_start(uint8_t id) "%u"
-multifd_send(uint8_t id, uint64_t packet_num, uint32_t normal, uint32_t flags, uint32_t next_packet_size) "channel %u packet_num %" PRIu64 " normal pages %u flags 0x%x next packet size %u"
+multifd_send(uint8_t id, uint64_t packet_num, uint32_t normal_pages, uint32_t zero_pages, uint32_t flags, uint32_t next_packet_size) "channel %u packet_num %" PRIu64 " normal pages %u zero pages %u flags 0x%x next packet size %u"
multifd_send_error(uint8_t id) "channel %u"
multifd_send_sync_main(long packet_num) "packet num %ld"
multifd_send_sync_main_signal(uint8_t id) "channel %u"
multifd_send_sync_main_wait(uint8_t id) "channel %u"
multifd_send_terminate_threads(void) ""
-multifd_send_thread_end(uint8_t id, uint64_t packets, uint64_t normal_pages) "channel %u packets %" PRIu64 " normal pages %" PRIu64
+multifd_send_thread_end(uint8_t id, uint64_t packets, uint64_t normal_pages, uint64_t zero_pages) "channel %u packets %" PRIu64 " normal pages %" PRIu64 " zero pages %" PRIu64
multifd_send_thread_start(uint8_t id) "%u"
multifd_tls_outgoing_handshake_start(void *ioc, void *tioc, const char *hostname) "ioc=%p tioc=%p hostname=%s"
multifd_tls_outgoing_handshake_error(void *ioc, const char *err) "ioc=%p err=%s"
diff --git a/net/colo-compare.c b/net/colo-compare.c
index f2dfc0e..c4ad0ab 100644
--- a/net/colo-compare.c
+++ b/net/colo-compare.c
@@ -28,7 +28,6 @@
#include "sysemu/iothread.h"
#include "net/colo-compare.h"
#include "migration/colo.h"
-#include "migration/migration.h"
#include "util.h"
#include "block/aio-wait.h"
@@ -189,7 +188,7 @@
notify_remote_frame(s);
} else {
notifier_list_notify(&colo_compare_notifiers,
- migrate_get_current());
+ NULL);
}
}
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 5f06c39..85e73dd 100644
--- a/net/vhost-vdpa.c
+++ b/net/vhost-vdpa.c
@@ -26,7 +26,6 @@
#include <err.h>
#include "standard-headers/linux/virtio_net.h"
#include "monitor/monitor.h"
-#include "migration/migration.h"
#include "migration/misc.h"
#include "hw/virtio/vhost.h"
#include "trace.h"
@@ -374,7 +373,7 @@
assert(nc->info->type == NET_CLIENT_DRIVER_VHOST_VDPA);
if (s->always_svq ||
- migration_is_setup_or_active(migrate_get_current()->state)) {
+ migration_is_setup_or_active()) {
v->shadow_vqs_enabled = true;
} else {
v->shadow_vqs_enabled = false;
@@ -1583,14 +1582,13 @@
static int vhost_vdpa_probe_cvq_isolation(int device_fd, uint64_t features,
int cvq_index, Error **errp)
{
+ ERRP_GUARD();
uint64_t backend_features;
int64_t cvq_group;
uint8_t status = VIRTIO_CONFIG_S_ACKNOWLEDGE |
VIRTIO_CONFIG_S_DRIVER;
int r;
- ERRP_GUARD();
-
r = ioctl(device_fd, VHOST_GET_BACKEND_FEATURES, &backend_features);
if (unlikely(r < 0)) {
error_setg_errno(errp, errno, "Cannot get vdpa backend_features");
@@ -1777,6 +1775,7 @@
int net_init_vhost_vdpa(const Netdev *netdev, const char *name,
NetClientState *peer, Error **errp)
{
+ ERRP_GUARD();
const NetdevVhostVDPAOptions *opts;
uint64_t features;
int vdpa_device_fd;
diff --git a/qapi/ebpf.json b/qapi/ebpf.json
new file mode 100644
index 0000000..f413d00
--- /dev/null
+++ b/qapi/ebpf.json
@@ -0,0 +1,66 @@
+# -*- Mode: Python -*-
+# vim: filetype=python
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or later.
+# See the COPYING file in the top-level directory.
+
+##
+# = eBPF Objects
+#
+# eBPF object is an ELF binary that contains the eBPF
+# program and eBPF map description(BTF). Overall, eBPF
+# object should contain the program and enough metadata
+# to create/load eBPF with libbpf. As the eBPF maps/program
+# should correspond to QEMU, the eBPF can't be used from
+# different QEMU build.
+#
+# Currently, there is a possible eBPF for receive-side scaling (RSS).
+#
+##
+
+##
+# @EbpfObject:
+#
+# An eBPF ELF object.
+#
+# @object: the eBPF object encoded in base64
+#
+# Since: 9.0
+##
+{ 'struct': 'EbpfObject',
+ 'data': {'object': 'str'},
+ 'if': 'CONFIG_EBPF' }
+
+##
+# @EbpfProgramID:
+#
+# The eBPF programs that can be gotten with request-ebpf.
+#
+# @rss: Receive side scaling, technology that allows steering traffic
+# between queues by calculation hash. Users may set up
+# indirection table and hash/packet types configurations. Used
+# with virtio-net.
+#
+# Since: 9.0
+##
+{ 'enum': 'EbpfProgramID',
+ 'if': 'CONFIG_EBPF',
+ 'data': [ { 'name': 'rss' } ] }
+
+##
+# @request-ebpf:
+#
+# Retrieve an eBPF object that can be loaded with libbpf. Management
+# applications (g.e. libvirt) may load it and pass file descriptors to
+# QEMU, so they can run running QEMU without BPF capabilities.
+#
+# @id: The ID of the program to return.
+#
+# Returns: eBPF object encoded in base64.
+#
+# Since: 9.0
+##
+{ 'command': 'request-ebpf',
+ 'data': { 'id': 'EbpfProgramID' },
+ 'returns': 'EbpfObject',
+ 'if': 'CONFIG_EBPF' }
diff --git a/qapi/meson.build b/qapi/meson.build
index f81a375..375d564 100644
--- a/qapi/meson.build
+++ b/qapi/meson.build
@@ -33,6 +33,7 @@
'crypto',
'cxl',
'dump',
+ 'ebpf',
'error',
'introspect',
'job',
diff --git a/qapi/migration.json b/qapi/migration.json
index 51d188b..aa1b39b 100644
--- a/qapi/migration.json
+++ b/qapi/migration.json
@@ -671,6 +671,23 @@
'data': [ 'normal', 'cpr-reboot' ] }
##
+# @ZeroPageDetection:
+#
+# @none: Do not perform zero page checking.
+#
+# @legacy: Perform zero page checking in main migration thread.
+#
+# @multifd: Perform zero page checking in multifd sender thread if
+# multifd migration is enabled, else in the main migration
+# thread as for @legacy.
+#
+# Since: 9.0
+#
+##
+{ 'enum': 'ZeroPageDetection',
+ 'data': [ 'none', 'legacy', 'multifd' ] }
+
+##
# @BitmapMigrationBitmapAliasTransform:
#
# @persistent: If present, the bitmap will be made persistent or
@@ -891,6 +908,10 @@
# @mode: Migration mode. See description in @MigMode. Default is 'normal'.
# (Since 8.2)
#
+# @zero-page-detection: Whether and how to detect zero pages.
+# See description in @ZeroPageDetection. Default is 'multifd'.
+# (since 9.0)
+#
# Features:
#
# @deprecated: Member @block-incremental is deprecated. Use
@@ -924,7 +945,8 @@
'block-bitmap-mapping',
{ 'name': 'x-vcpu-dirty-limit-period', 'features': ['unstable'] },
'vcpu-dirty-limit',
- 'mode'] }
+ 'mode',
+ 'zero-page-detection'] }
##
# @MigrateSetParameters:
@@ -1083,6 +1105,10 @@
# @mode: Migration mode. See description in @MigMode. Default is 'normal'.
# (Since 8.2)
#
+# @zero-page-detection: Whether and how to detect zero pages.
+# See description in @ZeroPageDetection. Default is 'multifd'.
+# (since 9.0)
+#
# Features:
#
# @deprecated: Member @block-incremental is deprecated. Use
@@ -1136,7 +1162,8 @@
'*x-vcpu-dirty-limit-period': { 'type': 'uint64',
'features': [ 'unstable' ] },
'*vcpu-dirty-limit': 'uint64',
- '*mode': 'MigMode'} }
+ '*mode': 'MigMode',
+ '*zero-page-detection': 'ZeroPageDetection'} }
##
# @migrate-set-parameters:
@@ -1311,6 +1338,10 @@
# @mode: Migration mode. See description in @MigMode. Default is 'normal'.
# (Since 8.2)
#
+# @zero-page-detection: Whether and how to detect zero pages.
+# See description in @ZeroPageDetection. Default is 'multifd'.
+# (since 9.0)
+#
# Features:
#
# @deprecated: Member @block-incremental is deprecated. Use
@@ -1361,7 +1392,8 @@
'*x-vcpu-dirty-limit-period': { 'type': 'uint64',
'features': [ 'unstable' ] },
'*vcpu-dirty-limit': 'uint64',
- '*mode': 'MigMode'} }
+ '*mode': 'MigMode',
+ '*zero-page-detection': 'ZeroPageDetection'} }
##
# @query-migrate-parameters:
diff --git a/qapi/qapi-schema.json b/qapi/qapi-schema.json
index c01ec33..8304d45 100644
--- a/qapi/qapi-schema.json
+++ b/qapi/qapi-schema.json
@@ -53,6 +53,7 @@
{ 'include': 'char.json' }
{ 'include': 'dump.json' }
{ 'include': 'net.json' }
+{ 'include': 'ebpf.json' }
{ 'include': 'rdma.json' }
{ 'include': 'rocker.json' }
{ 'include': 'tpm.json' }
diff --git a/qga/commands-win32.c b/qga/commands-win32.c
index a101575..6242737 100644
--- a/qga/commands-win32.c
+++ b/qga/commands-win32.c
@@ -2120,49 +2120,47 @@
typedef struct _ga_matrix_lookup_t {
int major;
int minor;
- char const *version;
- char const *version_id;
+ const char *version;
+ const char *version_id;
} ga_matrix_lookup_t;
-static ga_matrix_lookup_t const WIN_VERSION_MATRIX[2][7] = {
- {
- /* Desktop editions */
- { 5, 0, "Microsoft Windows 2000", "2000"},
- { 5, 1, "Microsoft Windows XP", "xp"},
- { 6, 0, "Microsoft Windows Vista", "vista"},
- { 6, 1, "Microsoft Windows 7" "7"},
- { 6, 2, "Microsoft Windows 8", "8"},
- { 6, 3, "Microsoft Windows 8.1", "8.1"},
- { 0, 0, 0}
- },{
- /* Server editions */
- { 5, 2, "Microsoft Windows Server 2003", "2003"},
- { 6, 0, "Microsoft Windows Server 2008", "2008"},
- { 6, 1, "Microsoft Windows Server 2008 R2", "2008r2"},
- { 6, 2, "Microsoft Windows Server 2012", "2012"},
- { 6, 3, "Microsoft Windows Server 2012 R2", "2012r2"},
- { 0, 0, 0},
- { 0, 0, 0}
- }
+static const ga_matrix_lookup_t WIN_CLIENT_VERSION_MATRIX[] = {
+ { 5, 0, "Microsoft Windows 2000", "2000"},
+ { 5, 1, "Microsoft Windows XP", "xp"},
+ { 6, 0, "Microsoft Windows Vista", "vista"},
+ { 6, 1, "Microsoft Windows 7" "7"},
+ { 6, 2, "Microsoft Windows 8", "8"},
+ { 6, 3, "Microsoft Windows 8.1", "8.1"},
+ { }
+};
+
+static const ga_matrix_lookup_t WIN_SERVER_VERSION_MATRIX[] = {
+ { 5, 2, "Microsoft Windows Server 2003", "2003"},
+ { 6, 0, "Microsoft Windows Server 2008", "2008"},
+ { 6, 1, "Microsoft Windows Server 2008 R2", "2008r2"},
+ { 6, 2, "Microsoft Windows Server 2012", "2012"},
+ { 6, 3, "Microsoft Windows Server 2012 R2", "2012r2"},
+ { },
};
typedef struct _ga_win_10_0_t {
int first_build;
- char const *version;
- char const *version_id;
+ const char *version;
+ const char *version_id;
} ga_win_10_0_t;
-static ga_win_10_0_t const WIN_10_0_SERVER_VERSION_MATRIX[4] = {
+static const ga_win_10_0_t WIN_10_0_SERVER_VERSION_MATRIX[] = {
{14393, "Microsoft Windows Server 2016", "2016"},
{17763, "Microsoft Windows Server 2019", "2019"},
{20344, "Microsoft Windows Server 2022", "2022"},
- {0, 0}
+ {26040, "MIcrosoft Windows Server 2025", "2025"},
+ { }
};
-static ga_win_10_0_t const WIN_10_0_CLIENT_VERSION_MATRIX[3] = {
+static const ga_win_10_0_t WIN_10_0_CLIENT_VERSION_MATRIX[] = {
{10240, "Microsoft Windows 10", "10"},
{22000, "Microsoft Windows 11", "11"},
- {0, 0}
+ { }
};
static void ga_get_win_version(RTL_OSVERSIONINFOEXW *info, Error **errp)
@@ -2185,16 +2183,17 @@
return;
}
-static char *ga_get_win_name(OSVERSIONINFOEXW const *os_version, bool id)
+static char *ga_get_win_name(const OSVERSIONINFOEXW *os_version, bool id)
{
DWORD major = os_version->dwMajorVersion;
DWORD minor = os_version->dwMinorVersion;
DWORD build = os_version->dwBuildNumber;
int tbl_idx = (os_version->wProductType != VER_NT_WORKSTATION);
- ga_matrix_lookup_t const *table = WIN_VERSION_MATRIX[tbl_idx];
- ga_win_10_0_t const *win_10_0_table = tbl_idx ?
+ const ga_matrix_lookup_t *table = tbl_idx ?
+ WIN_SERVER_VERSION_MATRIX : WIN_CLIENT_VERSION_MATRIX;
+ const ga_win_10_0_t *win_10_0_table = tbl_idx ?
WIN_10_0_SERVER_VERSION_MATRIX : WIN_10_0_CLIENT_VERSION_MATRIX;
- ga_win_10_0_t const *win_10_0_version = NULL;
+ const ga_win_10_0_t *win_10_0_version = NULL;
while (table->version != NULL) {
if (major == 10 && minor == 0) {
while (win_10_0_table->version != NULL) {
diff --git a/scripts/tracetool.py b/scripts/tracetool.py
index ab7653a..5de9ce9 100755
--- a/scripts/tracetool.py
+++ b/scripts/tracetool.py
@@ -44,12 +44,9 @@ def error_opt(msg = None):
--help This help message.
--list-backends Print list of available backends.
--check-backends Check if the given backend is valid.
- --binary <path> Full path to QEMU binary.
- --target-type <type> QEMU emulator target type ('system' or 'user').
- --target-name <name> QEMU emulator target name.
- --group <name> Name of the event group
- --probe-prefix <prefix> Prefix for dtrace probe names
- (default: qemu-<target-type>-<target-name>).\
+ --binary <path> Full path to QEMU binary (required for 'stap' backend).
+ --group <name> Name of the event group.
+ --probe-prefix <prefix> Prefix for dtrace probe names (required for 'stap' backend).
""" % {
"script" : _SCRIPT,
"backends" : backend_descr,
@@ -67,7 +64,7 @@ def main(args):
long_opts = ["backends=", "format=", "help", "list-backends",
"check-backends", "group="]
- long_opts += ["binary=", "target-type=", "target-name=", "probe-prefix="]
+ long_opts += ["binary=", "probe-prefix="]
try:
opts, args = getopt.getopt(args[1:], "", long_opts)
@@ -79,8 +76,6 @@ def main(args):
arg_format = ""
arg_group = None
binary = None
- target_type = None
- target_name = None
probe_prefix = None
for opt, arg in opts:
if opt == "--help":
@@ -102,10 +97,6 @@ def main(args):
elif opt == "--binary":
binary = arg
- elif opt == '--target-type':
- target_type = arg
- elif opt == '--target-name':
- target_name = arg
elif opt == '--probe-prefix':
probe_prefix = arg
@@ -127,13 +118,8 @@ def main(args):
if arg_format == "stap":
if binary is None:
error_opt("--binary is required for SystemTAP tapset generator")
- if probe_prefix is None and target_type is None:
- error_opt("--target-type is required for SystemTAP tapset generator")
- if probe_prefix is None and target_name is None:
- error_opt("--target-name is required for SystemTAP tapset generator")
-
if probe_prefix is None:
- probe_prefix = ".".join(["qemu", target_type, target_name])
+ error_opt("--probe-prefix is required for SystemTAP tapset generator")
if len(args) < 2:
error_opt("missing trace-events and output filepaths")
diff --git a/stubs/colo.c b/stubs/colo.c
index 08c9f98..f8c069b 100644
--- a/stubs/colo.c
+++ b/stubs/colo.c
@@ -2,7 +2,6 @@
#include "qemu/notify.h"
#include "net/colo-compare.h"
#include "migration/colo.h"
-#include "migration/migration.h"
#include "qemu/error-report.h"
#include "qapi/qapi-commands-migration.h"
diff --git a/system/dirtylimit.c b/system/dirtylimit.c
index b5607eb..ab20da3 100644
--- a/system/dirtylimit.c
+++ b/system/dirtylimit.c
@@ -25,8 +25,6 @@
#include "sysemu/kvm.h"
#include "trace.h"
#include "migration/misc.h"
-#include "migration/migration.h"
-#include "migration/options.h"
/*
* Dirtylimit stop working if dirty page rate error
@@ -78,14 +76,13 @@
static void vcpu_dirty_rate_stat_collect(void)
{
- MigrationState *s = migrate_get_current();
VcpuStat stat;
int i = 0;
int64_t period = DIRTYLIMIT_CALC_TIME_MS;
if (migrate_dirty_limit() &&
- migration_is_active(s)) {
- period = s->parameters.x_vcpu_dirty_limit_period;
+ migration_is_active()) {
+ period = migrate_vcpu_dirty_limit_period();
}
/* calculate vcpu dirtyrate */
@@ -450,10 +447,8 @@
*/
static bool dirtylimit_is_allowed(void)
{
- MigrationState *ms = migrate_get_current();
-
- if (migration_is_running(ms->state) &&
- (!qemu_thread_is_self(&ms->thread)) &&
+ if (migration_is_running() &&
+ !migration_thread_is_self() &&
migrate_dirty_limit() &&
dirtylimit_in_service()) {
return false;
diff --git a/system/physmem.c b/system/physmem.c
index 6e9ed97..6cfb7a8 100644
--- a/system/physmem.c
+++ b/system/physmem.c
@@ -2681,53 +2681,69 @@
return false;
}
+static MemTxResult flatview_write_continue_step(MemTxAttrs attrs,
+ const uint8_t *buf,
+ hwaddr len, hwaddr mr_addr,
+ hwaddr *l, MemoryRegion *mr)
+{
+ if (!flatview_access_allowed(mr, attrs, mr_addr, *l)) {
+ return MEMTX_ACCESS_ERROR;
+ }
+
+ if (!memory_access_is_direct(mr, true)) {
+ uint64_t val;
+ MemTxResult result;
+ bool release_lock = prepare_mmio_access(mr);
+
+ *l = memory_access_size(mr, *l, mr_addr);
+ /*
+ * XXX: could force current_cpu to NULL to avoid
+ * potential bugs
+ */
+
+ /*
+ * Assure Coverity (and ourselves) that we are not going to OVERRUN
+ * the buffer by following ldn_he_p().
+ */
+#ifdef QEMU_STATIC_ANALYSIS
+ assert((*l == 1 && len >= 1) ||
+ (*l == 2 && len >= 2) ||
+ (*l == 4 && len >= 4) ||
+ (*l == 8 && len >= 8));
+#endif
+ val = ldn_he_p(buf, *l);
+ result = memory_region_dispatch_write(mr, mr_addr, val,
+ size_memop(*l), attrs);
+ if (release_lock) {
+ bql_unlock();
+ }
+
+ return result;
+ } else {
+ /* RAM case */
+ uint8_t *ram_ptr = qemu_ram_ptr_length(mr->ram_block, mr_addr, l,
+ false);
+
+ memmove(ram_ptr, buf, *l);
+ invalidate_and_set_dirty(mr, mr_addr, *l);
+
+ return MEMTX_OK;
+ }
+}
+
/* Called within RCU critical section. */
static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
MemTxAttrs attrs,
const void *ptr,
- hwaddr len, hwaddr addr1,
+ hwaddr len, hwaddr mr_addr,
hwaddr l, MemoryRegion *mr)
{
- uint8_t *ram_ptr;
- uint64_t val;
MemTxResult result = MEMTX_OK;
- bool release_lock = false;
const uint8_t *buf = ptr;
for (;;) {
- if (!flatview_access_allowed(mr, attrs, addr1, l)) {
- result |= MEMTX_ACCESS_ERROR;
- /* Keep going. */
- } else if (!memory_access_is_direct(mr, true)) {
- release_lock |= prepare_mmio_access(mr);
- l = memory_access_size(mr, l, addr1);
- /* XXX: could force current_cpu to NULL to avoid
- potential bugs */
-
- /*
- * Assure Coverity (and ourselves) that we are not going to OVERRUN
- * the buffer by following ldn_he_p().
- */
-#ifdef QEMU_STATIC_ANALYSIS
- assert((l == 1 && len >= 1) ||
- (l == 2 && len >= 2) ||
- (l == 4 && len >= 4) ||
- (l == 8 && len >= 8));
-#endif
- val = ldn_he_p(buf, l);
- result |= memory_region_dispatch_write(mr, addr1, val,
- size_memop(l), attrs);
- } else {
- /* RAM case */
- ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
- memmove(ram_ptr, buf, l);
- invalidate_and_set_dirty(mr, addr1, l);
- }
-
- if (release_lock) {
- bql_unlock();
- release_lock = false;
- }
+ result |= flatview_write_continue_step(attrs, buf, len, mr_addr, &l,
+ mr);
len -= l;
buf += l;
@@ -2738,7 +2754,7 @@
}
l = len;
- mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
+ mr = flatview_translate(fv, addr, &mr_addr, &l, true, attrs);
}
return result;
@@ -2749,63 +2765,76 @@
const void *buf, hwaddr len)
{
hwaddr l;
- hwaddr addr1;
+ hwaddr mr_addr;
MemoryRegion *mr;
l = len;
- mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
+ mr = flatview_translate(fv, addr, &mr_addr, &l, true, attrs);
if (!flatview_access_allowed(mr, attrs, addr, len)) {
return MEMTX_ACCESS_ERROR;
}
return flatview_write_continue(fv, addr, attrs, buf, len,
- addr1, l, mr);
+ mr_addr, l, mr);
+}
+
+static MemTxResult flatview_read_continue_step(MemTxAttrs attrs, uint8_t *buf,
+ hwaddr len, hwaddr mr_addr,
+ hwaddr *l,
+ MemoryRegion *mr)
+{
+ if (!flatview_access_allowed(mr, attrs, mr_addr, *l)) {
+ return MEMTX_ACCESS_ERROR;
+ }
+
+ if (!memory_access_is_direct(mr, false)) {
+ /* I/O case */
+ uint64_t val;
+ MemTxResult result;
+ bool release_lock = prepare_mmio_access(mr);
+
+ *l = memory_access_size(mr, *l, mr_addr);
+ result = memory_region_dispatch_read(mr, mr_addr, &val, size_memop(*l),
+ attrs);
+
+ /*
+ * Assure Coverity (and ourselves) that we are not going to OVERRUN
+ * the buffer by following stn_he_p().
+ */
+#ifdef QEMU_STATIC_ANALYSIS
+ assert((*l == 1 && len >= 1) ||
+ (*l == 2 && len >= 2) ||
+ (*l == 4 && len >= 4) ||
+ (*l == 8 && len >= 8));
+#endif
+ stn_he_p(buf, *l, val);
+
+ if (release_lock) {
+ bql_unlock();
+ }
+ return result;
+ } else {
+ /* RAM case */
+ uint8_t *ram_ptr = qemu_ram_ptr_length(mr->ram_block, mr_addr, l,
+ false);
+
+ memcpy(buf, ram_ptr, *l);
+
+ return MEMTX_OK;
+ }
}
/* Called within RCU critical section. */
MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
MemTxAttrs attrs, void *ptr,
- hwaddr len, hwaddr addr1, hwaddr l,
+ hwaddr len, hwaddr mr_addr, hwaddr l,
MemoryRegion *mr)
{
- uint8_t *ram_ptr;
- uint64_t val;
MemTxResult result = MEMTX_OK;
- bool release_lock = false;
uint8_t *buf = ptr;
fuzz_dma_read_cb(addr, len, mr);
for (;;) {
- if (!flatview_access_allowed(mr, attrs, addr1, l)) {
- result |= MEMTX_ACCESS_ERROR;
- /* Keep going. */
- } else if (!memory_access_is_direct(mr, false)) {
- /* I/O case */
- release_lock |= prepare_mmio_access(mr);
- l = memory_access_size(mr, l, addr1);
- result |= memory_region_dispatch_read(mr, addr1, &val,
- size_memop(l), attrs);
-
- /*
- * Assure Coverity (and ourselves) that we are not going to OVERRUN
- * the buffer by following stn_he_p().
- */
-#ifdef QEMU_STATIC_ANALYSIS
- assert((l == 1 && len >= 1) ||
- (l == 2 && len >= 2) ||
- (l == 4 && len >= 4) ||
- (l == 8 && len >= 8));
-#endif
- stn_he_p(buf, l, val);
- } else {
- /* RAM case */
- ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
- memcpy(buf, ram_ptr, l);
- }
-
- if (release_lock) {
- bql_unlock();
- release_lock = false;
- }
+ result |= flatview_read_continue_step(attrs, buf, len, mr_addr, &l, mr);
len -= l;
buf += l;
@@ -2816,7 +2845,7 @@
}
l = len;
- mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
+ mr = flatview_translate(fv, addr, &mr_addr, &l, false, attrs);
}
return result;
@@ -2827,16 +2856,16 @@
MemTxAttrs attrs, void *buf, hwaddr len)
{
hwaddr l;
- hwaddr addr1;
+ hwaddr mr_addr;
MemoryRegion *mr;
l = len;
- mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
+ mr = flatview_translate(fv, addr, &mr_addr, &l, false, attrs);
if (!flatview_access_allowed(mr, attrs, addr, len)) {
return MEMTX_ACCESS_ERROR;
}
return flatview_read_continue(fv, addr, attrs, buf, len,
- addr1, l, mr);
+ mr_addr, l, mr);
}
MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
@@ -3341,6 +3370,59 @@
return section.mr;
}
+/* Called within RCU critical section. */
+static MemTxResult address_space_write_continue_cached(MemTxAttrs attrs,
+ const void *ptr,
+ hwaddr len,
+ hwaddr mr_addr,
+ hwaddr l,
+ MemoryRegion *mr)
+{
+ MemTxResult result = MEMTX_OK;
+ const uint8_t *buf = ptr;
+
+ for (;;) {
+ result |= flatview_write_continue_step(attrs, buf, len, mr_addr, &l,
+ mr);
+
+ len -= l;
+ buf += l;
+ mr_addr += l;
+
+ if (!len) {
+ break;
+ }
+
+ l = len;
+ }
+
+ return result;
+}
+
+/* Called within RCU critical section. */
+static MemTxResult address_space_read_continue_cached(MemTxAttrs attrs,
+ void *ptr, hwaddr len,
+ hwaddr mr_addr, hwaddr l,
+ MemoryRegion *mr)
+{
+ MemTxResult result = MEMTX_OK;
+ uint8_t *buf = ptr;
+
+ for (;;) {
+ result |= flatview_read_continue_step(attrs, buf, len, mr_addr, &l, mr);
+ len -= l;
+ buf += l;
+ mr_addr += l;
+
+ if (!len) {
+ break;
+ }
+ l = len;
+ }
+
+ return result;
+}
+
/* Called from RCU critical section. address_space_read_cached uses this
* out of line function when the target is an MMIO or IOMMU region.
*/
@@ -3348,15 +3430,14 @@
address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
void *buf, hwaddr len)
{
- hwaddr addr1, l;
+ hwaddr mr_addr, l;
MemoryRegion *mr;
l = len;
- mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
+ mr = address_space_translate_cached(cache, addr, &mr_addr, &l, false,
MEMTXATTRS_UNSPECIFIED);
- return flatview_read_continue(cache->fv,
- addr, MEMTXATTRS_UNSPECIFIED, buf, len,
- addr1, l, mr);
+ return address_space_read_continue_cached(MEMTXATTRS_UNSPECIFIED,
+ buf, len, mr_addr, l, mr);
}
/* Called from RCU critical section. address_space_write_cached uses this
@@ -3366,15 +3447,14 @@
address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
const void *buf, hwaddr len)
{
- hwaddr addr1, l;
+ hwaddr mr_addr, l;
MemoryRegion *mr;
l = len;
- mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
+ mr = address_space_translate_cached(cache, addr, &mr_addr, &l, true,
MEMTXATTRS_UNSPECIFIED);
- return flatview_write_continue(cache->fv,
- addr, MEMTXATTRS_UNSPECIFIED, buf, len,
- addr1, l, mr);
+ return address_space_write_continue_cached(MEMTXATTRS_UNSPECIFIED,
+ buf, len, mr_addr, l, mr);
}
#define ARG1_DECL MemoryRegionCache *cache
diff --git a/system/qdev-monitor.c b/system/qdev-monitor.c
index 09e07ca..c124389 100644
--- a/system/qdev-monitor.c
+++ b/system/qdev-monitor.c
@@ -38,7 +38,6 @@
#include "qemu/option_int.h"
#include "sysemu/block-backend.h"
#include "migration/misc.h"
-#include "migration/migration.h"
#include "qemu/cutils.h"
#include "hw/qdev-properties.h"
#include "hw/clock.h"
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index bf70173..05f9ee41 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -135,40 +135,27 @@
static void ev4_cpu_initfn(Object *obj)
{
- AlphaCPU *cpu = ALPHA_CPU(obj);
- CPUAlphaState *env = &cpu->env;
-
- env->implver = IMPLVER_2106x;
+ cpu_env(CPU(obj))->implver = IMPLVER_2106x;
}
static void ev5_cpu_initfn(Object *obj)
{
- AlphaCPU *cpu = ALPHA_CPU(obj);
- CPUAlphaState *env = &cpu->env;
-
- env->implver = IMPLVER_21164;
+ cpu_env(CPU(obj))->implver = IMPLVER_21164;
}
static void ev56_cpu_initfn(Object *obj)
{
- AlphaCPU *cpu = ALPHA_CPU(obj);
- CPUAlphaState *env = &cpu->env;
-
- env->amask |= AMASK_BWX;
+ cpu_env(CPU(obj))->amask |= AMASK_BWX;
}
static void pca56_cpu_initfn(Object *obj)
{
- AlphaCPU *cpu = ALPHA_CPU(obj);
- CPUAlphaState *env = &cpu->env;
-
- env->amask |= AMASK_MVI;
+ cpu_env(CPU(obj))->amask |= AMASK_MVI;
}
static void ev6_cpu_initfn(Object *obj)
{
- AlphaCPU *cpu = ALPHA_CPU(obj);
- CPUAlphaState *env = &cpu->env;
+ CPUAlphaState *env = cpu_env(CPU(obj));
env->implver = IMPLVER_21264;
env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP;
@@ -176,16 +163,12 @@
static void ev67_cpu_initfn(Object *obj)
{
- AlphaCPU *cpu = ALPHA_CPU(obj);
- CPUAlphaState *env = &cpu->env;
-
- env->amask |= AMASK_CIX | AMASK_PREFETCH;
+ cpu_env(CPU(obj))->amask |= AMASK_CIX | AMASK_PREFETCH;
}
static void alpha_cpu_initfn(Object *obj)
{
- AlphaCPU *cpu = ALPHA_CPU(obj);
- CPUAlphaState *env = &cpu->env;
+ CPUAlphaState *env = cpu_env(CPU(obj));
env->lock_addr = -1;
#if defined(CONFIG_USER_ONLY)
diff --git a/target/alpha/gdbstub.c b/target/alpha/gdbstub.c
index 0f8fa15..13694fd 100644
--- a/target/alpha/gdbstub.c
+++ b/target/alpha/gdbstub.c
@@ -23,8 +23,7 @@
int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- AlphaCPU *cpu = ALPHA_CPU(cs);
- CPUAlphaState *env = &cpu->env;
+ CPUAlphaState *env = cpu_env(cs);
uint64_t val;
CPU_DoubleU d;
@@ -59,8 +58,7 @@
int alpha_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- AlphaCPU *cpu = ALPHA_CPU(cs);
- CPUAlphaState *env = &cpu->env;
+ CPUAlphaState *env = cpu_env(cs);
target_ulong tmp = ldtul_p(mem_buf);
CPU_DoubleU d;
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index 970c869..d6d4353 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -286,11 +286,10 @@
hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
- AlphaCPU *cpu = ALPHA_CPU(cs);
target_ulong phys;
int prot, fail;
- fail = get_physical_address(&cpu->env, addr, 0, 0, &phys, &prot);
+ fail = get_physical_address(cpu_env(cs), addr, 0, 0, &phys, &prot);
return (fail >= 0 ? -1 : phys);
}
@@ -298,8 +297,7 @@
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
- AlphaCPU *cpu = ALPHA_CPU(cs);
- CPUAlphaState *env = &cpu->env;
+ CPUAlphaState *env = cpu_env(cs);
target_ulong phys;
int prot, fail;
@@ -325,8 +323,7 @@
void alpha_cpu_do_interrupt(CPUState *cs)
{
- AlphaCPU *cpu = ALPHA_CPU(cs);
- CPUAlphaState *env = &cpu->env;
+ CPUAlphaState *env = cpu_env(cs);
int i = cs->exception_index;
if (qemu_loglevel_mask(CPU_LOG_INT)) {
@@ -435,8 +432,7 @@
bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
- AlphaCPU *cpu = ALPHA_CPU(cs);
- CPUAlphaState *env = &cpu->env;
+ CPUAlphaState *env = cpu_env(cs);
int idx = -1;
/* We never take interrupts while in PALmode. */
@@ -487,8 +483,7 @@
"a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
"t10", "t11", "ra", "t12", "at", "gp", "sp"
};
- AlphaCPU *cpu = ALPHA_CPU(cs);
- CPUAlphaState *env = &cpu->env;
+ CPUAlphaState *env = cpu_env(cs);
int i;
qemu_fprintf(f, "PC " TARGET_FMT_lx " PS %02x\n",
diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c
index a39b52c..872955f 100644
--- a/target/alpha/mem_helper.c
+++ b/target/alpha/mem_helper.c
@@ -42,18 +42,14 @@
void alpha_cpu_record_sigbus(CPUState *cs, vaddr addr,
MMUAccessType access_type, uintptr_t retaddr)
{
- AlphaCPU *cpu = ALPHA_CPU(cs);
- CPUAlphaState *env = &cpu->env;
-
- do_unaligned_access(env, addr, retaddr);
+ do_unaligned_access(cpu_env(cs), addr, retaddr);
}
#else
void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
- AlphaCPU *cpu = ALPHA_CPU(cs);
- CPUAlphaState *env = &cpu->env;
+ CPUAlphaState *env = cpu_env(cs);
do_unaligned_access(env, addr, retaddr);
cs->exception_index = EXCP_UNALIGN;
@@ -67,8 +63,7 @@
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr)
{
- AlphaCPU *cpu = ALPHA_CPU(cs);
- CPUAlphaState *env = &cpu->env;
+ CPUAlphaState *env = cpu_env(cs);
env->trap_arg0 = addr;
env->trap_arg1 = access_type == MMU_DATA_STORE ? 1 : 0;
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 882cf6c..a97cd54 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2903,8 +2903,8 @@
static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUAlphaState *env = cpu_env(cpu);
- uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next);
+ uint32_t insn = translator_ldl(cpu_env(cpu), &ctx->base,
+ ctx->base.pc_next);
ctx->base.pc_next += 4;
ctx->base.is_jmp = translate_one(ctx, insn);
diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c
index 2250cd7..3cc8cc7 100644
--- a/target/arm/arm-qmp-cmds.c
+++ b/target/arm/arm-qmp-cmds.c
@@ -28,7 +28,6 @@
#include "qapi/qobject-input-visitor.h"
#include "qapi/qapi-commands-machine-target.h"
#include "qapi/qapi-commands-misc-target.h"
-#include "qapi/qmp/qerror.h"
#include "qapi/qmp/qdict.h"
#include "qom/qom-qobject.h"
@@ -104,7 +103,7 @@
Error **errp)
{
CpuModelExpansionInfo *expansion_info;
- const QDict *qdict_in = NULL;
+ const QDict *qdict_in;
QDict *qdict_out;
ObjectClass *oc;
Object *obj;
@@ -151,27 +150,20 @@
}
}
- if (model->props) {
- qdict_in = qobject_to(QDict, model->props);
- if (!qdict_in) {
- error_setg(errp, QERR_INVALID_PARAMETER_TYPE, "props", "dict");
- return NULL;
- }
- }
-
obj = object_new(object_class_get_name(oc));
- if (qdict_in) {
+ if (model->props) {
Visitor *visitor;
Error *err = NULL;
visitor = qobject_input_visitor_new(model->props);
- if (!visit_start_struct(visitor, NULL, NULL, 0, errp)) {
+ if (!visit_start_struct(visitor, "model.props", NULL, 0, errp)) {
visit_free(visitor);
object_unref(obj);
return NULL;
}
+ qdict_in = qobject_to(QDict, model->props);
i = 0;
while ((name = cpu_model_advertised_features[i++]) != NULL) {
if (qdict_get(qdict_in, name)) {
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f3ed79c..ab8d007 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -214,9 +214,9 @@
static void arm_cpu_reset_hold(Object *obj)
{
- CPUState *s = CPU(obj);
- ARMCPU *cpu = ARM_CPU(s);
- ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
+ CPUState *cs = CPU(obj);
+ ARMCPU *cpu = ARM_CPU(cs);
+ ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
CPUARMState *env = &cpu->env;
if (acc->parent_phases.hold) {
@@ -233,7 +233,7 @@
env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
- cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON;
+ cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON;
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
@@ -438,7 +438,7 @@
/* Load the initial SP and PC from offset 0 and 4 in the vector table */
vecbase = env->v7m.vecbase[env->v7m.secure];
- rom = rom_ptr_for_as(s->as, vecbase, 8);
+ rom = rom_ptr_for_as(cs->as, vecbase, 8);
if (rom) {
/* Address zero is covered by ROM which hasn't yet been
* copied into physical memory.
@@ -451,8 +451,8 @@
* it got copied into memory. In the latter case, rom_ptr
* will return a NULL pointer and we should use ldl_phys instead.
*/
- initial_msp = ldl_phys(s->as, vecbase);
- initial_pc = ldl_phys(s->as, vecbase + 4);
+ initial_msp = ldl_phys(cs->as, vecbase);
+ initial_pc = ldl_phys(cs->as, vecbase + 4);
}
qemu_log_mask(CPU_LOG_INT,
@@ -2095,7 +2095,7 @@
* We rely on no XScale CPU having VFP so we can use the same bits in the
* TB flags field for VECSTRIDE and XSCALE_CPAR.
*/
- assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) ||
+ assert(arm_feature(env, ARM_FEATURE_AARCH64) ||
!cpu_isar_feature(aa32_vfp_simd, cpu) ||
!arm_feature(env, ARM_FEATURE_XSCALE));
@@ -2145,7 +2145,7 @@
}
if (cpu->cfgend) {
- if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
+ if (arm_feature(env, ARM_FEATURE_V7)) {
cpu->reset_sctlr |= SCTLR_EE;
} else {
cpu->reset_sctlr |= SCTLR_B;
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 8181303..ab85d62 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -1888,7 +1888,7 @@
cpu->psci_version = QEMU_PSCI_VERSION_0_2;
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
}
- if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+ if (!arm_feature(env, ARM_FEATURE_AARCH64)) {
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
}
if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 9d7dbae..b2b39b2 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -773,7 +773,7 @@
env->irq_line_state = UINT32_MAX;
if (!kvm_enabled()) {
- pmu_op_start(&cpu->env);
+ pmu_op_start(env);
}
return 0;
@@ -871,11 +871,11 @@
}
if (!kvm_enabled()) {
- pmu_op_finish(&cpu->env);
+ pmu_op_finish(env);
}
if (tcg_enabled()) {
- arm_rebuild_hflags(&cpu->env);
+ arm_rebuild_hflags(env);
}
return 0;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index a50170b..45ee1b5 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -43,11 +43,8 @@
static bool avr_cpu_has_work(CPUState *cs)
{
- AVRCPU *cpu = AVR_CPU(cs);
- CPUAVRState *env = &cpu->env;
-
return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET))
- && cpu_interrupts_enabled(env);
+ && cpu_interrupts_enabled(cpu_env(cs));
}
static int avr_cpu_mmu_index(CPUState *cs, bool ifetch)
@@ -58,28 +55,22 @@
static void avr_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
- AVRCPU *cpu = AVR_CPU(cs);
- CPUAVRState *env = &cpu->env;
-
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
- env->pc_w = tb->pc / 2; /* internally PC points to words */
+ cpu_env(cs)->pc_w = tb->pc / 2; /* internally PC points to words */
}
static void avr_restore_state_to_opc(CPUState *cs,
const TranslationBlock *tb,
const uint64_t *data)
{
- AVRCPU *cpu = AVR_CPU(cs);
- CPUAVRState *env = &cpu->env;
-
- env->pc_w = data[0];
+ cpu_env(cs)->pc_w = data[0];
}
static void avr_cpu_reset_hold(Object *obj)
{
CPUState *cs = CPU(obj);
AVRCPU *cpu = AVR_CPU(cs);
- AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
+ AVRCPUClass *mcc = AVR_CPU_GET_CLASS(obj);
CPUAVRState *env = &cpu->env;
if (mcc->parent_phases.hold) {
@@ -170,8 +161,7 @@
static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
- AVRCPU *cpu = AVR_CPU(cs);
- CPUAVRState *env = &cpu->env;
+ CPUAVRState *env = cpu_env(cs);
int i;
qemu_fprintf(f, "\n");
@@ -281,8 +271,7 @@
*/
static void avr_avr5_initfn(Object *obj)
{
- AVRCPU *cpu = AVR_CPU(obj);
- CPUAVRState *env = &cpu->env;
+ CPUAVRState *env = cpu_env(CPU(obj));
set_avr_feature(env, AVR_FEATURE_LPM);
set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
@@ -310,8 +299,7 @@
*/
static void avr_avr51_initfn(Object *obj)
{
- AVRCPU *cpu = AVR_CPU(obj);
- CPUAVRState *env = &cpu->env;
+ CPUAVRState *env = cpu_env(CPU(obj));
set_avr_feature(env, AVR_FEATURE_LPM);
set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
@@ -340,8 +328,7 @@
*/
static void avr_avr6_initfn(Object *obj)
{
- AVRCPU *cpu = AVR_CPU(obj);
- CPUAVRState *env = &cpu->env;
+ CPUAVRState *env = cpu_env(CPU(obj));
set_avr_feature(env, AVR_FEATURE_LPM);
set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
diff --git a/target/avr/gdbstub.c b/target/avr/gdbstub.c
index 150344d..2eeee2b 100644
--- a/target/avr/gdbstub.c
+++ b/target/avr/gdbstub.c
@@ -23,8 +23,7 @@
int avr_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- AVRCPU *cpu = AVR_CPU(cs);
- CPUAVRState *env = &cpu->env;
+ CPUAVRState *env = cpu_env(cs);
/* R */
if (n < 32) {
@@ -53,8 +52,7 @@
int avr_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- AVRCPU *cpu = AVR_CPU(cs);
- CPUAVRState *env = &cpu->env;
+ CPUAVRState *env = cpu_env(cs);
/* R */
if (n < 32) {
diff --git a/target/avr/helper.c b/target/avr/helper.c
index fdc9884..eeca415 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -30,8 +30,7 @@
bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
- AVRCPU *cpu = AVR_CPU(cs);
- CPUAVRState *env = &cpu->env;
+ CPUAVRState *env = cpu_env(cs);
/*
* We cannot separate a skip from the next instruction,
@@ -69,8 +68,7 @@
void avr_cpu_do_interrupt(CPUState *cs)
{
- AVRCPU *cpu = AVR_CPU(cs);
- CPUAVRState *env = &cpu->env;
+ CPUAVRState *env = cpu_env(cs);
uint32_t ret = env->pc_w;
int vector = 0;
@@ -144,9 +142,7 @@
if (probe) {
page_size = 1;
} else {
- AVRCPU *cpu = AVR_CPU(cs);
- CPUAVRState *env = &cpu->env;
- env->fullacc = 1;
+ cpu_env(cs)->fullacc = 1;
cpu_loop_exit_restore(cs, retaddr);
}
}
diff --git a/target/avr/translate.c b/target/avr/translate.c
index e5dd057..87e2bd5 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -2657,11 +2657,10 @@
static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUAVRState *env = cpu_env(cs);
uint32_t tb_flags = ctx->base.tb->flags;
ctx->cs = cs;
- ctx->env = env;
+ ctx->env = cpu_env(cs);
ctx->npc = ctx->base.pc_first / 2;
ctx->skip_cond = TCG_COND_NEVER;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 163fb05..eb4bddc 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -63,10 +63,9 @@
static void cris_cpu_reset_hold(Object *obj)
{
- CPUState *s = CPU(obj);
- CRISCPU *cpu = CRIS_CPU(s);
- CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
- CPUCRISState *env = &cpu->env;
+ CPUState *cs = CPU(obj);
+ CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
+ CPUCRISState *env = cpu_env(cs);
uint32_t vr;
if (ccc->parent_phases.hold) {
@@ -147,10 +146,7 @@
static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
{
- CRISCPU *cc = CRIS_CPU(cpu);
- CPUCRISState *env = &cc->env;
-
- if (env->pregs[PR_VR] != 32) {
+ if (cpu_env(cpu)->pregs[PR_VR] != 32) {
info->mach = bfd_mach_cris_v0_v10;
info->print_insn = print_insn_crisv10;
} else {
diff --git a/target/cris/gdbstub.c b/target/cris/gdbstub.c
index 25c0ca3..9e87069 100644
--- a/target/cris/gdbstub.c
+++ b/target/cris/gdbstub.c
@@ -23,8 +23,7 @@
int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- CRISCPU *cpu = CRIS_CPU(cs);
- CPUCRISState *env = &cpu->env;
+ CPUCRISState *env = cpu_env(cs);
if (n < 15) {
return gdb_get_reg32(mem_buf, env->regs[n]);
@@ -55,8 +54,7 @@
int cris_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- CRISCPU *cpu = CRIS_CPU(cs);
- CPUCRISState *env = &cpu->env;
+ CPUCRISState *env = cpu_env(cs);
uint8_t srs;
srs = env->pregs[PR_SRS];
@@ -90,8 +88,7 @@
int cris_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- CRISCPU *cpu = CRIS_CPU(cs);
- CPUCRISState *env = &cpu->env;
+ CPUCRISState *env = cpu_env(cs);
uint32_t tmp;
if (n > 49) {
diff --git a/target/cris/helper.c b/target/cris/helper.c
index c0bf987..1c3f868 100644
--- a/target/cris/helper.c
+++ b/target/cris/helper.c
@@ -53,8 +53,7 @@
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
- CRISCPU *cpu = CRIS_CPU(cs);
- CPUCRISState *env = &cpu->env;
+ CPUCRISState *env = cpu_env(cs);
struct cris_mmu_result res;
int prot, miss;
target_ulong phy;
@@ -97,8 +96,7 @@
void crisv10_cpu_do_interrupt(CPUState *cs)
{
- CRISCPU *cpu = CRIS_CPU(cs);
- CPUCRISState *env = &cpu->env;
+ CPUCRISState *env = cpu_env(cs);
int ex_vec = -1;
D_LOG("exception index=%d interrupt_req=%d\n",
@@ -159,8 +157,7 @@
void cris_cpu_do_interrupt(CPUState *cs)
{
- CRISCPU *cpu = CRIS_CPU(cs);
- CPUCRISState *env = &cpu->env;
+ CPUCRISState *env = cpu_env(cs);
int ex_vec = -1;
D_LOG("exception index=%d interrupt_req=%d\n",
@@ -262,8 +259,7 @@
bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
- CRISCPU *cpu = CRIS_CPU(cs);
- CPUCRISState *env = &cpu->env;
+ CPUCRISState *env = cpu_env(cs);
bool ret = false;
if (interrupt_request & CPU_INTERRUPT_HARD
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 8f74b6c..b3a4d61 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3002,7 +3002,6 @@
static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUCRISState *env = cpu_env(cs);
unsigned int insn_len;
/* Pretty disas. */
@@ -3010,7 +3009,7 @@
dc->clear_x = 1;
- insn_len = dc->decoder(env, dc);
+ insn_len = dc->decoder(cpu_env(cs), dc);
dc->ppc = dc->pc;
dc->pc += insn_len;
dc->base.pc_next += insn_len;
@@ -3176,8 +3175,7 @@
void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
- CRISCPU *cpu = CRIS_CPU(cs);
- CPUCRISState *env = &cpu->env;
+ CPUCRISState *env = cpu_env(cs);
const char * const *regnames;
const char * const *pregnames;
int i;
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index a10d87b..3a716b9 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -236,10 +236,7 @@
static void hexagon_dump_state(CPUState *cs, FILE *f, int flags)
{
- HexagonCPU *cpu = HEXAGON_CPU(cs);
- CPUHexagonState *env = &cpu->env;
-
- hexagon_dump(env, f, flags);
+ hexagon_dump(cpu_env(cs), f, flags);
}
void hexagon_debug(CPUHexagonState *env)
@@ -249,25 +246,19 @@
static void hexagon_cpu_set_pc(CPUState *cs, vaddr value)
{
- HexagonCPU *cpu = HEXAGON_CPU(cs);
- CPUHexagonState *env = &cpu->env;
- env->gpr[HEX_REG_PC] = value;
+ cpu_env(cs)->gpr[HEX_REG_PC] = value;
}
static vaddr hexagon_cpu_get_pc(CPUState *cs)
{
- HexagonCPU *cpu = HEXAGON_CPU(cs);
- CPUHexagonState *env = &cpu->env;
- return env->gpr[HEX_REG_PC];
+ return cpu_env(cs)->gpr[HEX_REG_PC];
}
static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
- HexagonCPU *cpu = HEXAGON_CPU(cs);
- CPUHexagonState *env = &cpu->env;
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
- env->gpr[HEX_REG_PC] = tb->pc;
+ cpu_env(cs)->gpr[HEX_REG_PC] = tb->pc;
}
static bool hexagon_cpu_has_work(CPUState *cs)
@@ -279,18 +270,14 @@
const TranslationBlock *tb,
const uint64_t *data)
{
- HexagonCPU *cpu = HEXAGON_CPU(cs);
- CPUHexagonState *env = &cpu->env;
-
- env->gpr[HEX_REG_PC] = data[0];
+ cpu_env(cs)->gpr[HEX_REG_PC] = data[0];
}
static void hexagon_cpu_reset_hold(Object *obj)
{
CPUState *cs = CPU(obj);
- HexagonCPU *cpu = HEXAGON_CPU(cs);
- HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(cpu);
- CPUHexagonState *env = &cpu->env;
+ HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(obj);
+ CPUHexagonState *env = cpu_env(cs);
if (mcc->parent_phases.hold) {
mcc->parent_phases.hold(obj);
diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c
index 6007e64..502c698 100644
--- a/target/hexagon/gdbstub.c
+++ b/target/hexagon/gdbstub.c
@@ -22,8 +22,7 @@
int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- HexagonCPU *cpu = HEXAGON_CPU(cs);
- CPUHexagonState *env = &cpu->env;
+ CPUHexagonState *env = cpu_env(cs);
if (n == HEX_REG_P3_0_ALIASED) {
uint32_t p3_0 = 0;
@@ -42,8 +41,7 @@
int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- HexagonCPU *cpu = HEXAGON_CPU(cs);
- CPUHexagonState *env = &cpu->env;
+ CPUHexagonState *env = cpu_env(cs);
if (n == HEX_REG_P3_0_ALIASED) {
uint32_t p3_0 = ldtul_p(mem_buf);
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 3fc895c..80f51e7 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -538,7 +538,6 @@
/* Purge (Insn/Data) TLB. */
static void ptlb_work(CPUState *cpu, run_on_cpu_data data)
{
- CPUHPPAState *env = cpu_env(cpu);
vaddr start = data.target_ptr;
vaddr end;
@@ -552,7 +551,7 @@
end = (vaddr)TARGET_PAGE_SIZE << (2 * end);
end = start + end - 1;
- hppa_flush_tlb_range(env, start, end);
+ hppa_flush_tlb_range(cpu_env(cpu), start, end);
}
/* This is local to the current cpu. */
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 01f3188..eb2046c 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3811,8 +3811,7 @@
#ifndef CONFIG_USER_ONLY
if (ctx->tb_flags & PSW_C) {
- CPUHPPAState *env = cpu_env(ctx->cs);
- int type = hppa_artype_for_page(env, ctx->base.pc_next);
+ int type = hppa_artype_for_page(cpu_env(ctx->cs), ctx->base.pc_next);
/* If we could not find a TLB entry, then we need to generate an
ITLB miss exception so the kernel will provide it.
The resulting TLB fill operation will invalidate this TB and
diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c
index 7422096..3f9093d 100644
--- a/target/i386/cpu-sysemu.c
+++ b/target/i386/cpu-sysemu.c
@@ -25,6 +25,7 @@
#include "qapi/error.h"
#include "qapi/qapi-visit-run-state.h"
#include "qapi/qmp/qdict.h"
+#include "qapi/qobject-input-visitor.h"
#include "qom/qom-qobject.h"
#include "qapi/qapi-commands-machine-target.h"
#include "hw/qdev-properties.h"
@@ -129,20 +130,36 @@
}
}
-static void object_apply_props(Object *obj, QDict *props, Error **errp)
+static void object_apply_props(Object *obj, QObject *props,
+ const char *props_arg_name, Error **errp)
{
+ Visitor *visitor;
+ QDict *qdict;
const QDictEntry *prop;
- for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
- if (!object_property_set_qobject(obj, qdict_entry_key(prop),
- qdict_entry_value(prop), errp)) {
- break;
+ visitor = qobject_input_visitor_new(props);
+ if (!visit_start_struct(visitor, props_arg_name, NULL, 0, errp)) {
+ visit_free(visitor);
+ return;
+ }
+
+ qdict = qobject_to(QDict, props);
+ for (prop = qdict_first(qdict); prop; prop = qdict_next(qdict, prop)) {
+ if (!object_property_set(obj, qdict_entry_key(prop),
+ visitor, errp)) {
+ goto out;
}
}
+
+ visit_check_struct(visitor, errp);
+out:
+ visit_end_struct(visitor, NULL);
+ visit_free(visitor);
}
/* Create X86CPU object according to model+props specification */
-static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
+static X86CPU *x86_cpu_from_model(const char *model, QObject *props,
+ const char *props_arg_name, Error **errp)
{
X86CPU *xc = NULL;
X86CPUClass *xcc;
@@ -156,7 +173,7 @@
xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
if (props) {
- object_apply_props(OBJECT(xc), props, &err);
+ object_apply_props(OBJECT(xc), props, props_arg_name, &err);
if (err) {
goto out;
}
@@ -187,8 +204,7 @@
QDict *props = NULL;
const char *base_name;
- xc = x86_cpu_from_model(model->name, qobject_to(QDict, model->props),
- &err);
+ xc = x86_cpu_from_model(model->name, model->props, "model.props", &err);
if (err) {
goto out;
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 2666ef3..9a210d8 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6695,9 +6695,9 @@
static void x86_cpu_reset_hold(Object *obj)
{
- CPUState *s = CPU(obj);
- X86CPU *cpu = X86_CPU(s);
- X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
+ CPUState *cs = CPU(obj);
+ X86CPU *cpu = X86_CPU(cs);
+ X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
CPUX86State *env = &cpu->env;
target_ulong cr4;
uint64_t xcr0;
@@ -6785,8 +6785,8 @@
memset(env->dr, 0, sizeof(env->dr));
env->dr[6] = DR6_FIXED_1;
env->dr[7] = DR7_FIXED_1;
- cpu_breakpoint_remove_all(s, BP_CPU);
- cpu_watchpoint_remove_all(s, BP_CPU);
+ cpu_breakpoint_remove_all(cs, BP_CPU);
+ cpu_watchpoint_remove_all(cs, BP_CPU);
cr4 = 0;
xcr0 = XSTATE_FP_MASK;
@@ -6837,9 +6837,9 @@
env->triple_fault_pending = false;
#if !defined(CONFIG_USER_ONLY)
/* We hard-wire the BSP to the first CPU. */
- apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
+ apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0);
- s->halted = !cpu_is_bsp(cpu);
+ cs->halted = !cpu_is_bsp(cpu);
if (kvm_enabled()) {
kvm_arch_reset_vcpu(cpu);
diff --git a/target/i386/hvf/x86.c b/target/i386/hvf/x86.c
index 8ceea63..80e3613 100644
--- a/target/i386/hvf/x86.c
+++ b/target/i386/hvf/x86.c
@@ -46,7 +46,7 @@
return ar;
}*/
-bool x86_read_segment_descriptor(struct CPUState *cpu,
+bool x86_read_segment_descriptor(CPUState *cpu,
struct x86_segment_descriptor *desc,
x68_segment_selector sel)
{
@@ -76,7 +76,7 @@
return true;
}
-bool x86_write_segment_descriptor(struct CPUState *cpu,
+bool x86_write_segment_descriptor(CPUState *cpu,
struct x86_segment_descriptor *desc,
x68_segment_selector sel)
{
@@ -99,7 +99,7 @@
return true;
}
-bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc,
+bool x86_read_call_gate(CPUState *cpu, struct x86_call_gate *idt_desc,
int gate)
{
target_ulong base = rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_BASE);
@@ -115,30 +115,30 @@
return true;
}
-bool x86_is_protected(struct CPUState *cpu)
+bool x86_is_protected(CPUState *cpu)
{
uint64_t cr0 = rvmcs(cpu->accel->fd, VMCS_GUEST_CR0);
return cr0 & CR0_PE_MASK;
}
-bool x86_is_real(struct CPUState *cpu)
+bool x86_is_real(CPUState *cpu)
{
return !x86_is_protected(cpu);
}
-bool x86_is_v8086(struct CPUState *cpu)
+bool x86_is_v8086(CPUState *cpu)
{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
return x86_is_protected(cpu) && (env->eflags & VM_MASK);
}
-bool x86_is_long_mode(struct CPUState *cpu)
+bool x86_is_long_mode(CPUState *cpu)
{
return rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA;
}
-bool x86_is_long64_mode(struct CPUState *cpu)
+bool x86_is_long64_mode(CPUState *cpu)
{
struct vmx_segment desc;
vmx_read_segment_descriptor(cpu, &desc, R_CS);
@@ -146,24 +146,24 @@
return x86_is_long_mode(cpu) && ((desc.ar >> 13) & 1);
}
-bool x86_is_paging_mode(struct CPUState *cpu)
+bool x86_is_paging_mode(CPUState *cpu)
{
uint64_t cr0 = rvmcs(cpu->accel->fd, VMCS_GUEST_CR0);
return cr0 & CR0_PG_MASK;
}
-bool x86_is_pae_enabled(struct CPUState *cpu)
+bool x86_is_pae_enabled(CPUState *cpu)
{
uint64_t cr4 = rvmcs(cpu->accel->fd, VMCS_GUEST_CR4);
return cr4 & CR4_PAE_MASK;
}
-target_ulong linear_addr(struct CPUState *cpu, target_ulong addr, X86Seg seg)
+target_ulong linear_addr(CPUState *cpu, target_ulong addr, X86Seg seg)
{
return vmx_read_segment_base(cpu, seg) + addr;
}
-target_ulong linear_addr_size(struct CPUState *cpu, target_ulong addr, int size,
+target_ulong linear_addr_size(CPUState *cpu, target_ulong addr, int size,
X86Seg seg)
{
switch (size) {
@@ -179,7 +179,7 @@
return linear_addr(cpu, addr, seg);
}
-target_ulong linear_rip(struct CPUState *cpu, target_ulong rip)
+target_ulong linear_rip(CPUState *cpu, target_ulong rip)
{
return linear_addr(cpu, rip, R_CS);
}
diff --git a/target/i386/hvf/x86.h b/target/i386/hvf/x86.h
index 947b98d..3570f29 100644
--- a/target/i386/hvf/x86.h
+++ b/target/i386/hvf/x86.h
@@ -248,30 +248,30 @@
#define BH(cpu) RH(cpu, R_EBX)
/* deal with GDT/LDT descriptors in memory */
-bool x86_read_segment_descriptor(struct CPUState *cpu,
+bool x86_read_segment_descriptor(CPUState *cpu,
struct x86_segment_descriptor *desc,
x68_segment_selector sel);
-bool x86_write_segment_descriptor(struct CPUState *cpu,
+bool x86_write_segment_descriptor(CPUState *cpu,
struct x86_segment_descriptor *desc,
x68_segment_selector sel);
-bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc,
+bool x86_read_call_gate(CPUState *cpu, struct x86_call_gate *idt_desc,
int gate);
/* helpers */
-bool x86_is_protected(struct CPUState *cpu);
-bool x86_is_real(struct CPUState *cpu);
-bool x86_is_v8086(struct CPUState *cpu);
-bool x86_is_long_mode(struct CPUState *cpu);
-bool x86_is_long64_mode(struct CPUState *cpu);
-bool x86_is_paging_mode(struct CPUState *cpu);
-bool x86_is_pae_enabled(struct CPUState *cpu);
+bool x86_is_protected(CPUState *cpu);
+bool x86_is_real(CPUState *cpu);
+bool x86_is_v8086(CPUState *cpu);
+bool x86_is_long_mode(CPUState *cpu);
+bool x86_is_long64_mode(CPUState *cpu);
+bool x86_is_paging_mode(CPUState *cpu);
+bool x86_is_pae_enabled(CPUState *cpu);
enum X86Seg;
-target_ulong linear_addr(struct CPUState *cpu, target_ulong addr, enum X86Seg seg);
-target_ulong linear_addr_size(struct CPUState *cpu, target_ulong addr, int size,
+target_ulong linear_addr(CPUState *cpu, target_ulong addr, enum X86Seg seg);
+target_ulong linear_addr_size(CPUState *cpu, target_ulong addr, int size,
enum X86Seg seg);
-target_ulong linear_rip(struct CPUState *cpu, target_ulong rip);
+target_ulong linear_rip(CPUState *cpu, target_ulong rip);
static inline uint64_t rdtscp(void)
{
diff --git a/target/i386/hvf/x86_descr.c b/target/i386/hvf/x86_descr.c
index c2d2e9e..f33836d 100644
--- a/target/i386/hvf/x86_descr.c
+++ b/target/i386/hvf/x86_descr.c
@@ -67,12 +67,12 @@
return sel;
}
-void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, X86Seg seg)
+void vmx_write_segment_selector(CPUState *cpu, x68_segment_selector selector, X86Seg seg)
{
wvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector, selector.sel);
}
-void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, X86Seg seg)
+void vmx_read_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, X86Seg seg)
{
desc->sel = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector);
desc->base = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].base);
@@ -90,7 +90,9 @@
wvmcs(cpu->accel->fd, sf->ar_bytes, desc->ar);
}
-void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc)
+void x86_segment_descriptor_to_vmx(CPUState *cpu, x68_segment_selector selector,
+ struct x86_segment_descriptor *desc,
+ struct vmx_segment *vmx_desc)
{
vmx_desc->sel = selector.sel;
vmx_desc->base = x86_segment_base(desc);
@@ -107,7 +109,8 @@
desc->type;
}
-void vmx_segment_to_x86_descriptor(struct CPUState *cpu, struct vmx_segment *vmx_desc, struct x86_segment_descriptor *desc)
+void vmx_segment_to_x86_descriptor(CPUState *cpu, struct vmx_segment *vmx_desc,
+ struct x86_segment_descriptor *desc)
{
x86_set_segment_limit(desc, vmx_desc->limit);
x86_set_segment_base(desc, vmx_desc->base);
diff --git a/target/i386/hvf/x86_descr.h b/target/i386/hvf/x86_descr.h
index c356932..9f06014 100644
--- a/target/i386/hvf/x86_descr.h
+++ b/target/i386/hvf/x86_descr.h
@@ -29,29 +29,29 @@
} vmx_segment;
/* deal with vmstate descriptors */
-void vmx_read_segment_descriptor(struct CPUState *cpu,
+void vmx_read_segment_descriptor(CPUState *cpu,
struct vmx_segment *desc, enum X86Seg seg);
void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc,
enum X86Seg seg);
-x68_segment_selector vmx_read_segment_selector(struct CPUState *cpu,
+x68_segment_selector vmx_read_segment_selector(CPUState *cpu,
enum X86Seg seg);
-void vmx_write_segment_selector(struct CPUState *cpu,
+void vmx_write_segment_selector(CPUState *cpu,
x68_segment_selector selector,
enum X86Seg seg);
-uint64_t vmx_read_segment_base(struct CPUState *cpu, enum X86Seg seg);
-void vmx_write_segment_base(struct CPUState *cpu, enum X86Seg seg,
+uint64_t vmx_read_segment_base(CPUState *cpu, enum X86Seg seg);
+void vmx_write_segment_base(CPUState *cpu, enum X86Seg seg,
uint64_t base);
-void x86_segment_descriptor_to_vmx(struct CPUState *cpu,
+void x86_segment_descriptor_to_vmx(CPUState *cpu,
x68_segment_selector selector,
struct x86_segment_descriptor *desc,
struct vmx_segment *vmx_desc);
uint32_t vmx_read_segment_limit(CPUState *cpu, enum X86Seg seg);
uint32_t vmx_read_segment_ar(CPUState *cpu, enum X86Seg seg);
-void vmx_segment_to_x86_descriptor(struct CPUState *cpu,
+void vmx_segment_to_x86_descriptor(CPUState *cpu,
struct vmx_segment *vmx_desc,
struct x86_segment_descriptor *desc);
diff --git a/target/i386/hvf/x86_emu.h b/target/i386/hvf/x86_emu.h
index 4b846ba..8bd9760 100644
--- a/target/i386/hvf/x86_emu.h
+++ b/target/i386/hvf/x86_emu.h
@@ -26,8 +26,8 @@
void init_emu(void);
bool exec_instruction(CPUX86State *env, struct x86_decode *ins);
-void load_regs(struct CPUState *cpu);
-void store_regs(struct CPUState *cpu);
+void load_regs(CPUState *cpu);
+void store_regs(CPUState *cpu);
void simulate_rdmsr(CPUX86State *env);
void simulate_wrmsr(CPUX86State *env);
diff --git a/target/i386/hvf/x86_mmu.c b/target/i386/hvf/x86_mmu.c
index 8cd0862..649074a 100644
--- a/target/i386/hvf/x86_mmu.c
+++ b/target/i386/hvf/x86_mmu.c
@@ -49,7 +49,7 @@
bool exec_access;
};
-static int gpt_top_level(struct CPUState *cpu, bool pae)
+static int gpt_top_level(CPUState *cpu, bool pae)
{
if (!pae) {
return 2;
@@ -73,7 +73,7 @@
}
-static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt,
+static bool get_pt_entry(CPUState *cpu, struct gpt_translation *pt,
int level, bool pae)
{
int index;
@@ -95,7 +95,7 @@
}
/* test page table entry */
-static bool test_pt_entry(struct CPUState *cpu, struct gpt_translation *pt,
+static bool test_pt_entry(CPUState *cpu, struct gpt_translation *pt,
int level, bool *is_large, bool pae)
{
uint64_t pte = pt->pte[level];
@@ -166,7 +166,7 @@
-static bool walk_gpt(struct CPUState *cpu, target_ulong addr, int err_code,
+static bool walk_gpt(CPUState *cpu, target_ulong addr, int err_code,
struct gpt_translation *pt, bool pae)
{
int top_level, level;
@@ -205,7 +205,7 @@
}
-bool mmu_gva_to_gpa(struct CPUState *cpu, target_ulong gva, uint64_t *gpa)
+bool mmu_gva_to_gpa(CPUState *cpu, target_ulong gva, uint64_t *gpa)
{
bool res;
struct gpt_translation pt;
@@ -225,7 +225,7 @@
return false;
}
-void vmx_write_mem(struct CPUState *cpu, target_ulong gva, void *data, int bytes)
+void vmx_write_mem(CPUState *cpu, target_ulong gva, void *data, int bytes)
{
uint64_t gpa;
@@ -246,7 +246,7 @@
}
}
-void vmx_read_mem(struct CPUState *cpu, void *data, target_ulong gva, int bytes)
+void vmx_read_mem(CPUState *cpu, void *data, target_ulong gva, int bytes)
{
uint64_t gpa;
diff --git a/target/i386/hvf/x86_mmu.h b/target/i386/hvf/x86_mmu.h
index 9ae8a54..9447ae0 100644
--- a/target/i386/hvf/x86_mmu.h
+++ b/target/i386/hvf/x86_mmu.h
@@ -36,9 +36,9 @@
#define MMU_PAGE_US (1 << 2)
#define MMU_PAGE_NX (1 << 3)
-bool mmu_gva_to_gpa(struct CPUState *cpu, target_ulong gva, uint64_t *gpa);
+bool mmu_gva_to_gpa(CPUState *cpu, target_ulong gva, uint64_t *gpa);
-void vmx_write_mem(struct CPUState *cpu, target_ulong gva, void *data, int bytes);
-void vmx_read_mem(struct CPUState *cpu, void *data, target_ulong gva, int bytes);
+void vmx_write_mem(CPUState *cpu, target_ulong gva, void *data, int bytes);
+void vmx_read_mem(CPUState *cpu, void *data, target_ulong gva, int bytes);
#endif /* X86_MMU_H */
diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c
index 3b1ef5f..be2c462 100644
--- a/target/i386/hvf/x86hvf.c
+++ b/target/i386/hvf/x86hvf.c
@@ -408,7 +408,7 @@
if (!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
(cs->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->eflags & IF_MASK) && !(info & VMCS_INTR_VALID)) {
- int line = cpu_get_pic_interrupt(&x86cpu->env);
+ int line = cpu_get_pic_interrupt(env);
cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
if (line >= 0) {
wvmcs(cs->accel->fd, VMCS_ENTRY_INTR_INFO, line |
diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c
index cfdca91..49a3a3b 100644
--- a/target/i386/nvmm/nvmm-all.c
+++ b/target/i386/nvmm/nvmm-all.c
@@ -340,7 +340,6 @@
static bool
nvmm_can_take_int(CPUState *cpu)
{
- CPUX86State *env = cpu_env(cpu);
AccelCPUState *qcpu = cpu->accel;
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
struct nvmm_machine *mach = get_nvmm_mach();
@@ -349,7 +348,7 @@
return false;
}
- if (qcpu->int_shadow || !(env->eflags & IF_MASK)) {
+ if (qcpu->int_shadow || !(cpu_env(cpu)->eflags & IF_MASK)) {
struct nvmm_x64_state *state = vcpu->state;
/* Exit on interrupt window. */
@@ -645,13 +644,12 @@
nvmm_handle_halted(struct nvmm_machine *mach, CPUState *cpu,
struct nvmm_vcpu_exit *exit)
{
- CPUX86State *env = cpu_env(cpu);
int ret = 0;
bql_lock();
if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
- (env->eflags & IF_MASK)) &&
+ (cpu_env(cpu)->eflags & IF_MASK)) &&
!(cpu->interrupt_request & CPU_INTERRUPT_NMI)) {
cpu->exception_index = EXCP_HLT;
cpu->halted = true;
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index a726265..31eec70 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -300,7 +300,6 @@
/* X64 Extended Control Registers */
static void whpx_set_xcrs(CPUState *cpu)
{
- CPUX86State *env = cpu_env(cpu);
HRESULT hr;
struct whpx_state *whpx = &whpx_global;
WHV_REGISTER_VALUE xcr0;
@@ -311,7 +310,7 @@
}
/* Only xcr0 is supported by the hypervisor currently */
- xcr0.Reg64 = env->xcr0;
+ xcr0.Reg64 = cpu_env(cpu)->xcr0;
hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
whpx->partition, cpu->cpu_index, &xcr0_name, 1, &xcr0);
if (FAILED(hr)) {
@@ -321,7 +320,6 @@
static int whpx_set_tsc(CPUState *cpu)
{
- CPUX86State *env = cpu_env(cpu);
WHV_REGISTER_NAME tsc_reg = WHvX64RegisterTsc;
WHV_REGISTER_VALUE tsc_val;
HRESULT hr;
@@ -345,7 +343,7 @@
}
}
- tsc_val.Reg64 = env->tsc;
+ tsc_val.Reg64 = cpu_env(cpu)->tsc;
hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
whpx->partition, cpu->cpu_index, &tsc_reg, 1, &tsc_val);
if (FAILED(hr)) {
@@ -556,7 +554,6 @@
static int whpx_get_tsc(CPUState *cpu)
{
- CPUX86State *env = cpu_env(cpu);
WHV_REGISTER_NAME tsc_reg = WHvX64RegisterTsc;
WHV_REGISTER_VALUE tsc_val;
HRESULT hr;
@@ -569,14 +566,13 @@
return -1;
}
- env->tsc = tsc_val.Reg64;
+ cpu_env(cpu)->tsc = tsc_val.Reg64;
return 0;
}
/* X64 Extended Control Registers */
static void whpx_get_xcrs(CPUState *cpu)
{
- CPUX86State *env = cpu_env(cpu);
HRESULT hr;
struct whpx_state *whpx = &whpx_global;
WHV_REGISTER_VALUE xcr0;
@@ -594,7 +590,7 @@
return;
}
- env->xcr0 = xcr0.Reg64;
+ cpu_env(cpu)->xcr0 = xcr0.Reg64;
}
static void whpx_get_registers(CPUState *cpu)
@@ -1400,8 +1396,7 @@
{
if (cpu->vcpu_dirty) {
/* The CPU registers have been modified by other parts of QEMU. */
- CPUArchState *env = cpu_env(cpu);
- return env->eip;
+ return cpu_env(cpu)->eip;
} else if (exit_context_valid) {
/*
* The CPU registers have not been modified by neither other parts
@@ -1439,12 +1434,11 @@
static int whpx_handle_halt(CPUState *cpu)
{
- CPUX86State *env = cpu_env(cpu);
int ret = 0;
bql_lock();
if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
- (env->eflags & IF_MASK)) &&
+ (cpu_env(cpu)->eflags & IF_MASK)) &&
!(cpu->interrupt_request & CPU_INTERRUPT_NMI)) {
cpu->exception_index = EXCP_HLT;
cpu->halted = true;
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index bc26841..f6ffb3a 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -91,18 +91,12 @@
static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
{
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
-
- set_pc(env, value);
+ set_pc(cpu_env(cs), value);
}
static vaddr loongarch_cpu_get_pc(CPUState *cs)
{
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
-
- return env->pc;
+ return cpu_env(cs)->pc;
}
#ifndef CONFIG_USER_ONLY
@@ -157,8 +151,7 @@
#ifndef CONFIG_USER_ONLY
static void loongarch_cpu_do_interrupt(CPUState *cs)
{
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
bool update_badinstr = 1;
int cause = -1;
const char *name;
@@ -308,8 +301,7 @@
MemTxResult response,
uintptr_t retaddr)
{
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
if (access_type == MMU_INST_FETCH) {
do_raise_exception(env, EXCCODE_ADEF, retaddr);
@@ -321,8 +313,7 @@
static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
if (cpu_loongarch_hw_interrupts_enabled(env) &&
cpu_loongarch_hw_interrupts_pending(env)) {
@@ -339,21 +330,15 @@
static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
-
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
- set_pc(env, tb->pc);
+ set_pc(cpu_env(cs), tb->pc);
}
static void loongarch_restore_state_to_opc(CPUState *cs,
const TranslationBlock *tb,
const uint64_t *data)
{
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
-
- set_pc(env, data[0]);
+ set_pc(cpu_env(cs), data[0]);
}
#endif /* CONFIG_TCG */
@@ -362,12 +347,10 @@
#ifdef CONFIG_USER_ONLY
return true;
#else
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
bool has_work = false;
if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
- cpu_loongarch_hw_interrupts_pending(env)) {
+ cpu_loongarch_hw_interrupts_pending(cpu_env(cs))) {
has_work = true;
}
@@ -509,9 +492,8 @@
static void loongarch_cpu_reset_hold(Object *obj)
{
CPUState *cs = CPU(obj);
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu);
- CPULoongArchState *env = &cpu->env;
+ LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(obj);
+ CPULoongArchState *env = cpu_env(cs);
if (lacc->parent_phases.hold) {
lacc->parent_phases.hold(obj);
@@ -694,8 +676,7 @@
void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
int i;
qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index 45f821d..960eec9 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -218,8 +218,7 @@
hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
hwaddr phys_addr;
int prot;
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
index 22c6889..a0e1439 100644
--- a/target/loongarch/gdbstub.c
+++ b/target/loongarch/gdbstub.c
@@ -33,8 +33,7 @@
int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
uint64_t val;
if (0 <= n && n < 32) {
@@ -60,8 +59,7 @@
int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
target_ulong tmp;
int read_length;
int length = 0;
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index c19978a..d630cc3 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -22,7 +22,6 @@
#include "hw/irq.h"
#include "qemu/log.h"
#include "hw/loader.h"
-#include "migration/migration.h"
#include "sysemu/runstate.h"
#include "cpu-csr.h"
#include "kvm_loongarch.h"
@@ -38,8 +37,7 @@
int ret = 0;
int i;
struct kvm_regs regs;
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
/* Get the current register set as KVM seems it */
ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s);
@@ -62,8 +60,7 @@
int ret = 0;
int i;
struct kvm_regs regs;
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
/* Set the registers based on QEMU's view of things */
for (i = 0; i < 32; i++) {
@@ -82,8 +79,7 @@
static int kvm_loongarch_get_csr(CPUState *cs)
{
int ret = 0;
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CRMD),
&env->CSR_CRMD);
@@ -253,8 +249,7 @@
static int kvm_loongarch_put_csr(CPUState *cs, int level)
{
int ret = 0;
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CRMD),
&env->CSR_CRMD);
@@ -430,9 +425,7 @@
{
int ret, i;
struct kvm_fpu fpu;
-
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
ret = kvm_vcpu_ioctl(cs, KVM_GET_FPU, &fpu);
if (ret < 0) {
@@ -456,9 +449,7 @@
{
int ret, i;
struct kvm_fpu fpu;
-
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
fpu.fcsr = env->fcsr0;
fpu.fcc = 0;
@@ -487,8 +478,7 @@
{
int ret = 0;
struct kvm_mp_state mp_state;
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
if (cap_has_mp_state) {
ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
@@ -505,12 +495,8 @@
static int kvm_loongarch_put_mpstate(CPUState *cs)
{
int ret = 0;
-
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
-
struct kvm_mp_state mp_state = {
- .mp_state = env->mp_state
+ .mp_state = cpu_env(cs)->mp_state
};
if (cap_has_mp_state) {
@@ -527,8 +513,7 @@
{
int i, ret = 0;
uint64_t val;
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
for (i = 0; i < 21; i++) {
ret = kvm_get_one_reg(cs, KVM_IOC_CPUCFG(i), &val);
@@ -549,8 +534,7 @@
.attr = 2,
.addr = (uint64_t)&val,
};
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
ret = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr);
@@ -575,8 +559,7 @@
static int kvm_loongarch_put_cpucfg(CPUState *cs)
{
int i, ret = 0;
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
uint64_t val;
for (i = 0; i < 21; i++) {
@@ -758,8 +741,7 @@
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
{
int ret = 0;
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
MemTxAttrs attrs = {};
attrs.requester_id = env_cpu(env)->cpu_index;
diff --git a/target/loongarch/loongarch-qmp-cmds.c b/target/loongarch/loongarch-qmp-cmds.c
index ec33ce8..8721a5e 100644
--- a/target/loongarch/loongarch-qmp-cmds.c
+++ b/target/loongarch/loongarch-qmp-cmds.c
@@ -10,7 +10,6 @@
#include "qapi/error.h"
#include "qapi/qapi-commands-machine-target.h"
#include "cpu.h"
-#include "qapi/qmp/qerror.h"
#include "qapi/qmp/qdict.h"
#include "qapi/qobject-input-visitor.h"
#include "qom/qom-qobject.h"
@@ -48,6 +47,8 @@
CpuModelInfo *model,
Error **errp)
{
+ Visitor *visitor;
+ bool ok;
CpuModelExpansionInfo *expansion_info;
QDict *qdict_out;
ObjectClass *oc;
@@ -60,6 +61,21 @@
return NULL;
}
+ if (model->props) {
+ visitor = qobject_input_visitor_new(model->props);
+ if (!visit_start_struct(visitor, "model.props", NULL, 0, errp)) {
+ visit_free(visitor);
+ return NULL;
+ }
+
+ ok = visit_check_struct(visitor, errp);
+ visit_end_struct(visitor, NULL);
+ visit_free(visitor);
+ if (!ok) {
+ return NULL;
+ }
+ }
+
oc = cpu_class_by_name(TYPE_LOONGARCH_CPU, model->name);
if (!oc) {
error_setg(errp, "The CPU type '%s' is not a recognized LoongArch CPU type",
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index a08c08b..22be031 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -449,8 +449,7 @@
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
- LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- CPULoongArchState *env = &cpu->env;
+ CPULoongArchState *env = cpu_env(cs);
hwaddr physical;
int prot;
int ret;
diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
index 58674cb..7567712 100644
--- a/target/loongarch/tcg/translate.c
+++ b/target/loongarch/tcg/translate.c
@@ -282,10 +282,9 @@
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
- CPULoongArchState *env = cpu_env(cs);
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
+ ctx->opcode = translator_ldl(cpu_env(cs), &ctx->base, ctx->base.pc_next);
if (!decode(ctx, ctx->opcode)) {
qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. "
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index cc6e453..7c8efbb 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -73,10 +73,9 @@
static void m68k_cpu_reset_hold(Object *obj)
{
- CPUState *s = CPU(obj);
- M68kCPU *cpu = M68K_CPU(s);
- M68kCPUClass *mcc = M68K_CPU_GET_CLASS(cpu);
- CPUM68KState *env = &cpu->env;
+ CPUState *cs = CPU(obj);
+ M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj);
+ CPUM68KState *env = cpu_env(cs);
floatx80 nan = floatx80_default_nan(NULL);
int i;
@@ -122,8 +121,7 @@
static void m5206_cpu_initfn(Object *obj)
{
- M68kCPU *cpu = M68K_CPU(obj);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(CPU(obj));
m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
m68k_set_feature(env, M68K_FEATURE_MOVEFROMSR_PRIV);
@@ -132,8 +130,7 @@
/* Base feature set, including isns. for m68k family */
static void m68000_cpu_initfn(Object *obj)
{
- M68kCPU *cpu = M68K_CPU(obj);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(CPU(obj));
m68k_set_feature(env, M68K_FEATURE_M68K);
m68k_set_feature(env, M68K_FEATURE_USP);
@@ -147,8 +144,7 @@
*/
static void m68010_cpu_initfn(Object *obj)
{
- M68kCPU *cpu = M68K_CPU(obj);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(CPU(obj));
m68000_cpu_initfn(obj);
m68k_set_feature(env, M68K_FEATURE_M68010);
@@ -168,8 +164,7 @@
*/
static void m68020_cpu_initfn(Object *obj)
{
- M68kCPU *cpu = M68K_CPU(obj);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(CPU(obj));
m68010_cpu_initfn(obj);
m68k_unset_feature(env, M68K_FEATURE_M68010);
@@ -199,8 +194,7 @@
*/
static void m68030_cpu_initfn(Object *obj)
{
- M68kCPU *cpu = M68K_CPU(obj);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(CPU(obj));
m68020_cpu_initfn(obj);
m68k_unset_feature(env, M68K_FEATURE_M68020);
@@ -226,8 +220,7 @@
*/
static void m68040_cpu_initfn(Object *obj)
{
- M68kCPU *cpu = M68K_CPU(obj);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(CPU(obj));
m68030_cpu_initfn(obj);
m68k_unset_feature(env, M68K_FEATURE_M68030);
@@ -247,8 +240,7 @@
*/
static void m68060_cpu_initfn(Object *obj)
{
- M68kCPU *cpu = M68K_CPU(obj);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(CPU(obj));
m68040_cpu_initfn(obj);
m68k_unset_feature(env, M68K_FEATURE_M68040);
@@ -261,8 +253,7 @@
static void m5208_cpu_initfn(Object *obj)
{
- M68kCPU *cpu = M68K_CPU(obj);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(CPU(obj));
m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC);
@@ -274,8 +265,7 @@
static void cfv4e_cpu_initfn(Object *obj)
{
- M68kCPU *cpu = M68K_CPU(obj);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(CPU(obj));
m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
m68k_set_feature(env, M68K_FEATURE_CF_ISA_B);
@@ -288,8 +278,7 @@
static void any_cpu_initfn(Object *obj)
{
- M68kCPU *cpu = M68K_CPU(obj);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(CPU(obj));
m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
m68k_set_feature(env, M68K_FEATURE_CF_ISA_B);
diff --git a/target/m68k/gdbstub.c b/target/m68k/gdbstub.c
index 1e5f033..15547e2 100644
--- a/target/m68k/gdbstub.c
+++ b/target/m68k/gdbstub.c
@@ -23,8 +23,7 @@
int m68k_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- M68kCPU *cpu = M68K_CPU(cs);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(cs);
if (n < 8) {
/* D0-D7 */
@@ -50,8 +49,7 @@
int m68k_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- M68kCPU *cpu = M68K_CPU(cs);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(cs);
uint32_t tmp;
tmp = ldl_p(mem_buf);
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 1c33995..1a475f0 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -906,8 +906,7 @@
hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
- M68kCPU *cpu = M68K_CPU(cs);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(cs);
hwaddr phys_addr;
int prot;
int access_type;
@@ -955,8 +954,7 @@
MMUAccessType qemu_access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
- M68kCPU *cpu = M68K_CPU(cs);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(cs);
hwaddr physical;
int prot;
int access_type;
@@ -984,7 +982,7 @@
access_type |= ACCESS_SUPER;
}
- ret = get_physical_address(&cpu->env, &physical, &prot,
+ ret = get_physical_address(env, &physical, &prot,
address, access_type, &page_size);
if (likely(ret == 0)) {
tlb_set_page(cs, address & TARGET_PAGE_MASK,
diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c
index b4ffb70..546cff2 100644
--- a/target/m68k/m68k-semi.c
+++ b/target/m68k/m68k-semi.c
@@ -77,8 +77,7 @@
static void m68k_semi_u32_cb(CPUState *cs, uint64_t ret, int err)
{
- M68kCPU *cpu = M68K_CPU(cs);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(cs);
target_ulong args = env->dregs[1];
if (put_user_u32(ret, args) ||
@@ -95,8 +94,7 @@
static void m68k_semi_u64_cb(CPUState *cs, uint64_t ret, int err)
{
- M68kCPU *cpu = M68K_CPU(cs);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(cs);
target_ulong args = env->dregs[1];
if (put_user_u32(ret >> 32, args) ||
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index 956e76e..125f6c1 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -441,10 +441,7 @@
void m68k_cpu_do_interrupt(CPUState *cs)
{
- M68kCPU *cpu = M68K_CPU(cs);
- CPUM68KState *env = &cpu->env;
-
- do_interrupt_all(env, 0);
+ do_interrupt_all(cpu_env(cs), 0);
}
static inline void do_interrupt_m68k_hardirq(CPUM68KState *env)
@@ -457,8 +454,7 @@
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr)
{
- M68kCPU *cpu = M68K_CPU(cs);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(cs);
cpu_restore_state(cs, retaddr);
@@ -511,8 +507,7 @@
bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
- M68kCPU *cpu = M68K_CPU(cs);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(cs);
if (interrupt_request & CPU_INTERRUPT_HARD
&& ((env->sr & SR_I) >> SR_I_SHIFT) < env->pending_level) {
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index d7d5ff4..6ae3df4 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -6100,8 +6100,7 @@
void m68k_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
- M68kCPU *cpu = M68K_CPU(cs);
- CPUM68KState *env = &cpu->env;
+ CPUM68KState *env = cpu_env(cs);
int i;
uint16_t sr;
for (i = 0; i < 8; i++) {
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index e533e7a..96c2b71 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -183,9 +183,9 @@
static void mb_cpu_reset_hold(Object *obj)
{
- CPUState *s = CPU(obj);
- MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
- MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
+ CPUState *cs = CPU(obj);
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(obj);
CPUMBState *env = &cpu->env;
if (mcc->parent_phases.hold) {
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
index eb168d1..09d74e1 100644
--- a/target/microblaze/gdbstub.c
+++ b/target/microblaze/gdbstub.c
@@ -110,9 +110,8 @@
int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
CPUClass *cc = CPU_GET_CLASS(cs);
- CPUMBState *env = &cpu->env;
+ CPUMBState *env = cpu_env(cs);
uint32_t tmp;
if (n > cc->gdb_num_core_regs) {
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 460eee0..d25c9eb 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -252,8 +252,7 @@
bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
- MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
- CPUMBState *env = &cpu->env;
+ CPUMBState *env = cpu_env(cs);
if ((interrupt_request & CPU_INTERRUPT_HARD)
&& (env->msr & MSR_IE)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index a465c2d..4e52ef3 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1630,7 +1630,6 @@
static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
{
DisasContext *dc = container_of(dcb, DisasContext, base);
- CPUMBState *env = cpu_env(cs);
uint32_t ir;
/* TODO: This should raise an exception, not terminate qemu. */
@@ -1641,7 +1640,7 @@
dc->tb_flags_to_set = 0;
- ir = cpu_ldl_code(env, dc->base.pc_next);
+ ir = cpu_ldl_code(cpu_env(cs), dc->base.pc_next);
if (!decode(dc, ir)) {
trap_illegal(dc, true);
}
@@ -1800,8 +1799,7 @@
void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
- MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
- CPUMBState *env = &cpu->env;
+ CPUMBState *env = cpu_env(cs);
uint32_t iflags;
int i;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index d644adb..8d8f690 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -80,8 +80,7 @@
static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int i;
qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
@@ -123,9 +122,7 @@
static void mips_cpu_set_pc(CPUState *cs, vaddr value)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
-
- mips_env_set_pc(&cpu->env, value);
+ mips_env_set_pc(cpu_env(cs), value);
}
static vaddr mips_cpu_get_pc(CPUState *cs)
@@ -137,8 +134,7 @@
static bool mips_cpu_has_work(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
bool has_work = false;
/*
@@ -193,7 +189,7 @@
{
CPUState *cs = CPU(obj);
MIPSCPU *cpu = MIPS_CPU(cs);
- MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
+ MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
CPUMIPSState *env = &cpu->env;
if (mcc->parent_phases.hold) {
@@ -433,10 +429,7 @@
static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
- MIPSCPU *cpu = MIPS_CPU(s);
- CPUMIPSState *env = &cpu->env;
-
- if (!(env->insn_flags & ISA_NANOMIPS32)) {
+ if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) {
#if TARGET_BIG_ENDIAN
info->print_insn = print_insn_big_mips;
#else
diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c
index 62d7b72..169d474 100644
--- a/target/mips/gdbstub.c
+++ b/target/mips/gdbstub.c
@@ -25,8 +25,7 @@
int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
if (n < 32) {
return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
@@ -78,8 +77,7 @@
int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
target_ulong tmp;
tmp = ldtul_p(mem_buf);
diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index 15d0cf9..6c52e59 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -63,8 +63,7 @@
int kvm_arch_init_vcpu(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int ret = 0;
qemu_add_vm_change_state_handler(kvm_mips_update_state, cs);
@@ -460,8 +459,7 @@
*/
static int kvm_mips_save_count(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
uint64_t count_ctl;
int err, ret = 0;
@@ -502,8 +500,7 @@
*/
static int kvm_mips_restore_count(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
uint64_t count_ctl;
int err_dc, err, ret = 0;
@@ -590,8 +587,7 @@
static int kvm_mips_put_fpu_registers(CPUState *cs, int level)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int err, ret = 0;
unsigned int i;
@@ -670,8 +666,7 @@
static int kvm_mips_get_fpu_registers(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int err, ret = 0;
unsigned int i;
@@ -751,8 +746,7 @@
static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int err, ret = 0;
(void)level;
@@ -974,8 +968,7 @@
static int kvm_mips_get_cp0_registers(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int err, ret = 0;
err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
@@ -1181,8 +1174,7 @@
int kvm_arch_put_registers(CPUState *cs, int level)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
struct kvm_regs regs;
int ret;
int i;
@@ -1217,8 +1209,7 @@
int kvm_arch_get_registers(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int ret = 0;
struct kvm_regs regs;
int i;
diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c
index 13c8bc8f..5c5184e 100644
--- a/target/mips/sysemu/physaddr.c
+++ b/target/mips/sysemu/physaddr.c
@@ -230,8 +230,7 @@
hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
hwaddr phys_addr;
int prot;
diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c
index da49a93..13275d1 100644
--- a/target/mips/tcg/exception.c
+++ b/target/mips/tcg/exception.c
@@ -79,8 +79,7 @@
void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
env->active_tc.PC = tb->pc;
diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c
index 98935b5..65403f1 100644
--- a/target/mips/tcg/op_helper.c
+++ b/target/mips/tcg/op_helper.c
@@ -279,8 +279,7 @@
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int error_code = 0;
int excp;
@@ -306,9 +305,8 @@
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
- CPUMIPSState *env = &cpu->env;
+ MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cs);
+ CPUMIPSState *env = cpu_env(cs);
if (access_type == MMU_INST_FETCH) {
do_raise_exception(env, EXCP_IBE, retaddr);
diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/sysemu/special_helper.c
index 518d3fb..5baa253 100644
--- a/target/mips/tcg/sysemu/special_helper.c
+++ b/target/mips/tcg/sysemu/special_helper.c
@@ -90,8 +90,7 @@
bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
if ((env->hflags & MIPS_HFLAG_BMASK) != 0
&& !(cs->tcg_cflags & CF_PCREL) && env->active_tc.PC != tb->pc) {
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
index cdae42f..119eae7 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -906,8 +906,7 @@
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
hwaddr physical;
int prot;
int ret = TLBRET_BADADDR;
@@ -1340,8 +1339,7 @@
bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
if (cpu_mips_hw_interrupts_enabled(env) &&
cpu_mips_hw_interrupts_pending(env)) {
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 3ba2101..06c108c 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -15566,8 +15566,7 @@
const TranslationBlock *tb,
const uint64_t *data)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
env->active_tc.PC = data[0];
env->hflags &= ~MIPS_HFLAG_BMASK;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 0760bf6..679aff5 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -28,28 +28,19 @@
static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
{
- Nios2CPU *cpu = NIOS2_CPU(cs);
- CPUNios2State *env = &cpu->env;
-
- env->pc = value;
+ cpu_env(cs)->pc = value;
}
static vaddr nios2_cpu_get_pc(CPUState *cs)
{
- Nios2CPU *cpu = NIOS2_CPU(cs);
- CPUNios2State *env = &cpu->env;
-
- return env->pc;
+ return cpu_env(cs)->pc;
}
static void nios2_restore_state_to_opc(CPUState *cs,
const TranslationBlock *tb,
const uint64_t *data)
{
- Nios2CPU *cpu = NIOS2_CPU(cs);
- CPUNios2State *env = &cpu->env;
-
- env->pc = data[0];
+ cpu_env(cs)->pc = data[0];
}
static bool nios2_cpu_has_work(CPUState *cs)
@@ -67,7 +58,7 @@
{
CPUState *cs = CPU(obj);
Nios2CPU *cpu = NIOS2_CPU(cs);
- Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(cpu);
+ Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(obj);
CPUNios2State *env = &cpu->env;
if (ncc->parent_phases.hold) {
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index bb3b09e..ac57121 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -287,8 +287,7 @@
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
- Nios2CPU *cpu = NIOS2_CPU(cs);
- CPUNios2State *env = &cpu->env;
+ CPUNios2State *env = cpu_env(cs);
env->ctrl[CR_BADADDR] = addr;
cs->exception_index = EXCP_UNALIGN;
diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c
index 0b84fcb..420702e 100644
--- a/target/nios2/nios2-semi.c
+++ b/target/nios2/nios2-semi.c
@@ -75,8 +75,7 @@
static void nios2_semi_u32_cb(CPUState *cs, uint64_t ret, int err)
{
- Nios2CPU *cpu = NIOS2_CPU(cs);
- CPUNios2State *env = &cpu->env;
+ CPUNios2State *env = cpu_env(cs);
target_ulong args = env->regs[R_ARG1];
if (put_user_u32(ret, args) ||
@@ -93,8 +92,7 @@
static void nios2_semi_u64_cb(CPUState *cs, uint64_t ret, int err)
{
- Nios2CPU *cpu = NIOS2_CPU(cs);
- CPUNios2State *env = &cpu->env;
+ CPUNios2State *env = cpu_env(cs);
target_ulong args = env->regs[R_ARG1];
if (put_user_u32(ret >> 32, args) ||
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 612556b..7ddc6ac 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -970,7 +970,6 @@
static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUNios2State *env = cpu_env(cs);
const Nios2Instruction *instr;
uint32_t code, pc;
uint8_t op;
@@ -980,7 +979,7 @@
dc->base.pc_next = pc + 4;
/* Decode an instruction */
- code = cpu_ldl_code(env, pc);
+ code = cpu_ldl_code(cpu_env(cs), pc);
op = get_opcode(code);
if (unlikely(op >= ARRAY_SIZE(i_type_instructions))) {
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index a3cb80c..33c45db 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -87,9 +87,9 @@
static void openrisc_cpu_reset_hold(Object *obj)
{
- CPUState *s = CPU(obj);
- OpenRISCCPU *cpu = OPENRISC_CPU(s);
- OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
+ CPUState *cs = CPU(obj);
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+ OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(obj);
if (occ->parent_phases.hold) {
occ->parent_phases.hold(obj);
@@ -100,7 +100,7 @@
cpu->env.pc = 0x100;
cpu->env.sr = SR_FO | SR_SM;
cpu->env.lock_addr = -1;
- s->exception_index = -1;
+ cs->exception_index = -1;
cpu_set_fpcsr(&cpu->env, 0);
set_float_detect_tininess(float_tininess_before_rounding,
diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c
index d1074a0..c2a77d5 100644
--- a/target/openrisc/gdbstub.c
+++ b/target/openrisc/gdbstub.c
@@ -23,8 +23,7 @@
int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- OpenRISCCPU *cpu = OPENRISC_CPU(cs);
- CPUOpenRISCState *env = &cpu->env;
+ CPUOpenRISCState *env = cpu_env(cs);
if (n < 32) {
return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n));
@@ -48,9 +47,8 @@
int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUClass *cc = CPU_GET_CLASS(cs);
- CPUOpenRISCState *env = &cpu->env;
+ CPUOpenRISCState *env = cpu_env(cs);
uint32_t tmp;
if (n > cc->gdb_num_core_regs) {
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index d4fdb8c..b3b5b40 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -29,8 +29,7 @@
void openrisc_cpu_do_interrupt(CPUState *cs)
{
- OpenRISCCPU *cpu = OPENRISC_CPU(cs);
- CPUOpenRISCState *env = &cpu->env;
+ CPUOpenRISCState *env = cpu_env(cs);
int exception = cs->exception_index;
env->epcr = env->pc;
@@ -105,8 +104,7 @@
bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
- OpenRISCCPU *cpu = OPENRISC_CPU(cs);
- CPUOpenRISCState *env = &cpu->env;
+ CPUOpenRISCState *env = cpu_env(cs);
int idx = -1;
if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) {
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 785bcb6..23fff46 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1564,8 +1564,7 @@
static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- OpenRISCCPU *cpu = OPENRISC_CPU(cs);
- uint32_t insn = translator_ldl(&cpu->env, &dc->base, dc->base.pc_next);
+ uint32_t insn = translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_next);
if (!decode(dc, insn)) {
gen_illegal_exception(dc);
@@ -1668,8 +1667,7 @@
void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
- OpenRISCCPU *cpu = OPENRISC_CPU(cs);
- CPUOpenRISCState *env = &cpu->env;
+ CPUOpenRISCState *env = cpu_env(cs);
int i;
qemu_fprintf(f, "PC=%08x\n", env->pc);
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index 36e465b..f2301b4 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -728,14 +728,10 @@
"POWER8 v2.0")
POWERPC_DEF("power8nvl_v1.0", CPU_POWERPC_POWER8NVL_v10, POWER8,
"POWER8NVL v1.0")
- POWERPC_DEF("power9_v1.0", CPU_POWERPC_POWER9_DD1, POWER9,
- "POWER9 v1.0")
POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, POWER9,
"POWER9 v2.0")
POWERPC_DEF("power9_v2.2", CPU_POWERPC_POWER9_DD22, POWER9,
"POWER9 v2.2")
- POWERPC_DEF("power10_v1.0", CPU_POWERPC_POWER10_DD1, POWER10,
- "POWER10 v1.0")
POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10,
"POWER10 v2.0")
#endif /* defined (TARGET_PPC64) */
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 0133da4..67e6b2e 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1584,6 +1584,8 @@
uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
+void cpu_ppc_increase_tb_by_offset(CPUPPCState *env, int64_t offset);
+void cpu_ppc_decrease_tb_by_offset(CPUPPCState *env, int64_t offset);
uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
bool ppc_decr_clear_on_delivery(CPUPPCState *env);
@@ -1755,9 +1757,11 @@
#define SPR_PSPB (0x09F)
#define SPR_DPDES (0x0B0)
#define SPR_DAWR0 (0x0B4)
+#define SPR_DAWR1 (0x0B5)
#define SPR_RPR (0x0BA)
#define SPR_CIABR (0x0BB)
#define SPR_DAWRX0 (0x0BC)
+#define SPR_DAWRX1 (0x0BD)
#define SPR_HFSCR (0x0BE)
#define SPR_VRSAVE (0x100)
#define SPR_USPRG0 (0x100)
@@ -1951,6 +1955,12 @@
#define SPR_BOOKE_TLB2CFG (0x2B2)
#define SPR_BOOKE_TLB3CFG (0x2B3)
#define SPR_BOOKE_EPR (0x2BE)
+#define SPR_POWER_USIER2 (0x2E0)
+#define SPR_POWER_USIER3 (0x2E1)
+#define SPR_POWER_UMMCR3 (0x2E2)
+#define SPR_POWER_SIER2 (0x2F0)
+#define SPR_POWER_SIER3 (0x2F1)
+#define SPR_POWER_MMCR3 (0x2F2)
#define SPR_PERF0 (0x300)
#define SPR_RCPU_MI_RBA0 (0x300)
#define SPR_MPC_MI_CTR (0x300)
@@ -2948,6 +2958,7 @@
}
#if !defined(CONFIG_USER_ONLY)
+/* Sort out endianness of interrupt. Depends on the CPU, HV mode, etc. */
static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
{
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 1d3d1db..7e65f08 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5308,6 +5308,38 @@
0x00000000);
}
+static void register_power10_pmu_sup_sprs(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_POWER_MMCR3, "MMCR3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCR3, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_SIER2, "SIER2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_SIER2, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_SIER3, "SIER3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_SIER3, 0x00000000);
+}
+
+static void register_power10_pmu_user_sprs(CPUPPCState *env)
+{
+ spr_register(env, SPR_POWER_UMMCR3, "UMMCR3",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_POWER_USIER2, "USIER2",
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_POWER_USIER3, "USIER3",
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
static void register_power5p_ear_sprs(CPUPPCState *env)
{
/* External access control */
@@ -6350,10 +6382,7 @@
return false;
}
- if ((pvr & 0x0f00) == 0x100) {
- /* DD1.x always matches power9_v1.0 */
- return true;
- } else if ((pvr & 0x0f00) == 0x200) {
+ if ((pvr & 0x0f00) == 0x200) {
if ((pvr & 0xf) < 2) {
/* DD2.0, DD2.1 match power9_v2.0 */
if ((pcc->pvr & 0xf) == 0) {
@@ -6505,6 +6534,8 @@
register_power9_mmu_sprs(env);
register_power10_hash_sprs(env);
register_power10_dexcr_sprs(env);
+ register_power10_pmu_sup_sprs(env);
+ register_power10_pmu_user_sprs(env);
/* FIXME: Filter fields properly based on privilege level */
spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
@@ -6536,7 +6567,7 @@
}
if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
- /* Major DD version matches to power10_v1.0 and power10_v2.0 */
+ /* Major DD version matches power10_v2.0 */
return true;
}
@@ -6576,11 +6607,10 @@
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
- PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 |
+ PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 |
PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_HV) |
- (1ull << MSR_TM) |
(1ull << MSR_VR) |
(1ull << MSR_VSX) |
(1ull << MSR_EE) |
@@ -6620,7 +6650,7 @@
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
- POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
+ POWERPC_FLAG_VSX | POWERPC_FLAG_SCV;
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
}
@@ -7108,9 +7138,9 @@
static void ppc_cpu_reset_hold(Object *obj)
{
- CPUState *s = CPU(obj);
- PowerPCCPU *cpu = POWERPC_CPU(s);
- PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ CPUState *cs = CPU(obj);
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(obj);
CPUPPCState *env = &cpu->env;
target_ulong msr;
int i;
@@ -7159,8 +7189,8 @@
env->nip = env->hreset_vector | env->excp_prefix;
if (tcg_enabled()) {
- cpu_breakpoint_remove_all(s, BP_CPU);
- cpu_watchpoint_remove_all(s, BP_CPU);
+ cpu_breakpoint_remove_all(cs, BP_CPU);
+ cpu_watchpoint_remove_all(cs, BP_CPU);
if (env->mmu_model != POWERPC_MMU_REAL) {
ppc_tlb_invalidate_all(env);
}
@@ -7174,7 +7204,7 @@
env->reserve_addr = (target_ulong)-1ULL;
/* Be sure no exception or interrupt is pending */
env->pending_interrupts = 0;
- s->exception_index = POWERPC_EXCP_NONE;
+ cs->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
ppc_irq_reset(cpu);
@@ -7196,12 +7226,9 @@
static bool ppc_cpu_is_big_endian(CPUState *cs)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
-
cpu_synchronize_state(cs);
- return !FIELD_EX64(env->msr, MSR, LE);
+ return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE);
}
static bool ppc_get_irq_stats(InterruptStatsProvider *obj,
@@ -7288,8 +7315,7 @@
static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
if ((env->hflags >> MSR_LE) & 1) {
info->endian = BFD_ENDIAN_LITTLE;
@@ -7445,8 +7471,7 @@
#define RGPL 4
#define RFPL 4
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
int i;
qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 98952de..80f584f 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -35,7 +35,7 @@
/*****************************************************************************/
/* Exception processing */
-#if !defined(CONFIG_USER_ONLY)
+#ifndef CONFIG_USER_ONLY
static const char *powerpc_excp_name(int excp)
{
@@ -186,7 +186,7 @@
env->error_code);
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
static int powerpc_reset_wakeup(CPUPPCState *env, int excp, target_ulong *msr)
{
/* We no longer are in a PM state */
@@ -380,7 +380,7 @@
}
}
}
-#endif
+#endif /* TARGET_PPC64 */
static void powerpc_reset_excp_state(PowerPCCPU *cpu)
{
@@ -403,9 +403,8 @@
* We don't use hreg_store_msr here as already have treated any
* special case that could occur. Just store MSR and update hflags
*
- * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
- * will prevent setting of the HV bit which some exceptions might need
- * to do.
+ * Note: We *MUST* not use hreg_store_msr() as-is anyway because it will
+ * prevent setting of the HV bit which some exceptions might need to do.
*/
env->nip = vector;
env->msr = msr;
@@ -445,38 +444,26 @@
static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- int srr0, srr1;
+ int srr0 = SPR_SRR0, srr1 = SPR_SRR1;
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
- /*
- * new interrupt handler msr preserves existing ME unless
- * explicitly overridden.
- */
+ /* new interrupt handler msr preserves ME unless explicitly overridden */
new_msr = env->msr & (((target_ulong)1 << MSR_ME));
- /* target registers */
- srr0 = SPR_SRR0;
- srr1 = SPR_SRR1;
-
- /*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later.
- */
+ /* HV emu assistance interrupt only exists on server arch 2.05 or later */
if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
switch (excp) {
@@ -488,7 +475,6 @@
powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
-
srr0 = SPR_40x_SRR2;
srr1 = SPR_40x_SRR3;
break;
@@ -523,7 +509,7 @@
env->spr[SPR_40x_ESR] = ESR_PTR;
break;
default:
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -550,52 +536,41 @@
trace_ppc_excp_print("PIT");
break;
case POWERPC_EXCP_DEBUG: /* Debug interrupt */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
- /* Save PC */
env->spr[srr0] = env->nip;
-
- /* Save MSR */
env->spr[srr1] = msr;
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
- /*
- * new interrupt handler msr preserves existing ME unless
- * explicitly overridden
- */
+ /* new interrupt handler msr preserves ME unless explicitly overridden */
new_msr = env->msr & ((target_ulong)1 << MSR_ME);
- /*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later.
- */
+ /* HV emu assistance interrupt only exists on server arch 2.05 or later */
if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
switch (excp) {
@@ -605,7 +580,6 @@
powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
-
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
@@ -633,11 +607,9 @@
powerpc_reset_excp_state(cpu);
return;
}
-
/*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
+ * NIP always points to the faulting instruction for FP exceptions,
+ * so always use store_next and claim we are precise in the MSR.
*/
msr |= 0x00100000;
break;
@@ -653,7 +625,7 @@
break;
default:
/* Should never occur */
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -675,8 +647,9 @@
break;
case POWERPC_EXCP_RESET: /* System reset exception */
if (FIELD_EX64(env->msr, MSR, POW)) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
- "exception %d with no HV support\n", excp);
+ cpu_abort(env_cpu(env),
+ "Trying to deliver power-saving system reset exception "
+ "%d with no HV support\n", excp);
}
break;
case POWERPC_EXCP_TRACE: /* Trace exception */
@@ -703,60 +676,44 @@
case POWERPC_EXCP_SMI: /* System management interrupt */
case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
- /*
- * Sort out endianness of interrupt, this differs depending on the
- * CPU, the HV mode, etc...
- */
if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
new_msr |= (target_ulong)1 << MSR_LE;
}
-
- /* Save PC */
env->spr[SPR_SRR0] = env->nip;
-
- /* Save MSR */
env->spr[SPR_SRR1] = msr;
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
- /*
- * new interrupt handler msr preserves existing ME unless
- * explicitly overridden
- */
+ /* new interrupt handler msr preserves ME unless explicitly overridden */
new_msr = env->msr & ((target_ulong)1 << MSR_ME);
- /*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later.
- */
+ /* HV emu assistance interrupt only exists on server arch 2.05 or later */
if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
switch (excp) {
@@ -764,7 +721,6 @@
powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
-
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
@@ -792,11 +748,9 @@
powerpc_reset_excp_state(cpu);
return;
}
-
/*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
+ * NIP always points to the faulting instruction for FP exceptions,
+ * so always use store_next and claim we are precise in the MSR.
*/
msr |= 0x00100000;
break;
@@ -812,7 +766,7 @@
break;
default:
/* Should never occur */
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -854,8 +808,9 @@
break;
case POWERPC_EXCP_RESET: /* System reset exception */
if (FIELD_EX64(env->msr, MSR, POW)) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
- "exception %d with no HV support\n", excp);
+ cpu_abort(env_cpu(env),
+ "Trying to deliver power-saving system reset exception "
+ "%d with no HV support\n", excp);
}
break;
case POWERPC_EXCP_TRACE: /* Trace exception */
@@ -864,71 +819,53 @@
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
ppc_excp_debug_sw_tlb(env, excp);
-
msr |= env->crf[0] << 28;
msr |= env->error_code; /* key, D/I, S/L bits */
/* Set way using a LRU mechanism */
msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
-
break;
case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
case POWERPC_EXCP_SMI: /* System management interrupt */
case POWERPC_EXCP_THERM: /* Thermal interrupt */
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
- /*
- * Sort out endianness of interrupt, this differs depending on the
- * CPU, the HV mode, etc...
- */
if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
new_msr |= (target_ulong)1 << MSR_LE;
}
-
- /* Save PC */
env->spr[SPR_SRR0] = env->nip;
-
- /* Save MSR */
env->spr[SPR_SRR1] = msr;
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
- /*
- * new interrupt handler msr preserves existing ME unless
- * explicitly overridden
- */
+ /* new interrupt handler msr preserves ME unless explicitly overridden */
new_msr = env->msr & ((target_ulong)1 << MSR_ME);
- /*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later.
- */
+ /* HV emu assistance interrupt only exists on server arch 2.05 or later */
if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
switch (excp) {
@@ -936,7 +873,6 @@
powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
-
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
@@ -964,11 +900,9 @@
powerpc_reset_excp_state(cpu);
return;
}
-
/*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
+ * NIP always points to the faulting instruction for FP exceptions,
+ * so always use store_next and claim we are precise in the MSR.
*/
msr |= 0x00100000;
break;
@@ -984,7 +918,7 @@
break;
default:
/* Should never occur */
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -1026,7 +960,8 @@
break;
case POWERPC_EXCP_RESET: /* System reset exception */
if (FIELD_EX64(env->msr, MSR, POW)) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
+ cpu_abort(env_cpu(env),
+ "Trying to deliver power-saving system reset "
"exception %d with no HV support\n", excp);
}
break;
@@ -1039,54 +974,39 @@
case POWERPC_EXCP_THERM: /* Thermal interrupt */
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
case POWERPC_EXCP_VPUA: /* Vector assist exception */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
- /*
- * Sort out endianness of interrupt, this differs depending on the
- * CPU, the HV mode, etc...
- */
if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
new_msr |= (target_ulong)1 << MSR_LE;
}
-
- /* Save PC */
env->spr[SPR_SRR0] = env->nip;
-
- /* Save MSR */
env->spr[SPR_SRR1] = msr;
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- int srr0, srr1;
+ int srr0 = SPR_SRR0, srr1 = SPR_SRR1;
+ /*
+ * Book E does not play games with certain bits of xSRR1 being MSR save
+ * bits and others being error status. xSRR1 is the old MSR, period.
+ */
msr = env->msr;
- /*
- * new interrupt handler msr preserves existing ME unless
- * explicitly overridden
- */
+ /* new interrupt handler msr preserves ME unless explicitly overridden */
new_msr = env->msr & ((target_ulong)1 << MSR_ME);
- /* target registers */
- srr0 = SPR_SRR0;
- srr1 = SPR_SRR1;
-
- /*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later.
- */
+ /* HV emu assistance interrupt only exists on server arch 2.05 or later */
if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
@@ -1103,10 +1023,9 @@
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
switch (excp) {
@@ -1135,6 +1054,7 @@
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
if (env->mpic_proxy) {
+ CPUState *cs = env_cpu(env);
/* IACK the IRQ on delivery */
env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
}
@@ -1149,11 +1069,9 @@
powerpc_reset_excp_state(cpu);
return;
}
-
/*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
+ * NIP always points to the faulting instruction for FP exceptions,
+ * so always use store_next and claim we are precise in the MSR.
*/
msr |= 0x00100000;
env->spr[SPR_BOOKE_ESR] = ESR_FP;
@@ -1173,7 +1091,7 @@
break;
default:
/* Should never occur */
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -1214,7 +1132,8 @@
/* DBSR already modified by caller */
} else {
- cpu_abort(cs, "Debug exception triggered on unsupported model\n");
+ cpu_abort(env_cpu(env),
+ "Debug exception triggered on unsupported model\n");
}
break;
case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
@@ -1228,21 +1147,23 @@
break;
case POWERPC_EXCP_RESET: /* System reset exception */
if (FIELD_EX64(env->msr, MSR, POW)) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
+ cpu_abort(env_cpu(env),
+ "Trying to deliver power-saving system reset "
"exception %d with no HV support\n", excp);
}
break;
case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
/* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
new_msr |= (target_ulong)1 << MSR_CM;
@@ -1251,12 +1172,8 @@
}
#endif
- /* Save PC */
env->spr[srr0] = env->nip;
-
- /* Save MSR */
env->spr[srr1] = msr;
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
@@ -1376,24 +1293,19 @@
static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- int srr0, srr1, lev = -1;
+ int srr0 = SPR_SRR0, srr1 = SPR_SRR1, lev = -1;
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
/*
- * new interrupt handler msr preserves existing HV and ME unless
- * explicitly overridden
+ * new interrupt handler msr preserves HV and ME unless explicitly
+ * overridden
*/
new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
- /* target registers */
- srr0 = SPR_SRR0;
- srr1 = SPR_SRR1;
-
/*
* check for special resume at 0x100 from doze/nap/sleep/winkle on
* P7/P8/P9
@@ -1415,10 +1327,9 @@
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
if (is_prefix_insn_excp(cpu, excp)) {
@@ -1435,7 +1346,6 @@
*/
new_msr |= (target_ulong)MSR_HVB;
}
-
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
@@ -1453,23 +1363,17 @@
{
bool lpes0;
- /*
- * LPES0 is only taken into consideration if we support HV
- * mode for this CPU.
- */
+ /* LPES0 is only taken into consideration if we support HV mode */
if (!env->has_hv_mode) {
break;
}
-
lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
-
if (!lpes0) {
new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
}
-
break;
}
case POWERPC_EXCP_ALIGN: /* Alignment exception */
@@ -1492,11 +1396,9 @@
powerpc_reset_excp_state(cpu);
return;
}
-
/*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
+ * NIP always points to the faulting instruction for FP exceptions,
+ * so always use store_next and claim we are precise in the MSR.
*/
msr |= 0x00100000;
break;
@@ -1512,7 +1414,7 @@
break;
default:
/* Should never occur */
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -1578,7 +1480,8 @@
new_msr |= (target_ulong)MSR_HVB;
} else {
if (FIELD_EX64(env->msr, MSR, POW)) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
+ cpu_abort(env_cpu(env),
+ "Trying to deliver power-saving system reset "
"exception %d with no HV support\n", excp);
}
}
@@ -1650,29 +1553,22 @@
case POWERPC_EXCP_VPUA: /* Vector assist exception */
case POWERPC_EXCP_MAINT: /* Maintenance exception */
case POWERPC_EXCP_HV_MAINT: /* Hypervisor Maintenance exception */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
- /*
- * Sort out endianness of interrupt, this differs depending on the
- * CPU, the HV mode, etc...
- */
if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
new_msr |= (target_ulong)1 << MSR_LE;
}
-
new_msr |= (target_ulong)1 << MSR_SF;
if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
- /* Save PC */
env->spr[srr0] = env->nip;
-
- /* Save MSR */
env->spr[srr1] = msr;
}
@@ -1681,19 +1577,15 @@
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
/* Deliver interrupt to L1 by returning from the H_ENTER_NESTED call */
vhc->deliver_hv_excp(cpu, excp);
-
powerpc_reset_excp_state(cpu);
-
} else {
/* Sanity check */
if (!(env->msr_mask & MSR_HVB) && srr0 == SPR_HSRR0) {
- cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
- "no HV support\n", excp);
+ cpu_abort(env_cpu(env), "Trying to deliver HV exception (HSRR) %d "
+ "with no HV support\n", excp);
}
-
/* This can update new_msr and vector if AIL applies */
ppc_excp_apply_ail(cpu, excp, msr, &new_msr, &vector);
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
}
@@ -1702,15 +1594,15 @@
{
g_assert_not_reached();
}
-#endif
+#endif /* TARGET_PPC64 */
static void powerpc_excp(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
}
qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
@@ -1753,7 +1645,7 @@
powerpc_excp(cpu, cs->exception_index);
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
#define P7_UNUSED_INTERRUPTS \
(PPC_INTERRUPT_RESET | PPC_INTERRUPT_HVIRT | PPC_INTERRUPT_CEXT | \
PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | PPC_INTERRUPT_FIT | \
@@ -2084,10 +1976,23 @@
return 0;
}
-#endif
+#endif /* TARGET_PPC64 */
-static int ppc_next_unmasked_interrupt_generic(CPUPPCState *env)
+static int ppc_next_unmasked_interrupt(CPUPPCState *env)
{
+#ifdef TARGET_PPC64
+ switch (env->excp_model) {
+ case POWERPC_EXCP_POWER7:
+ return p7_next_unmasked_interrupt(env);
+ case POWERPC_EXCP_POWER8:
+ return p8_next_unmasked_interrupt(env);
+ case POWERPC_EXCP_POWER9:
+ case POWERPC_EXCP_POWER10:
+ return p9_next_unmasked_interrupt(env);
+ default:
+ break;
+ }
+#endif
bool async_deliver;
/* External reset */
@@ -2198,23 +2103,6 @@
return 0;
}
-static int ppc_next_unmasked_interrupt(CPUPPCState *env)
-{
- switch (env->excp_model) {
-#if defined(TARGET_PPC64)
- case POWERPC_EXCP_POWER7:
- return p7_next_unmasked_interrupt(env);
- case POWERPC_EXCP_POWER8:
- return p8_next_unmasked_interrupt(env);
- case POWERPC_EXCP_POWER9:
- case POWERPC_EXCP_POWER10:
- return p9_next_unmasked_interrupt(env);
-#endif
- default:
- return ppc_next_unmasked_interrupt_generic(env);
- }
-}
-
/*
* Sets CPU_INTERRUPT_HARD if there is at least one unmasked interrupt to be
* delivered and clears CPU_INTERRUPT_HARD otherwise.
@@ -2240,11 +2128,10 @@
}
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
static void p7_deliver_interrupt(CPUPPCState *env, int interrupt)
{
PowerPCCPU *cpu = env_archcpu(env);
- CPUState *cs = env_cpu(env);
switch (interrupt) {
case PPC_INTERRUPT_MCK: /* Machine check exception */
@@ -2288,14 +2175,14 @@
assert(!env->resume_as_sreset);
break;
default:
- cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt);
+ cpu_abort(env_cpu(env), "Invalid PowerPC interrupt %d. Aborting\n",
+ interrupt);
}
}
static void p8_deliver_interrupt(CPUPPCState *env, int interrupt)
{
PowerPCCPU *cpu = env_archcpu(env);
- CPUState *cs = env_cpu(env);
switch (interrupt) {
case PPC_INTERRUPT_MCK: /* Machine check exception */
@@ -2359,7 +2246,8 @@
assert(!env->resume_as_sreset);
break;
default:
- cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt);
+ cpu_abort(env_cpu(env), "Invalid PowerPC interrupt %d. Aborting\n",
+ interrupt);
}
}
@@ -2438,15 +2326,28 @@
assert(!env->resume_as_sreset);
break;
default:
- cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt);
+ cpu_abort(env_cpu(env), "Invalid PowerPC interrupt %d. Aborting\n",
+ interrupt);
}
}
-#endif
+#endif /* TARGET_PPC64 */
-static void ppc_deliver_interrupt_generic(CPUPPCState *env, int interrupt)
+static void ppc_deliver_interrupt(CPUPPCState *env, int interrupt)
{
+#ifdef TARGET_PPC64
+ switch (env->excp_model) {
+ case POWERPC_EXCP_POWER7:
+ return p7_deliver_interrupt(env, interrupt);
+ case POWERPC_EXCP_POWER8:
+ return p8_deliver_interrupt(env, interrupt);
+ case POWERPC_EXCP_POWER9:
+ case POWERPC_EXCP_POWER10:
+ return p9_deliver_interrupt(env, interrupt);
+ default:
+ break;
+ }
+#endif
PowerPCCPU *cpu = env_archcpu(env);
- CPUState *cs = env_cpu(env);
switch (interrupt) {
case PPC_INTERRUPT_RESET: /* External reset */
@@ -2543,27 +2444,8 @@
assert(!env->resume_as_sreset);
break;
default:
- cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt);
- }
-}
-
-static void ppc_deliver_interrupt(CPUPPCState *env, int interrupt)
-{
- switch (env->excp_model) {
-#if defined(TARGET_PPC64)
- case POWERPC_EXCP_POWER7:
- p7_deliver_interrupt(env, interrupt);
- break;
- case POWERPC_EXCP_POWER8:
- p8_deliver_interrupt(env, interrupt);
- break;
- case POWERPC_EXCP_POWER9:
- case POWERPC_EXCP_POWER10:
- p9_deliver_interrupt(env, interrupt);
- break;
-#endif
- default:
- ppc_deliver_interrupt_generic(env, interrupt);
+ cpu_abort(env_cpu(env), "Invalid PowerPC interrupt %d. Aborting\n",
+ interrupt);
}
}
@@ -2597,8 +2479,7 @@
bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
int interrupt;
if ((interrupt_request & CPU_INTERRUPT_HARD) == 0) {
@@ -2660,10 +2541,8 @@
{
raise_exception_err_ra(env, exception, 0, 0);
}
-#endif
-#if !defined(CONFIG_USER_ONLY)
-#ifdef CONFIG_TCG
+#ifndef CONFIG_USER_ONLY
void helper_store_msr(CPUPPCState *env, target_ulong val)
{
uint32_t excp = hreg_store_msr(env, val, 0);
@@ -2679,7 +2558,7 @@
ppc_maybe_interrupt(env);
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
void helper_scv(CPUPPCState *env, uint32_t lev)
{
if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) {
@@ -2707,7 +2586,7 @@
ppc_maybe_interrupt(env);
}
-#endif /* defined(TARGET_PPC64) */
+#endif /* TARGET_PPC64 */
static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
{
@@ -2718,7 +2597,7 @@
if (env->flags & POWERPC_FLAG_TGPR)
msr &= ~(1ULL << MSR_TGPR);
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
/* Switching to 32-bit ? Crop the nip */
if (!msr_is_64bit(env, msr)) {
nip = (uint32_t)nip;
@@ -2747,7 +2626,7 @@
do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful);
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
void helper_rfid(CPUPPCState *env)
{
/*
@@ -2768,9 +2647,7 @@
{
do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
}
-#endif
-#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
void helper_rfebb(CPUPPCState *env, target_ulong s)
{
target_ulong msr = env->msr;
@@ -2845,7 +2722,7 @@
do_ebb(env, POWERPC_EXCP_PERFM_EBB);
}
-#endif
+#endif /* TARGET_PPC64 */
/*****************************************************************************/
/* Embedded PowerPC specific helpers */
@@ -2870,10 +2747,8 @@
/* FIXME: choose CSRR1 or MCSRR1 based on cpu type */
do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
}
-#endif /* CONFIG_TCG */
-#endif /* !defined(CONFIG_USER_ONLY) */
+#endif /* !CONFIG_USER_ONLY */
-#ifdef CONFIG_TCG
void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
uint32_t flags)
{
@@ -2887,7 +2762,7 @@
}
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
uint32_t flags)
{
@@ -2900,10 +2775,8 @@
POWERPC_EXCP_TRAP, GETPC());
}
}
-#endif
-#endif
+#endif /* TARGET_PPC64 */
-#ifdef CONFIG_TCG
static uint32_t helper_SIMON_LIKE_32_64(uint32_t x, uint64_t key, uint32_t lane)
{
const uint16_t c = 0xfffc;
@@ -3014,12 +2887,8 @@
HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false, NPHIE)
HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true, PHIE)
HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false, PHIE)
-#endif /* CONFIG_TCG */
-#if !defined(CONFIG_USER_ONLY)
-
-#ifdef CONFIG_TCG
-
+#ifndef CONFIG_USER_ONLY
/* Embedded.Processor Control */
static int dbell2irq(target_ulong rb)
{
@@ -3126,7 +2995,7 @@
book3s_msgsnd_common(pir, PPC_INTERRUPT_HDOORBELL);
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb)
{
helper_hfscr_facility_check(env, HFSCR_MSGP, "msgclrp", HFSCR_IC_MSGP);
@@ -3366,5 +3235,5 @@
return false;
}
-#endif /* CONFIG_TCG */
#endif /* !CONFIG_USER_ONLY */
+#endif /* CONFIG_TCG */
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index 122ea9d..3f1e61b 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -108,8 +108,7 @@
int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
uint8_t *mem_buf;
int r = ppc_gdb_register_len(n);
@@ -152,8 +151,7 @@
int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
uint8_t *mem_buf;
int r = ppc_gdb_register_len_apple(n);
@@ -206,8 +204,7 @@
int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
int r = ppc_gdb_register_len(n);
if (!r) {
@@ -253,8 +250,7 @@
}
int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
int r = ppc_gdb_register_len_apple(n);
if (!r) {
@@ -324,6 +320,9 @@
continue;
}
+ gdb_feature_builder_append_reg(&builder, g_ascii_strdown(spr->name, -1),
+ TARGET_LONG_BITS, num_regs,
+ "int", "spr");
/*
* GDB identifies registers based on the order they are
* presented in the XML. These ids will not match QEMU's
@@ -334,10 +333,6 @@
*/
spr->gdb_id = num_regs;
num_regs++;
-
- gdb_feature_builder_append_reg(&builder, g_ascii_strdown(spr->name, -1),
- TARGET_LONG_BITS, num_regs,
- "int", "spr");
}
gdb_feature_builder_end(&builder);
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 410b39c..2525898 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -264,6 +264,11 @@
value &= ~MSR_HVB;
value |= env->msr & MSR_HVB;
}
+ /* Attempt to modify MSR[ME] in guest state is ignored */
+ if (is_book3s_arch2x(env) && !(env->msr & MSR_HVB)) {
+ value &= ~(1 << MSR_ME);
+ value |= env->msr & (1 << MSR_ME);
+ }
if ((value ^ env->msr) & (R_MSR_IR_MASK | R_MSR_DR_MASK)) {
cpu_interrupt_exittb(cs);
}
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 4fcf3af..eada59f 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -187,6 +187,12 @@
&X_a ra
@X_a ...... ra:3 .. ..... ..... .......... . &X_a
+&XO rt ra rb oe:bool rc:bool
+@XO ...... rt:5 ra:5 rb:5 oe:1 ......... rc:1 &XO
+
+&XO_ta rt ra oe:bool rc:bool
+@XO_ta ...... rt:5 ra:5 ..... oe:1 ......... rc:1 &XO_ta
+
%xx_xt 0:1 21:5
%xx_xb 1:1 11:5
%xx_xa 2:1 16:5
@@ -322,10 +328,30 @@
### Fixed-Point Arithmetic Instructions
+ADD 011111 ..... ..... ..... . 100001010 . @XO
+ADDC 011111 ..... ..... ..... . 000001010 . @XO
+ADDE 011111 ..... ..... ..... . 010001010 . @XO
+
+# ADDEX is Z23-form, with CY=0; all other values for CY are reserved.
+# This works out the same as X-form.
+ADDEX 011111 ..... ..... ..... 00 10101010 - @X
+
ADDI 001110 ..... ..... ................ @D
ADDIS 001111 ..... ..... ................ @D
+ADDIC 001100 ..... ..... ................ @D
+ADDIC_ 001101 ..... ..... ................ @D
ADDPCIS 010011 ..... ..... .......... 00010 . @DX
+ADDME 011111 ..... ..... ----- . 011101010 . @XO_ta
+ADDZE 011111 ..... ..... ----- . 011001010 . @XO_ta
+
+SUBF 011111 ..... ..... ..... . 000101000 . @XO
+SUBFIC 001000 ..... ..... ................ @D
+SUBFC 011111 ..... ..... ..... . 000001000 . @XO
+SUBFE 011111 ..... ..... ..... . 010001000 . @XO
+
+SUBFME 011111 ..... ..... ----- . 011101000 . @XO_ta
+SUBFZE 011111 ..... ..... ----- . 011001000 . @XO_ta
## Fixed-Point Logical Instructions
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index bcf30a5..8231feb 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -546,8 +546,7 @@
static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
/* Init 'val' to avoid "uninitialised value" Valgrind warnings */
union {
uint32_t u32;
@@ -581,8 +580,7 @@
static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
union {
uint32_t u32;
uint64_t u64;
@@ -615,8 +613,7 @@
static int kvm_put_fp(CPUState *cs)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
struct kvm_one_reg reg;
int i;
int ret;
@@ -635,8 +632,8 @@
for (i = 0; i < 32; i++) {
uint64_t vsr[2];
- uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
- uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
+ uint64_t *fpr = cpu_fpr_ptr(env, i);
+ uint64_t *vsrl = cpu_vsrl_ptr(env, i);
#if HOST_BIG_ENDIAN
vsr[0] = float64_val(*fpr);
@@ -682,8 +679,7 @@
static int kvm_get_fp(CPUState *cs)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
struct kvm_one_reg reg;
int i;
int ret;
@@ -704,8 +700,8 @@
for (i = 0; i < 32; i++) {
uint64_t vsr[2];
- uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
- uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
+ uint64_t *fpr = cpu_fpr_ptr(env, i);
+ uint64_t *vsrl = cpu_vsrl_ptr(env, i);
reg.addr = (uintptr_t) &vsr;
reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
@@ -2369,17 +2365,6 @@
#if defined(TARGET_PPC64)
pcc->radix_page_info = kvmppc_get_radix_page_info();
-
- if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
- /*
- * POWER9 DD1 has some bugs which make it not really ISA 3.00
- * compliant. More importantly, advertising ISA 3.00
- * architected mode may prevent guests from activating
- * necessary DD1 workarounds.
- */
- pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
- | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
- }
#endif /* defined(TARGET_PPC64) */
}
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index a9d41d2..58e808d 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -49,9 +49,6 @@
CPUState *cs = env_cpu(env);
CPUState *ccs;
uint32_t nr_threads = cs->nr_threads;
- uint32_t core_id = env->spr[SPR_PIR] & ~(nr_threads - 1);
-
- assert(core_id == env->spr[SPR_PIR] - env->spr[SPR_TIR]);
if (nr_threads == 1) {
env->spr[sprn] = val;
diff --git a/target/ppc/ppc-qmp-cmds.c b/target/ppc/ppc-qmp-cmds.c
index ee0b99f..a25d86a 100644
--- a/target/ppc/ppc-qmp-cmds.c
+++ b/target/ppc/ppc-qmp-cmds.c
@@ -137,8 +137,7 @@
int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
{
int i, regnum;
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
/* General purpose registers */
if ((qemu_tolower(name[0]) == 'r') &&
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 28fc779..93ffec7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -296,33 +296,26 @@
tcg_gen_movi_tl(cpu_nip, nip);
}
-static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
+static void gen_exception_err_nip(DisasContext *ctx, uint32_t excp,
+ uint32_t error, target_ulong nip)
{
TCGv_i32 t0, t1;
- /*
- * These are all synchronous exceptions, we set the PC back to the
- * faulting instruction
- */
- gen_update_nip(ctx, ctx->cia);
+ gen_update_nip(ctx, nip);
t0 = tcg_constant_i32(excp);
t1 = tcg_constant_i32(error);
gen_helper_raise_exception_err(tcg_env, t0, t1);
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_exception(DisasContext *ctx, uint32_t excp)
+static inline void gen_exception_err(DisasContext *ctx, uint32_t excp,
+ uint32_t error)
{
- TCGv_i32 t0;
-
/*
* These are all synchronous exceptions, we set the PC back to the
* faulting instruction
*/
- gen_update_nip(ctx, ctx->cia);
- t0 = tcg_constant_i32(excp);
- gen_helper_raise_exception(tcg_env, t0);
- ctx->base.is_jmp = DISAS_NORETURN;
+ gen_exception_err_nip(ctx, excp, error, ctx->cia);
}
static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
@@ -336,6 +329,15 @@
ctx->base.is_jmp = DISAS_NORETURN;
}
+static inline void gen_exception(DisasContext *ctx, uint32_t excp)
+{
+ /*
+ * These are all synchronous exceptions, we set the PC back to the
+ * faulting instruction
+ */
+ gen_exception_nip(ctx, excp, ctx->cia);
+}
+
#if !defined(CONFIG_USER_ONLY)
static void gen_ppc_maybe_interrupt(DisasContext *ctx)
{
@@ -1735,61 +1737,6 @@
tcg_gen_mov_tl(ret, t0);
}
}
-/* Add functions with two operands */
-#define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
- cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
- ca, glue(ca, 32), \
- add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
-}
-/* Add functions with one operand and one immediate */
-#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \
- add_ca, compute_ca, compute_ov) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv t0 = tcg_constant_tl(const_val); \
- gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
- cpu_gpr[rA(ctx->opcode)], t0, \
- ca, glue(ca, 32), \
- add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
-}
-
-/* add add. addo addo. */
-GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0)
-GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1)
-/* addc addc. addco addco. */
-GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0)
-GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1)
-/* adde adde. addeo addeo. */
-GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0)
-GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1)
-/* addme addme. addmeo addmeo. */
-GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0)
-GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1)
-/* addex */
-GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
-/* addze addze. addzeo addzeo.*/
-GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
-GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
-/* addic addic.*/
-static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
-{
- TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
- gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
- c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
-}
-
-static void gen_addic(DisasContext *ctx)
-{
- gen_op_addic(ctx, 0);
-}
-
-static void gen_addic_(DisasContext *ctx)
-{
- gen_op_addic(ctx, 1);
-}
static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, int sign, int compute_ov)
@@ -2210,47 +2157,6 @@
tcg_gen_mov_tl(ret, t0);
}
}
-/* Sub functions with Two operands functions */
-#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
- cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
- add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
-}
-/* Sub functions with one operand and one immediate */
-#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
- add_ca, compute_ca, compute_ov) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv t0 = tcg_constant_tl(const_val); \
- gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
- cpu_gpr[rA(ctx->opcode)], t0, \
- add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
-}
-/* subf subf. subfo subfo. */
-GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
-GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
-/* subfc subfc. subfco subfco. */
-GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
-GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
-/* subfe subfe. subfeo subfo. */
-GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
-GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
-/* subfme subfme. subfmeo subfmeo. */
-GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
-GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
-/* subfze subfze. subfzeo subfzeo.*/
-GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
-GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
-
-/* subfic */
-static void gen_subfic(DisasContext *ctx)
-{
- TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
- gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
- c, 0, 1, 0, 0);
-}
/* neg neg. nego nego. */
static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
@@ -6524,8 +6430,6 @@
GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
-GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
@@ -6536,7 +6440,6 @@
#endif
GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
-GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
@@ -6747,25 +6650,6 @@
GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
#endif
-#undef GEN_INT_ARITH_ADD
-#undef GEN_INT_ARITH_ADD_CONST
-#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
-GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
-#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
- add_ca, compute_ca, compute_ov) \
-GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
-GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
-GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
-GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
-GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
-GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
-GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
-GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
-GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
-GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300),
-GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
-GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
-
#undef GEN_INT_ARITH_DIVW
#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
@@ -6804,24 +6688,6 @@
GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
#endif
-#undef GEN_INT_ARITH_SUBF
-#undef GEN_INT_ARITH_SUBF_CONST
-#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
-GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
-#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
- add_ca, compute_ca, compute_ov) \
-GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
-GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
-GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
-GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
-GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
-GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
-GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
-GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
-GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
-GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
-GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
-
#undef GEN_LOGICAL1
#undef GEN_LOGICAL2
#define GEN_LOGICAL2(name, tcg_op, opc, type) \
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 51c6fa7..0c66465 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -325,6 +325,76 @@
return true;
}
+static bool trans_ADDEX(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ gen_op_arith_add(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
+ cpu_ov, cpu_ov32, true, true, false, false);
+ return true;
+}
+
+static bool do_add_D(DisasContext *ctx, arg_D *a, bool add_ca, bool compute_ca,
+ bool compute_ov, bool compute_rc0)
+{
+ gen_op_arith_add(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra],
+ tcg_constant_tl(a->si), cpu_ca, cpu_ca32,
+ add_ca, compute_ca, compute_ov, compute_rc0);
+ return true;
+}
+
+static bool do_add_XO(DisasContext *ctx, arg_XO *a, bool add_ca,
+ bool compute_ca)
+{
+ gen_op_arith_add(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
+ cpu_ca, cpu_ca32, add_ca, compute_ca, a->oe, a->rc);
+ return true;
+}
+
+static bool do_add_const_XO(DisasContext *ctx, arg_XO_ta *a, TCGv const_val,
+ bool add_ca, bool compute_ca)
+{
+ gen_op_arith_add(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], const_val,
+ cpu_ca, cpu_ca32, add_ca, compute_ca, a->oe, a->rc);
+ return true;
+}
+
+TRANS(ADD, do_add_XO, false, false);
+TRANS(ADDC, do_add_XO, false, true);
+TRANS(ADDE, do_add_XO, true, true);
+TRANS(ADDME, do_add_const_XO, tcg_constant_tl(-1LL), true, true);
+TRANS(ADDZE, do_add_const_XO, tcg_constant_tl(0), true, true);
+TRANS(ADDIC, do_add_D, false, true, false, false);
+TRANS(ADDIC_, do_add_D, false, true, false, true);
+
+static bool trans_SUBFIC(DisasContext *ctx, arg_D *a)
+{
+ gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra],
+ tcg_constant_tl(a->si), false, true, false, false);
+ return true;
+}
+
+static bool do_subf_XO(DisasContext *ctx, arg_XO *a, bool add_ca,
+ bool compute_ca)
+{
+ gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
+ add_ca, compute_ca, a->oe, a->rc);
+ return true;
+}
+
+static bool do_subf_const_XO(DisasContext *ctx, arg_XO_ta *a, TCGv const_val,
+ bool add_ca, bool compute_ca)
+{
+ gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], const_val,
+ add_ca, compute_ca, a->oe, a->rc);
+ return true;
+}
+
+TRANS(SUBF, do_subf_XO, false, false)
+TRANS(SUBFC, do_subf_XO, false, true)
+TRANS(SUBFE, do_subf_XO, true, true)
+TRANS(SUBFME, do_subf_const_XO, tcg_constant_tl(-1LL), true, true)
+TRANS(SUBFZE, do_subf_const_XO, tcg_constant_tl(0), true, true)
+
static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a)
{
gen_invalid(ctx);
diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c
index 7ff76f7..a4d07a0 100644
--- a/target/ppc/user_only_helper.c
+++ b/target/ppc/user_only_helper.c
@@ -27,8 +27,7 @@
MMUAccessType access_type,
bool maperr, uintptr_t retaddr)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
int exception, error_code;
/*
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5a48d30..c160b92 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -926,7 +926,7 @@
#endif
CPUState *cs = CPU(obj);
RISCVCPU *cpu = RISCV_CPU(cs);
- RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj);
CPURISCVState *env = &cpu->env;
if (mcc->parent_phases.hold) {
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index c7afdb1..cda7d78 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -44,7 +44,7 @@
#include "kvm_riscv.h"
#include "sbi_ecall_interface.h"
#include "chardev/char-fe.h"
-#include "migration/migration.h"
+#include "migration/misc.h"
#include "sysemu/runstate.h"
#include "hw/riscv/numa.h"
@@ -729,7 +729,7 @@
* frequency. Therefore, we should check whether they are the same here
* during the migration.
*/
- if (migration_is_running(migrate_get_current()->state)) {
+ if (migration_is_running()) {
KVM_RISCV_GET_TIMER(cs, frequency, reg);
if (reg != env->kvm_timer_frequency) {
error_report("Dst Hosts timer frequency != Src Hosts");
diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
index c48b9cf..d363dc3 100644
--- a/target/riscv/riscv-qmp-cmds.c
+++ b/target/riscv/riscv-qmp-cmds.c
@@ -28,7 +28,6 @@
#include "qapi/qapi-commands-machine-target.h"
#include "qapi/qmp/qbool.h"
#include "qapi/qmp/qdict.h"
-#include "qapi/qmp/qerror.h"
#include "qapi/qobject-input-visitor.h"
#include "qapi/visitor.h"
#include "qom/qom-qobject.h"
@@ -129,18 +128,20 @@
}
static void riscv_cpuobj_validate_qdict_in(Object *obj, QObject *props,
- const QDict *qdict_in,
+ const char *props_arg_name,
Error **errp)
{
+ const QDict *qdict_in;
const QDictEntry *qe;
Visitor *visitor;
Error *local_err = NULL;
visitor = qobject_input_visitor_new(props);
- if (!visit_start_struct(visitor, NULL, NULL, 0, &local_err)) {
+ if (!visit_start_struct(visitor, props_arg_name, NULL, 0, &local_err)) {
goto err;
}
+ qdict_in = qobject_to(QDict, props);
for (qe = qdict_first(qdict_in); qe; qe = qdict_next(qdict_in, qe)) {
object_property_find_err(obj, qe->key, &local_err);
if (local_err) {
@@ -170,7 +171,6 @@
Error **errp)
{
CpuModelExpansionInfo *expansion_info;
- const QDict *qdict_in = NULL;
QDict *qdict_out;
ObjectClass *oc;
Object *obj;
@@ -188,14 +188,6 @@
return NULL;
}
- if (model->props) {
- qdict_in = qobject_to(QDict, model->props);
- if (!qdict_in) {
- error_setg(errp, QERR_INVALID_PARAMETER_TYPE, "props", "dict");
- return NULL;
- }
- }
-
obj = object_new(object_class_get_name(oc));
riscv_check_if_cpu_available(RISCV_CPU(obj), &local_err);
@@ -205,8 +197,8 @@
return NULL;
}
- if (qdict_in) {
- riscv_cpuobj_validate_qdict_in(obj, model->props, qdict_in,
+ if (model->props) {
+ riscv_cpuobj_validate_qdict_in(obj, model->props, "model.props",
&local_err);
if (local_err) {
error_propagate(errp, local_err);
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 2f878d0..da673a5 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -71,9 +71,9 @@
static void rx_cpu_reset_hold(Object *obj)
{
- RXCPU *cpu = RX_CPU(obj);
- RXCPUClass *rcc = RX_CPU_GET_CLASS(cpu);
- CPURXState *env = &cpu->env;
+ CPUState *cs = CPU(obj);
+ RXCPUClass *rcc = RX_CPU_GET_CLASS(obj);
+ CPURXState *env = cpu_env(cs);
uint32_t *resetvec;
if (rcc->parent_phases.hold) {
diff --git a/target/rx/gdbstub.c b/target/rx/gdbstub.c
index d7e0e66..f222bf0 100644
--- a/target/rx/gdbstub.c
+++ b/target/rx/gdbstub.c
@@ -21,8 +21,7 @@
int rx_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- RXCPU *cpu = RX_CPU(cs);
- CPURXState *env = &cpu->env;
+ CPURXState *env = cpu_env(cs);
switch (n) {
case 0 ... 15:
@@ -53,8 +52,7 @@
int rx_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- RXCPU *cpu = RX_CPU(cs);
- CPURXState *env = &cpu->env;
+ CPURXState *env = cpu_env(cs);
uint32_t psw;
switch (n) {
case 0 ... 15:
diff --git a/target/rx/helper.c b/target/rx/helper.c
index dad5fb4..80912e8 100644
--- a/target/rx/helper.c
+++ b/target/rx/helper.c
@@ -45,8 +45,7 @@
#define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR)
void rx_cpu_do_interrupt(CPUState *cs)
{
- RXCPU *cpu = RX_CPU(cs);
- CPURXState *env = &cpu->env;
+ CPURXState *env = cpu_env(cs);
int do_irq = cs->interrupt_request & INT_FLAGS;
uint32_t save_psw;
@@ -122,8 +121,7 @@
bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
- RXCPU *cpu = RX_CPU(cs);
- CPURXState *env = &cpu->env;
+ CPURXState *env = cpu_env(cs);
int accept = 0;
/* hardware interrupt (Normal) */
if ((interrupt_request & CPU_INTERRUPT_HARD) &&
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 2265bd1..f6e9e0e 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -131,8 +131,7 @@
void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
- RXCPU *cpu = RX_CPU(cs);
- CPURXState *env = &cpu->env;
+ CPURXState *env = cpu_env(cs);
int i;
uint32_t psw;
@@ -2195,9 +2194,8 @@
static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
- CPURXState *env = cpu_env(cs);
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- ctx->env = env;
+ ctx->env = cpu_env(cs);
ctx->tb_flags = ctx->base.tb->flags;
}
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index a63d990..1a1c096 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@ -503,6 +503,7 @@
static void check_compatibility(const S390CPUModel *max_model,
const S390CPUModel *model, Error **errp)
{
+ ERRP_GUARD();
S390FeatBitmap missing;
if (model->def->gen > max_model->def->gen) {
@@ -566,6 +567,7 @@
void s390_realize_cpu_model(CPUState *cs, Error **errp)
{
+ ERRP_GUARD();
Error *err = NULL;
S390CPUClass *xcc = S390_CPU_GET_CLASS(cs);
S390CPU *cpu = S390_CPU(cs);
diff --git a/target/s390x/cpu_models_sysemu.c b/target/s390x/cpu_models_sysemu.c
index 63981bf..2d99218 100644
--- a/target/s390x/cpu_models_sysemu.c
+++ b/target/s390x/cpu_models_sysemu.c
@@ -17,7 +17,6 @@
#include "sysemu/kvm.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
-#include "qapi/qmp/qerror.h"
#include "qapi/qobject-input-visitor.h"
#include "qapi/qmp/qdict.h"
#include "qapi/qapi-commands-machine-target.h"
@@ -98,24 +97,16 @@
}
static void cpu_model_from_info(S390CPUModel *model, const CpuModelInfo *info,
- Error **errp)
+ const char *info_arg_name, Error **errp)
{
Error *err = NULL;
- const QDict *qdict = NULL;
+ const QDict *qdict;
const QDictEntry *e;
Visitor *visitor;
ObjectClass *oc;
S390CPU *cpu;
Object *obj;
- if (info->props) {
- qdict = qobject_to(QDict, info->props);
- if (!qdict) {
- error_setg(errp, QERR_INVALID_PARAMETER_TYPE, "props", "dict");
- return;
- }
- }
-
oc = cpu_class_by_name(TYPE_S390_CPU, info->name);
if (!oc) {
error_setg(errp, "The CPU definition \'%s\' is unknown.", info->name);
@@ -135,13 +126,17 @@
return;
}
- if (qdict) {
+ if (info->props) {
+ g_autofree const char *props_name = g_strdup_printf("%s.props",
+ info_arg_name);
+
visitor = qobject_input_visitor_new(info->props);
- if (!visit_start_struct(visitor, NULL, NULL, 0, errp)) {
+ if (!visit_start_struct(visitor, props_name, NULL, 0, errp)) {
visit_free(visitor);
object_unref(obj);
return;
}
+ qdict = qobject_to(QDict, info->props);
for (e = qdict_first(qdict); e; e = qdict_next(qdict, e)) {
if (!object_property_set(obj, e->key, visitor, &err)) {
break;
@@ -223,7 +218,7 @@
bool delta_changes = false;
/* convert it to our internal representation */
- cpu_model_from_info(&s390_model, model, &err);
+ cpu_model_from_info(&s390_model, model, "model", &err);
if (err) {
error_propagate(errp, err);
return NULL;
@@ -261,12 +256,12 @@
S390CPUModel modela, modelb;
/* convert both models to our internal representation */
- cpu_model_from_info(&modela, infoa, &err);
+ cpu_model_from_info(&modela, infoa, "modela", &err);
if (err) {
error_propagate(errp, err);
return NULL;
}
- cpu_model_from_info(&modelb, infob, &err);
+ cpu_model_from_info(&modelb, infob, "modelb", &err);
if (err) {
error_propagate(errp, err);
return NULL;
@@ -338,13 +333,13 @@
uint8_t max_gen;
/* convert both models to our internal representation */
- cpu_model_from_info(&modela, infoa, &err);
+ cpu_model_from_info(&modela, infoa, "modela", &err);
if (err) {
error_propagate(errp, err);
return NULL;
}
- cpu_model_from_info(&modelb, infob, &err);
+ cpu_model_from_info(&modelb, infob, "modelb", &err);
if (err) {
error_propagate(errp, err);
return NULL;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 2031168..4f5a4a3 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -71,8 +71,7 @@
static bool superh_io_recompile_replay_branch(CPUState *cs,
const TranslationBlock *tb)
{
- SuperHCPU *cpu = SUPERH_CPU(cs);
- CPUSH4State *env = &cpu->env;
+ CPUSH4State *env = cpu_env(cs);
if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND))
&& !(cs->tcg_cflags & CF_PCREL) && env->pc != tb->pc) {
@@ -106,10 +105,9 @@
static void superh_cpu_reset_hold(Object *obj)
{
- CPUState *s = CPU(obj);
- SuperHCPU *cpu = SUPERH_CPU(s);
- SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
- CPUSH4State *env = &cpu->env;
+ CPUState *cs = CPU(obj);
+ SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(obj);
+ CPUSH4State *env = cpu_env(cs);
if (scc->parent_phases.hold) {
scc->parent_phases.hold(obj);
@@ -159,8 +157,7 @@
static void sh7750r_cpu_initfn(Object *obj)
{
- SuperHCPU *cpu = SUPERH_CPU(obj);
- CPUSH4State *env = &cpu->env;
+ CPUSH4State *env = cpu_env(CPU(obj));
env->id = SH_CPU_SH7750R;
env->features = SH_FEATURE_BCR3_AND_BCR4;
@@ -177,8 +174,7 @@
static void sh7751r_cpu_initfn(Object *obj)
{
- SuperHCPU *cpu = SUPERH_CPU(obj);
- CPUSH4State *env = &cpu->env;
+ CPUSH4State *env = cpu_env(CPU(obj));
env->id = SH_CPU_SH7751R;
env->features = SH_FEATURE_BCR3_AND_BCR4;
@@ -195,8 +191,7 @@
static void sh7785_cpu_initfn(Object *obj)
{
- SuperHCPU *cpu = SUPERH_CPU(obj);
- CPUSH4State *env = &cpu->env;
+ CPUSH4State *env = cpu_env(CPU(obj));
env->id = SH_CPU_SH7785;
env->features = SH_FEATURE_SH4A;
@@ -231,8 +226,7 @@
static void superh_cpu_initfn(Object *obj)
{
- SuperHCPU *cpu = SUPERH_CPU(obj);
- CPUSH4State *env = &cpu->env;
+ CPUSH4State *env = cpu_env(CPU(obj));
env->movcal_backup_tail = &(env->movcal_backup);
}
diff --git a/target/sh4/gdbstub.c b/target/sh4/gdbstub.c
index d8e199f..75926d4 100644
--- a/target/sh4/gdbstub.c
+++ b/target/sh4/gdbstub.c
@@ -26,8 +26,7 @@
int superh_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- SuperHCPU *cpu = SUPERH_CPU(cs);
- CPUSH4State *env = &cpu->env;
+ CPUSH4State *env = cpu_env(cs);
switch (n) {
case 0 ... 7:
@@ -76,8 +75,7 @@
int superh_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- SuperHCPU *cpu = SUPERH_CPU(cs);
- CPUSH4State *env = &cpu->env;
+ CPUSH4State *env = cpu_env(cs);
switch (n) {
case 0 ... 7:
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 5a6f653..7c6f9d3 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -55,8 +55,7 @@
void superh_cpu_do_interrupt(CPUState *cs)
{
- SuperHCPU *cpu = SUPERH_CPU(cs);
- CPUSH4State *env = &cpu->env;
+ CPUSH4State *env = cpu_env(cs);
int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
int do_exp, irq_vector = cs->exception_index;
@@ -432,11 +431,10 @@
hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
- SuperHCPU *cpu = SUPERH_CPU(cs);
target_ulong physical;
int prot;
- if (get_physical_address(&cpu->env, &physical, &prot, addr, MMU_DATA_LOAD)
+ if (get_physical_address(cpu_env(cs), &physical, &prot, addr, MMU_DATA_LOAD)
== MMU_OK) {
return physical;
}
@@ -782,11 +780,8 @@
bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
- SuperHCPU *cpu = SUPERH_CPU(cs);
- CPUSH4State *env = &cpu->env;
-
/* Delay slots are indivisible, ignore interrupts */
- if (env->flags & TB_FLAG_DELAY_SLOT_MASK) {
+ if (cpu_env(cs)->flags & TB_FLAG_DELAY_SLOT_MASK) {
return false;
} else {
superh_cpu_do_interrupt(cs);
@@ -800,8 +795,7 @@
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
- SuperHCPU *cpu = SUPERH_CPU(cs);
- CPUSH4State *env = &cpu->env;
+ CPUSH4State *env = cpu_env(cs);
int ret;
target_ulong physical;
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index 54d390f..4559d0d 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -29,9 +29,7 @@
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
- CPUSH4State *env = cpu_env(cs);
-
- env->tea = addr;
+ cpu_env(cs)->tea = addr;
switch (access_type) {
case MMU_INST_FETCH:
case MMU_DATA_LOAD:
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 6a6d862..a9b1bc7 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -159,8 +159,7 @@
void superh_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
- SuperHCPU *cpu = SUPERH_CPU(cs);
- CPUSH4State *env = &cpu->env;
+ CPUSH4State *env = cpu_env(cs);
int i;
qemu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
@@ -2186,7 +2185,6 @@
static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUSH4State *env = cpu_env(cs);
uint32_t tbflags;
int bound;
@@ -2196,7 +2194,7 @@
/* We don't know if the delayed pc came from a dynamic or static branch,
so assume it is a dynamic branch. */
ctx->delayed_pc = -1; /* use delayed pc from env pointer */
- ctx->features = env->features;
+ ctx->features = cpu_env(cs)->features;
ctx->has_movcal = (tbflags & TB_FLAG_PENDING_MOVCA);
ctx->gbank = ((tbflags & (1 << SR_MD)) &&
(tbflags & (1 << SR_RB))) * 0x10;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 313ebc4..dc9ead2 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -31,10 +31,9 @@
static void sparc_cpu_reset_hold(Object *obj)
{
- CPUState *s = CPU(obj);
- SPARCCPU *cpu = SPARC_CPU(s);
- SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu);
- CPUSPARCState *env = &cpu->env;
+ CPUState *cs = CPU(obj);
+ SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
+ CPUSPARCState *env = cpu_env(cs);
if (scc->parent_phases.hold) {
scc->parent_phases.hold(obj);
@@ -83,8 +82,7 @@
static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
+ CPUSPARCState *env = cpu_env(cs);
if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) {
int pil = env->interrupt_index & 0xf;
@@ -613,8 +611,7 @@
static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
+ CPUSPARCState *env = cpu_env(cs);
int i, x;
qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
@@ -711,11 +708,8 @@
static bool sparc_cpu_has_work(CPUState *cs)
{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
-
return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
- cpu_interrupts_enabled(env);
+ cpu_interrupts_enabled(cpu_env(cs));
}
static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch)
@@ -777,8 +771,7 @@
CPUState *cs = CPU(dev);
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
Error *local_err = NULL;
- SPARCCPU *cpu = SPARC_CPU(dev);
- CPUSPARCState *env = &cpu->env;
+ CPUSPARCState *env = cpu_env(cs);
#if defined(CONFIG_USER_ONLY)
/* We are emulating the kernel, which will trap and emulate float128. */
diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c
index d1586b2..07ea81a 100644
--- a/target/sparc/gdbstub.c
+++ b/target/sparc/gdbstub.c
@@ -29,8 +29,7 @@
int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
+ CPUSPARCState *env = cpu_env(cs);
if (n < 8) {
/* g0..g7 */
diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c
index 058dd71..6b7d65b 100644
--- a/target/sparc/int32_helper.c
+++ b/target/sparc/int32_helper.c
@@ -99,8 +99,7 @@
void sparc_cpu_do_interrupt(CPUState *cs)
{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
+ CPUSPARCState *env = cpu_env(cs);
int cwp, intno = cs->exception_index;
if (qemu_loglevel_mask(CPU_LOG_INT)) {
diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c
index 27df9db..bd14c7a 100644
--- a/target/sparc/int64_helper.c
+++ b/target/sparc/int64_helper.c
@@ -130,8 +130,7 @@
void sparc_cpu_do_interrupt(CPUState *cs)
{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
+ CPUSPARCState *env = cpu_env(cs);
int intno = cs->exception_index;
trap_state *tsptr;
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 1ecd58e..e581bb4 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -418,8 +418,7 @@
bool is_write, bool is_exec, int is_asi,
unsigned size, uintptr_t retaddr)
{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
+ CPUSPARCState *env = cpu_env(cs);
int fault_type;
#ifdef DEBUG_UNASSIGNED
@@ -480,8 +479,7 @@
bool is_write, bool is_exec, int is_asi,
unsigned size, uintptr_t retaddr)
{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
+ CPUSPARCState *env = cpu_env(cs);
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index e7b1997..ad1591d 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -206,8 +206,7 @@
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
+ CPUSPARCState *env = cpu_env(cs);
CPUTLBEntryFull full = {};
target_ulong vaddr;
int error_code = 0, access_index;
@@ -391,8 +390,7 @@
int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address,
uint8_t *buf, int len, bool is_write)
{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
+ CPUSPARCState *env = cpu_env(cs);
target_ulong addr = address;
int i;
int len1;
@@ -759,8 +757,7 @@
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
+ CPUSPARCState *env = cpu_env(cs);
CPUTLBEntryFull full = {};
int error_code = 0, access_index;
@@ -898,8 +895,7 @@
hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
+ CPUSPARCState *env = cpu_env(cs);
hwaddr phys_addr;
int mmu_idx = cpu_mmu_index(cs, false);
@@ -916,8 +912,7 @@
int mmu_idx,
uintptr_t retaddr)
{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
+ CPUSPARCState *env = cpu_env(cs);
#ifdef TARGET_SPARC64
env->dmmu.sfsr = build_sfsr(env, mmu_idx, access_type);
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 692ce0b..319934d 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4844,13 +4844,12 @@
static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUSPARCState *env = cpu_env(cs);
int bound;
dc->pc = dc->base.pc_first;
dc->npc = (target_ulong)dc->base.tb->cs_base;
dc->mem_idx = dc->base.tb->flags & TB_FLAG_MMU_MASK;
- dc->def = &env->def;
+ dc->def = &cpu_env(cs)->def;
dc->fpu_enabled = tb_fpu_enabled(dc->base.tb->flags);
dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags);
#ifndef CONFIG_USER_ONLY
@@ -4900,10 +4899,9 @@
static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUSPARCState *env = cpu_env(cs);
unsigned int insn;
- insn = translator_ldl(env, &dc->base, dc->pc);
+ insn = translator_ldl(cpu_env(cs), &dc->base, dc->pc);
dc->base.pc_next += 4;
if (!decode(dc, insn)) {
@@ -5106,8 +5104,7 @@
const TranslationBlock *tb,
const uint64_t *data)
{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
+ CPUSPARCState *env = cpu_env(cs);
target_ulong pc = data[0];
target_ulong npc = data[1];
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 74e8a22..a9af73a 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -36,52 +36,38 @@
static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
{
- TriCoreCPU *cpu = TRICORE_CPU(cs);
- CPUTriCoreState *env = &cpu->env;
-
- env->PC = value & ~(target_ulong)1;
+ cpu_env(cs)->PC = value & ~(target_ulong)1;
}
static vaddr tricore_cpu_get_pc(CPUState *cs)
{
- TriCoreCPU *cpu = TRICORE_CPU(cs);
- CPUTriCoreState *env = &cpu->env;
-
- return env->PC;
+ return cpu_env(cs)->PC;
}
static void tricore_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
- TriCoreCPU *cpu = TRICORE_CPU(cs);
- CPUTriCoreState *env = &cpu->env;
-
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
- env->PC = tb->pc;
+ cpu_env(cs)->PC = tb->pc;
}
static void tricore_restore_state_to_opc(CPUState *cs,
const TranslationBlock *tb,
const uint64_t *data)
{
- TriCoreCPU *cpu = TRICORE_CPU(cs);
- CPUTriCoreState *env = &cpu->env;
-
- env->PC = data[0];
+ cpu_env(cs)->PC = data[0];
}
static void tricore_cpu_reset_hold(Object *obj)
{
- CPUState *s = CPU(obj);
- TriCoreCPU *cpu = TRICORE_CPU(s);
- TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(cpu);
- CPUTriCoreState *env = &cpu->env;
+ CPUState *cs = CPU(obj);
+ TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(obj);
if (tcc->parent_phases.hold) {
tcc->parent_phases.hold(obj);
}
- cpu_state_reset(env);
+ cpu_state_reset(cpu_env(cs));
}
static bool tricore_cpu_has_work(CPUState *cs)
diff --git a/target/tricore/gdbstub.c b/target/tricore/gdbstub.c
index e8f8e5e..f9309c5 100644
--- a/target/tricore/gdbstub.c
+++ b/target/tricore/gdbstub.c
@@ -106,8 +106,7 @@
int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- TriCoreCPU *cpu = TRICORE_CPU(cs);
- CPUTriCoreState *env = &cpu->env;
+ CPUTriCoreState *env = cpu_env(cs);
if (n < 16) { /* data registers */
return gdb_get_reg32(mem_buf, env->gpr_d[n]);
@@ -121,8 +120,7 @@
int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- TriCoreCPU *cpu = TRICORE_CPU(cs);
- CPUTriCoreState *env = &cpu->env;
+ CPUTriCoreState *env = cpu_env(cs);
uint32_t tmp;
tmp = ldl_p(mem_buf);
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index 649373a..6d9e80c 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -67,8 +67,7 @@
MMUAccessType rw, int mmu_idx,
bool probe, uintptr_t retaddr)
{
- TriCoreCPU *cpu = TRICORE_CPU(cs);
- CPUTriCoreState *env = &cpu->env;
+ CPUTriCoreState *env = cpu_env(cs);
hwaddr physical;
int prot;
int ret = 0;
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 278c514..c45e1d9 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -95,8 +95,7 @@
void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
- TriCoreCPU *cpu = TRICORE_CPU(cs);
- CPUTriCoreState *env = &cpu->env;
+ CPUTriCoreState *env = cpu_env(cs);
uint32_t psw;
int i;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 79f9181..875cf84 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -95,10 +95,9 @@
static void xtensa_cpu_reset_hold(Object *obj)
{
- CPUState *s = CPU(obj);
- XtensaCPU *cpu = XTENSA_CPU(s);
- XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
- CPUXtensaState *env = &cpu->env;
+ CPUState *cs = CPU(obj);
+ XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
+ CPUXtensaState *env = cpu_env(cs);
bool dfpu = xtensa_option_enabled(env->config,
XTENSA_OPTION_DFP_COPROCESSOR);
@@ -132,7 +131,7 @@
#ifndef CONFIG_USER_ONLY
reset_mmu(env);
- s->halted = env->runstall;
+ cs->halted = env->runstall;
#endif
set_no_signaling_nans(!dfpu, &env->fp_status);
set_use_first_nan(!dfpu, &env->fp_status);
diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c
index 497dafc..5546c82 100644
--- a/target/xtensa/dbg_helper.c
+++ b/target/xtensa/dbg_helper.c
@@ -66,8 +66,7 @@
bool xtensa_debug_check_breakpoint(CPUState *cs)
{
- XtensaCPU *cpu = XTENSA_CPU(cs);
- CPUXtensaState *env = &cpu->env;
+ CPUXtensaState *env = cpu_env(cs);
unsigned int i;
if (xtensa_get_cintlevel(env) >= env->config->debug_level) {
diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c
index 168419a..0514c2c 100644
--- a/target/xtensa/exc_helper.c
+++ b/target/xtensa/exc_helper.c
@@ -205,8 +205,7 @@
/* Called from cpu_handle_interrupt with BQL held */
void xtensa_cpu_do_interrupt(CPUState *cs)
{
- XtensaCPU *cpu = XTENSA_CPU(cs);
- CPUXtensaState *env = &cpu->env;
+ CPUXtensaState *env = cpu_env(cs);
if (cs->exception_index == EXC_IRQ) {
qemu_log_mask(CPU_LOG_INT,
diff --git a/target/xtensa/gdbstub.c b/target/xtensa/gdbstub.c
index 4b3bfb7..4748fb6 100644
--- a/target/xtensa/gdbstub.c
+++ b/target/xtensa/gdbstub.c
@@ -65,8 +65,7 @@
int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- XtensaCPU *cpu = XTENSA_CPU(cs);
- CPUXtensaState *env = &cpu->env;
+ CPUXtensaState *env = cpu_env(cs);
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
#ifdef CONFIG_USER_ONLY
int num_regs = env->config->gdb_regmap.num_core_regs;
@@ -120,8 +119,7 @@
int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- XtensaCPU *cpu = XTENSA_CPU(cs);
- CPUXtensaState *env = &cpu->env;
+ CPUXtensaState *env = cpu_env(cs);
uint32_t tmp;
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
#ifdef CONFIG_USER_ONLY
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index a9f8907..ca214b9 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -217,8 +217,7 @@
void xtensa_breakpoint_handler(CPUState *cs)
{
- XtensaCPU *cpu = XTENSA_CPU(cs);
- CPUXtensaState *env = &cpu->env;
+ CPUXtensaState *env = cpu_env(cs);
if (cs->watchpoint_hit) {
if (cs->watchpoint_hit->flags & BP_CPU) {
@@ -266,8 +265,7 @@
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
- XtensaCPU *cpu = XTENSA_CPU(cs);
- CPUXtensaState *env = &cpu->env;
+ CPUXtensaState *env = cpu_env(cs);
uint32_t paddr;
uint32_t page_size;
unsigned access;
@@ -297,8 +295,7 @@
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr)
{
- XtensaCPU *cpu = XTENSA_CPU(cs);
- CPUXtensaState *env = &cpu->env;
+ CPUXtensaState *env = cpu_env(cs);
cpu_restore_state(cs, retaddr);
HELPER(exception_cause_vaddr)(env, env->pc,
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index e477246..b206d57 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1127,10 +1127,9 @@
CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUXtensaState *env = cpu_env(cpu);
uint32_t tb_flags = dc->base.tb->flags;
- dc->config = env->config;
+ dc->config = cpu_env(cpu)->config;
dc->pc = dc->base.pc_first;
dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK;
dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring;
@@ -1248,8 +1247,7 @@
void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
- XtensaCPU *cpu = XTENSA_CPU(cs);
- CPUXtensaState *env = &cpu->env;
+ CPUXtensaState *env = cpu_env(cs);
xtensa_isa isa = env->config->isa;
int i, j;
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index dec8ecc..56fc9cb 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1388,8 +1388,7 @@
if (!const_b) {
tcg_out_insn(s, 3510, ANDS, ext, TCG_REG_XZR, a, b);
} else {
- tcg_debug_assert(is_limm(b));
- tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, a, b);
+ tcg_out_logicali(s, I3404_ANDSI, ext, TCG_REG_XZR, a, b);
}
} else {
if (!const_b) {
@@ -1465,6 +1464,7 @@
case TCG_COND_TSTNE:
/* tst xN,0xffffffff; b.ne L -> cbnz wN,L */
if (b_const && b == UINT32_MAX) {
+ c = tcg_tst_eqne_cond(c);
ext = TCG_TYPE_I32;
need_cmp = false;
break;
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index a8a4c66..9d6e619 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -79,7 +79,7 @@
g_assert(_resp); \
_error = resp_get_error(_resp); \
g_assert(_error); \
- g_assert(g_str_equal(_error, expected_error)); \
+ g_assert_cmpstr(_error, ==, expected_error); \
qobject_unref(_resp); \
})
@@ -194,8 +194,8 @@
g_assert(resp);
error = resp_get_error(resp);
g_assert(error);
- g_assert(g_str_equal(error,
- "The requested expansion type is not supported"));
+ g_assert_cmpstr(error, ==,
+ "The requested expansion type is not supported");
qobject_unref(resp);
}
@@ -212,8 +212,9 @@
g_assert(resp);
error = resp_get_error(resp);
g_assert(error);
- g_assert(g_str_equal(error,
- "Invalid parameter type for 'props', expected: dict"));
+ g_assert_cmpstr(error, ==,
+ "Invalid parameter type for 'model.props',"
+ " expected: object");
qobject_unref(resp);
}
@@ -446,7 +447,7 @@
assert_bad_props(qts, "max");
assert_error(qts, "foo", "The CPU type 'foo' is not a recognized "
"ARM CPU type", NULL);
- assert_error(qts, "max", "Parameter 'not-a-prop' is unexpected",
+ assert_error(qts, "max", "Parameter 'model.props.not-a-prop' is unexpected",
"{ 'not-a-prop': false }");
assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL);
diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
index 4023d80..71895ab 100644
--- a/tests/qtest/migration-test.c
+++ b/tests/qtest/migration-test.c
@@ -2772,6 +2772,24 @@
}
static void *
+test_migrate_precopy_tcp_multifd_start_zero_page_legacy(QTestState *from,
+ QTestState *to)
+{
+ test_migrate_precopy_tcp_multifd_start_common(from, to, "none");
+ migrate_set_parameter_str(from, "zero-page-detection", "legacy");
+ return NULL;
+}
+
+static void *
+test_migration_precopy_tcp_multifd_start_no_zero_page(QTestState *from,
+ QTestState *to)
+{
+ test_migrate_precopy_tcp_multifd_start_common(from, to, "none");
+ migrate_set_parameter_str(from, "zero-page-detection", "none");
+ return NULL;
+}
+
+static void *
test_migrate_precopy_tcp_multifd_zlib_start(QTestState *from,
QTestState *to)
{
@@ -2812,6 +2830,36 @@
test_precopy_common(&args);
}
+static void test_multifd_tcp_zero_page_legacy(void)
+{
+ MigrateCommon args = {
+ .listen_uri = "defer",
+ .start_hook = test_migrate_precopy_tcp_multifd_start_zero_page_legacy,
+ /*
+ * Multifd is more complicated than most of the features, it
+ * directly takes guest page buffers when sending, make sure
+ * everything will work alright even if guest page is changing.
+ */
+ .live = true,
+ };
+ test_precopy_common(&args);
+}
+
+static void test_multifd_tcp_no_zero_page(void)
+{
+ MigrateCommon args = {
+ .listen_uri = "defer",
+ .start_hook = test_migration_precopy_tcp_multifd_start_no_zero_page,
+ /*
+ * Multifd is more complicated than most of the features, it
+ * directly takes guest page buffers when sending, make sure
+ * everything will work alright even if guest page is changing.
+ */
+ .live = true,
+ };
+ test_precopy_common(&args);
+}
+
static void test_multifd_tcp_zlib(void)
{
MigrateCommon args = {
@@ -3729,6 +3777,10 @@
}
migration_test_add("/migration/multifd/tcp/plain/none",
test_multifd_tcp_none);
+ migration_test_add("/migration/multifd/tcp/plain/zero-page/legacy",
+ test_multifd_tcp_zero_page_legacy);
+ migration_test_add("/migration/multifd/tcp/plain/zero-page/none",
+ test_multifd_tcp_no_zero_page);
migration_test_add("/migration/multifd/tcp/plain/cancel",
test_multifd_tcp_cancel);
migration_test_add("/migration/multifd/tcp/plain/zlib",
diff --git a/tests/unit/test-vmstate.c b/tests/unit/test-vmstate.c
index c4f9faa..63f28f2 100644
--- a/tests/unit/test-vmstate.c
+++ b/tests/unit/test-vmstate.c
@@ -24,7 +24,6 @@
#include "qemu/osdep.h"
-#include "../migration/migration.h"
#include "migration/vmstate.h"
#include "migration/qemu-file-types.h"
#include "../migration/qemu-file.h"
diff --git a/tools/ebpf/rss.bpf.c b/tools/ebpf/rss.bpf.c
index 20f227e..9715d11 100644
--- a/tools/ebpf/rss.bpf.c
+++ b/tools/ebpf/rss.bpf.c
@@ -81,6 +81,7 @@
__uint(key_size, sizeof(__u32));
__uint(value_size, sizeof(struct rss_config_t));
__uint(max_entries, 1);
+ __uint(map_flags, BPF_F_MMAPABLE);
} tap_rss_map_configurations SEC(".maps");
struct {
@@ -88,6 +89,7 @@
__uint(key_size, sizeof(__u32));
__uint(value_size, sizeof(struct toeplitz_key_data_t));
__uint(max_entries, 1);
+ __uint(map_flags, BPF_F_MMAPABLE);
} tap_rss_map_toeplitz_key SEC(".maps");
struct {
@@ -95,6 +97,7 @@
__uint(key_size, sizeof(__u32));
__uint(value_size, sizeof(__u16));
__uint(max_entries, INDIRECTION_TABLE_SIZE);
+ __uint(map_flags, BPF_F_MMAPABLE);
} tap_rss_map_indirection_table SEC(".maps");
static inline void net_rx_rss_add_chunk(__u8 *rss_input, size_t *bytes_written,
@@ -317,7 +320,7 @@
info->in_src = ip.saddr;
info->in_dst = ip.daddr;
- info->is_fragmented = !!ip.frag_off;
+ info->is_fragmented = !!(bpf_ntohs(ip.frag_off) & (0x2000 | 0x1fff));
l4_protocol = ip.protocol;
l4_offset = ip.ihl * 4;
@@ -528,7 +531,7 @@
return result;
}
-SEC("tun_rss_steering")
+SEC("socket")
int tun_rss_steering_prog(struct __sk_buff *skb)
{
diff --git a/ui/dbus-listener.c b/ui/dbus-listener.c
index 18f556a..4a0a5d7 100644
--- a/ui/dbus-listener.c
+++ b/ui/dbus-listener.c
@@ -83,6 +83,9 @@
egl_fb fb;
#endif
#endif
+
+ guint dbus_filter;
+ guint32 out_serial_to_discard;
};
G_DEFINE_TYPE(DBusDisplayListener, dbus_display_listener, G_TYPE_OBJECT)
@@ -90,6 +93,12 @@
static void dbus_gfx_update(DisplayChangeListener *dcl,
int x, int y, int w, int h);
+static void ddl_discard_pending_messages(DBusDisplayListener *ddl)
+{
+ ddl->out_serial_to_discard = g_dbus_connection_get_last_serial(
+ g_dbus_proxy_get_connection(G_DBUS_PROXY(ddl->proxy)));
+}
+
#ifdef CONFIG_OPENGL
static void dbus_scanout_disable(DisplayChangeListener *dcl)
{
@@ -276,6 +285,8 @@
return;
}
+ ddl_discard_pending_messages(ddl);
+
/* FIXME: add missing x/y/w/h support */
qemu_dbus_display1_listener_call_scanout_dmabuf(
ddl->proxy,
@@ -323,6 +334,8 @@
return false;
}
+ ddl_discard_pending_messages(ddl);
+
if (!qemu_dbus_display1_listener_win32_map_call_scanout_map_sync(
ddl->map_proxy,
GPOINTER_TO_UINT(target_handle),
@@ -384,6 +397,8 @@
return false;
}
+ ddl_discard_pending_messages(ddl);
+
qemu_dbus_display1_listener_win32_d3d11_call_scanout_texture2d(
ddl->d3d11_proxy,
GPOINTER_TO_INT(target_handle),
@@ -630,11 +645,28 @@
DBUS_DEFAULT_TIMEOUT, NULL, NULL, NULL);
}
+static void ddl_scanout(DBusDisplayListener *ddl)
+{
+ GVariant *v_data;
+
+ v_data = g_variant_new_from_data(
+ G_VARIANT_TYPE("ay"), surface_data(ddl->ds),
+ surface_stride(ddl->ds) * surface_height(ddl->ds), TRUE,
+ (GDestroyNotify)pixman_image_unref, pixman_image_ref(ddl->ds->image));
+
+ ddl_discard_pending_messages(ddl);
+
+ qemu_dbus_display1_listener_call_scanout(
+ ddl->proxy, surface_width(ddl->ds), surface_height(ddl->ds),
+ surface_stride(ddl->ds), surface_format(ddl->ds), v_data,
+ G_DBUS_CALL_FLAGS_NONE, DBUS_DEFAULT_TIMEOUT, NULL, NULL,
+ g_object_ref(ddl));
+}
+
static void dbus_gfx_update(DisplayChangeListener *dcl,
int x, int y, int w, int h)
{
DBusDisplayListener *ddl = container_of(dcl, DBusDisplayListener, dcl);
- GVariant *v_data;
assert(ddl->ds);
@@ -652,23 +684,7 @@
#endif
if (x == 0 && y == 0 && w == surface_width(ddl->ds) && h == surface_height(ddl->ds)) {
- v_data = g_variant_new_from_data(
- G_VARIANT_TYPE("ay"),
- surface_data(ddl->ds),
- surface_stride(ddl->ds) * surface_height(ddl->ds),
- TRUE,
- (GDestroyNotify)pixman_image_unref,
- pixman_image_ref(ddl->ds->image));
- qemu_dbus_display1_listener_call_scanout(
- ddl->proxy,
- surface_width(ddl->ds),
- surface_height(ddl->ds),
- surface_stride(ddl->ds),
- surface_format(ddl->ds),
- v_data,
- G_DBUS_CALL_FLAGS_NONE,
- DBUS_DEFAULT_TIMEOUT, NULL, NULL, NULL);
- return;
+ return ddl_scanout(ddl);
}
dbus_gfx_update_sub(ddl, x, y, w, h);
@@ -964,6 +980,28 @@
#endif
}
+static GDBusMessage *
+dbus_filter(GDBusConnection *connection,
+ GDBusMessage *message,
+ gboolean incoming,
+ gpointer user_data)
+{
+ DBusDisplayListener *ddl = DBUS_DISPLAY_LISTENER(user_data);
+ guint32 serial;
+
+ if (incoming) {
+ return message;
+ }
+
+ serial = g_dbus_message_get_serial(message);
+ if (serial <= ddl->out_serial_to_discard) {
+ trace_dbus_filter(serial, ddl->out_serial_to_discard);
+ return NULL;
+ }
+
+ return message;
+}
+
DBusDisplayListener *
dbus_display_listener_new(const char *bus_name,
GDBusConnection *conn,
@@ -988,6 +1026,7 @@
return NULL;
}
+ ddl->dbus_filter = g_dbus_connection_add_filter(conn, dbus_filter, g_object_ref(ddl), g_object_unref);
ddl->bus_name = g_strdup(bus_name);
ddl->conn = conn;
ddl->console = console;
diff --git a/ui/trace-events b/ui/trace-events
index 16c35c9..e6a2894 100644
--- a/ui/trace-events
+++ b/ui/trace-events
@@ -161,6 +161,7 @@
dbus_clipboard_unregister(const char *bus_name) "peer %s"
dbus_scanout_texture(uint32_t tex_id, bool backing_y_0_top, uint32_t backing_width, uint32_t backing_height, uint32_t x, uint32_t y, uint32_t w, uint32_t h) "tex_id:%u y0top:%d back:%ux%u %u+%u-%ux%u"
dbus_gl_gfx_switch(void *p) "surf: %p"
+dbus_filter(unsigned int serial, unsigned int filter) "serial=%u (<= %u)"
# egl-helpers.c
egl_init_d3d11_device(void *p) "d3d device: %p"
diff --git a/ui/vnc.c b/ui/vnc.c
index af20d24..fc12b34 100644
--- a/ui/vnc.c
+++ b/ui/vnc.c
@@ -1931,7 +1931,8 @@
}
qkbd_state_key_event(vs->vd->kbd, qcode, down);
- if (!qemu_console_is_graphic(NULL)) {
+ if (!qemu_console_is_graphic(vs->vd->dcl.con)) {
+ QemuTextConsole *con = QEMU_TEXT_CONSOLE(vs->vd->dcl.con);
bool numlock = qkbd_state_modifier_get(vs->vd->kbd, QKBD_MOD_NUMLOCK);
bool control = qkbd_state_modifier_get(vs->vd->kbd, QKBD_MOD_CTRL);
/* QEMU console emulation */
@@ -1945,88 +1946,88 @@
case 0xb8: /* Right ALT */
break;
case 0xc8:
- qemu_text_console_put_keysym(NULL, QEMU_KEY_UP);
+ qemu_text_console_put_keysym(con, QEMU_KEY_UP);
break;
case 0xd0:
- qemu_text_console_put_keysym(NULL, QEMU_KEY_DOWN);
+ qemu_text_console_put_keysym(con, QEMU_KEY_DOWN);
break;
case 0xcb:
- qemu_text_console_put_keysym(NULL, QEMU_KEY_LEFT);
+ qemu_text_console_put_keysym(con, QEMU_KEY_LEFT);
break;
case 0xcd:
- qemu_text_console_put_keysym(NULL, QEMU_KEY_RIGHT);
+ qemu_text_console_put_keysym(con, QEMU_KEY_RIGHT);
break;
case 0xd3:
- qemu_text_console_put_keysym(NULL, QEMU_KEY_DELETE);
+ qemu_text_console_put_keysym(con, QEMU_KEY_DELETE);
break;
case 0xc7:
- qemu_text_console_put_keysym(NULL, QEMU_KEY_HOME);
+ qemu_text_console_put_keysym(con, QEMU_KEY_HOME);
break;
case 0xcf:
- qemu_text_console_put_keysym(NULL, QEMU_KEY_END);
+ qemu_text_console_put_keysym(con, QEMU_KEY_END);
break;
case 0xc9:
- qemu_text_console_put_keysym(NULL, QEMU_KEY_PAGEUP);
+ qemu_text_console_put_keysym(con, QEMU_KEY_PAGEUP);
break;
case 0xd1:
- qemu_text_console_put_keysym(NULL, QEMU_KEY_PAGEDOWN);
+ qemu_text_console_put_keysym(con, QEMU_KEY_PAGEDOWN);
break;
case 0x47:
- qemu_text_console_put_keysym(NULL, numlock ? '7' : QEMU_KEY_HOME);
+ qemu_text_console_put_keysym(con, numlock ? '7' : QEMU_KEY_HOME);
break;
case 0x48:
- qemu_text_console_put_keysym(NULL, numlock ? '8' : QEMU_KEY_UP);
+ qemu_text_console_put_keysym(con, numlock ? '8' : QEMU_KEY_UP);
break;
case 0x49:
- qemu_text_console_put_keysym(NULL, numlock ? '9' : QEMU_KEY_PAGEUP);
+ qemu_text_console_put_keysym(con, numlock ? '9' : QEMU_KEY_PAGEUP);
break;
case 0x4b:
- qemu_text_console_put_keysym(NULL, numlock ? '4' : QEMU_KEY_LEFT);
+ qemu_text_console_put_keysym(con, numlock ? '4' : QEMU_KEY_LEFT);
break;
case 0x4c:
- qemu_text_console_put_keysym(NULL, '5');
+ qemu_text_console_put_keysym(con, '5');
break;
case 0x4d:
- qemu_text_console_put_keysym(NULL, numlock ? '6' : QEMU_KEY_RIGHT);
+ qemu_text_console_put_keysym(con, numlock ? '6' : QEMU_KEY_RIGHT);
break;
case 0x4f:
- qemu_text_console_put_keysym(NULL, numlock ? '1' : QEMU_KEY_END);
+ qemu_text_console_put_keysym(con, numlock ? '1' : QEMU_KEY_END);
break;
case 0x50:
- qemu_text_console_put_keysym(NULL, numlock ? '2' : QEMU_KEY_DOWN);
+ qemu_text_console_put_keysym(con, numlock ? '2' : QEMU_KEY_DOWN);
break;
case 0x51:
- qemu_text_console_put_keysym(NULL, numlock ? '3' : QEMU_KEY_PAGEDOWN);
+ qemu_text_console_put_keysym(con, numlock ? '3' : QEMU_KEY_PAGEDOWN);
break;
case 0x52:
- qemu_text_console_put_keysym(NULL, '0');
+ qemu_text_console_put_keysym(con, '0');
break;
case 0x53:
- qemu_text_console_put_keysym(NULL, numlock ? '.' : QEMU_KEY_DELETE);
+ qemu_text_console_put_keysym(con, numlock ? '.' : QEMU_KEY_DELETE);
break;
case 0xb5:
- qemu_text_console_put_keysym(NULL, '/');
+ qemu_text_console_put_keysym(con, '/');
break;
case 0x37:
- qemu_text_console_put_keysym(NULL, '*');
+ qemu_text_console_put_keysym(con, '*');
break;
case 0x4a:
- qemu_text_console_put_keysym(NULL, '-');
+ qemu_text_console_put_keysym(con, '-');
break;
case 0x4e:
- qemu_text_console_put_keysym(NULL, '+');
+ qemu_text_console_put_keysym(con, '+');
break;
case 0x9c:
- qemu_text_console_put_keysym(NULL, '\n');
+ qemu_text_console_put_keysym(con, '\n');
break;
default:
if (control) {
- qemu_text_console_put_keysym(NULL, sym & 0x1f);
+ qemu_text_console_put_keysym(con, sym & 0x1f);
} else {
- qemu_text_console_put_keysym(NULL, sym);
+ qemu_text_console_put_keysym(con, sym);
}
break;
}
@@ -2044,7 +2045,7 @@
int keycode;
int lsym = sym;
- if (lsym >= 'A' && lsym <= 'Z' && qemu_console_is_graphic(NULL)) {
+ if (lsym >= 'A' && lsym <= 'Z' && qemu_console_is_graphic(vs->vd->dcl.con)) {
lsym = lsym - 'A' + 'a';
}
