target/microblaze: Fix width of ESR
The exception status register is only 32-bits wide.
Do not use a 64-bit type to represent it.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c
index da5e98b..3de99ea 100644
--- a/linux-user/microblaze/cpu_loop.c
+++ b/linux-user/microblaze/cpu_loop.c
@@ -106,7 +106,7 @@
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
default:
- fprintf(stderr, "Unhandled hw-exception: 0x%" PRIx64 "\n",
+ fprintf(stderr, "Unhandled hw-exception: 0x%x\n",
env->esr & ESR_EC_MASK);
cpu_dump_state(cs, stderr, 0);
exit(EXIT_FAILURE);
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 019e5df..aaac0c9 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -239,7 +239,7 @@
uint32_t pc;
uint32_t msr;
uint64_t ear;
- uint64_t esr;
+ uint32_t esr;
uint64_t fsr;
uint64_t btr;
uint64_t edr;
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index af79091..b2373f6 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -144,7 +144,7 @@
qemu_log_mask(CPU_LOG_INT,
"hw exception at pc=%x ear=%" PRIx64 " "
- "esr=%" PRIx64 " iflags=%x\n",
+ "esr=%x iflags=%x\n",
env->pc, env->ear,
env->esr, env->iflags);
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index a7f6cb7..dc2bec0 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -76,7 +76,7 @@
int i;
qemu_log("PC=%08x\n", env->pc);
- qemu_log("rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " "
+ qemu_log("rmsr=%x resr=%x rear=%" PRIx64 " "
"debug[%x] imm=%x iflags=%x\n",
env->msr, env->esr, env->ear,
env->debug, env->imm, env->iflags);
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 0e71e7e..f63aae6 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -58,7 +58,7 @@
static TCGv_i32 cpu_pc;
static TCGv_i32 cpu_msr;
static TCGv_i64 cpu_ear;
-static TCGv_i64 cpu_esr;
+static TCGv_i32 cpu_esr;
static TCGv_i64 cpu_fsr;
static TCGv_i64 cpu_btr;
static TCGv_i64 cpu_edr;
@@ -182,7 +182,7 @@
{
if (cond && (dc->tb_flags & MSR_EE_FLAG)
&& dc->cpu->cfg.illegal_opcode_exception) {
- tcg_gen_movi_i64(cpu_esr, ESR_EC_ILLEGAL_OP);
+ tcg_gen_movi_i32(cpu_esr, ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
return cond;
@@ -198,7 +198,7 @@
bool cond_user = cond && mem_index == MMU_USER_IDX;
if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) {
- tcg_gen_movi_i64(cpu_esr, ESR_EC_PRIVINSN);
+ tcg_gen_movi_i32(cpu_esr, ESR_EC_PRIVINSN);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
return cond_user;
@@ -539,7 +539,7 @@
tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]);
break;
case SR_ESR:
- tcg_gen_extu_i32_i64(cpu_esr, cpu_R[dc->ra]);
+ tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]);
break;
case SR_FSR:
tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]);
@@ -580,7 +580,7 @@
}
break;
case SR_ESR:
- tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_esr);
+ tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr);
break;
case SR_FSR:
tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr);
@@ -1399,7 +1399,7 @@
static int dec_check_fpuv2(DisasContext *dc)
{
if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) {
- tcg_gen_movi_i64(cpu_esr, ESR_EC_FPU);
+ tcg_gen_movi_i32(cpu_esr, ESR_EC_FPU);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0;
@@ -1797,7 +1797,7 @@
qemu_fprintf(f, "IN: PC=%x %s\n",
env->pc, lookup_symbol(env->pc));
- qemu_fprintf(f, "rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " "
+ qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " "
"debug=%x imm=%x iflags=%x fsr=%" PRIx64 " "
"rbtr=%" PRIx64 "\n",
env->msr, env->esr, env->ear,
@@ -1866,7 +1866,7 @@
cpu_ear =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear");
cpu_esr =
- tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr");
+ tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr");
cpu_fsr =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr");
cpu_btr =
