hw/arm/mps2: New board model mps2-an500
Implement a model of the MPS2 with the AN500 firmware. This is
similar to the AN385, with the following differences:
* Cortex-M7 CPU
* PSRAM is at 0x6000_0000
* Ethernet is at 0xa000_0000
* No zbt_boot_ctrl remapping of the low 16K
(but QEMU doesn't implement this anyway)
* no "block RAM" at 0x01000000
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200903202048.15370-3-peter.maydell@linaro.org
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
index e680a4c..7f2e9c8 100644
--- a/docs/system/arm/mps2.rst
+++ b/docs/system/arm/mps2.rst
@@ -1,5 +1,5 @@
-Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
-================================================================================================
+Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
+================================================================================================================
These board models all use Arm M-profile CPUs.
@@ -14,6 +14,8 @@
Cortex-M3 as documented in ARM Application Note AN385
``mps2-an386``
Cortex-M4 as documented in ARM Application Note AN386
+``mps2-an500``
+ Cortex-M7 as documented in ARM Application Note AN500
``mps2-an511``
Cortex-M3 'DesignStart' as documented in AN511
``mps2-an505``
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index d3ec73f..5d47160 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -16,6 +16,7 @@
* We model the following FPGA images:
* "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
* "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
+ * "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500
* "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
*
* Links to the TRM for the board itself and to the various Application
@@ -50,6 +51,7 @@
typedef enum MPS2FPGAType {
FPGA_AN385,
FPGA_AN386,
+ FPGA_AN500,
FPGA_AN511,
} MPS2FPGAType;
@@ -57,6 +59,9 @@
MachineClass parent;
MPS2FPGAType fpga_type;
uint32_t scc_id;
+ bool has_block_ram;
+ hwaddr ethernet_base;
+ hwaddr psram_base;
};
typedef struct MPS2MachineClass MPS2MachineClass;
@@ -85,6 +90,7 @@
#define TYPE_MPS2_MACHINE "mps2"
#define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
#define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386")
+#define TYPE_MPS2_AN500_MACHINE MACHINE_TYPE_NAME("mps2-an500")
#define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
DECLARE_OBJ_CHECKERS(MPS2MachineState, MPS2MachineClass,
@@ -144,11 +150,12 @@
*
* AN385/AN386/AN511:
* 0x21000000 .. 0x21ffffff : PSRAM (16MB)
- * AN385/AN386 only:
+ * AN385/AN386/AN500:
* 0x00000000 .. 0x003fffff : ZBT SSRAM1
* 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
* 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
* 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
+ * AN385/AN386 only:
* 0x01000000 .. 0x01003fff : block RAM (16K)
* 0x01004000 .. 0x01007fff : mirror of above
* 0x01008000 .. 0x0100bfff : mirror of above
@@ -158,22 +165,17 @@
* 0x00400000 .. 0x007fffff : ZBT SSRAM1
* 0x20000000 .. 0x2001ffff : SRAM
* 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
+ * AN500 only:
+ * 0x60000000 .. 0x60ffffff : PSRAM (16MB)
*
* The AN385/AN386 has a feature where the lowest 16K can be mapped
* either to the bottom of the ZBT SSRAM1 or to the block RAM.
* This is of no use for QEMU so we don't implement it (as if
* zbt_boot_ctrl is always zero).
*/
- memory_region_add_subregion(system_memory, 0x21000000, machine->ram);
+ memory_region_add_subregion(system_memory, mmc->psram_base, machine->ram);
- switch (mmc->fpga_type) {
- case FPGA_AN385:
- case FPGA_AN386:
- make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
- make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
- make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
- make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
- &mms->ssram23, 0x20400000);
+ if (mmc->has_block_ram) {
make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000);
make_ram_alias(&mms->blockram_m1, "mps.blockram_m1",
&mms->blockram, 0x01004000);
@@ -181,6 +183,17 @@
&mms->blockram, 0x01008000);
make_ram_alias(&mms->blockram_m3, "mps.blockram_m3",
&mms->blockram, 0x0100c000);
+ }
+
+ switch (mmc->fpga_type) {
+ case FPGA_AN385:
+ case FPGA_AN386:
+ case FPGA_AN500:
+ make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
+ make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
+ make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
+ make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
+ &mms->ssram23, 0x20400000);
break;
case FPGA_AN511:
make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000);
@@ -197,6 +210,7 @@
switch (mmc->fpga_type) {
case FPGA_AN385:
case FPGA_AN386:
+ case FPGA_AN500:
qdev_prop_set_uint32(armv7m, "num-irq", 32);
break;
case FPGA_AN511:
@@ -234,6 +248,7 @@
switch (mmc->fpga_type) {
case FPGA_AN385:
case FPGA_AN386:
+ case FPGA_AN500:
{
/* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
* Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
@@ -383,7 +398,7 @@
/* In hardware this is a LAN9220; the LAN9118 is software compatible
* except that it doesn't support the checksum-offload feature.
*/
- lan9118_init(&nd_table[0], 0x40200000,
+ lan9118_init(&nd_table[0], mmc->ethernet_base,
qdev_get_gpio_in(armv7m,
mmc->fpga_type == FPGA_AN511 ? 47 : 13));
@@ -412,6 +427,9 @@
mmc->fpga_type = FPGA_AN385;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
mmc->scc_id = 0x41043850;
+ mmc->psram_base = 0x21000000;
+ mmc->ethernet_base = 0x40200000;
+ mmc->has_block_ram = true;
}
static void mps2_an386_class_init(ObjectClass *oc, void *data)
@@ -423,6 +441,23 @@
mmc->fpga_type = FPGA_AN386;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
mmc->scc_id = 0x41043860;
+ mmc->psram_base = 0x21000000;
+ mmc->ethernet_base = 0x40200000;
+ mmc->has_block_ram = true;
+}
+
+static void mps2_an500_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
+
+ mc->desc = "ARM MPS2 with AN500 FPGA image for Cortex-M7";
+ mmc->fpga_type = FPGA_AN500;
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m7");
+ mmc->scc_id = 0x41045000;
+ mmc->psram_base = 0x60000000;
+ mmc->ethernet_base = 0xa0000000;
+ mmc->has_block_ram = false;
}
static void mps2_an511_class_init(ObjectClass *oc, void *data)
@@ -434,6 +469,9 @@
mmc->fpga_type = FPGA_AN511;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
mmc->scc_id = 0x41045110;
+ mmc->psram_base = 0x21000000;
+ mmc->ethernet_base = 0x40200000;
+ mmc->has_block_ram = false;
}
static const TypeInfo mps2_info = {
@@ -457,6 +495,12 @@
.class_init = mps2_an386_class_init,
};
+static const TypeInfo mps2_an500_info = {
+ .name = TYPE_MPS2_AN500_MACHINE,
+ .parent = TYPE_MPS2_MACHINE,
+ .class_init = mps2_an500_class_init,
+};
+
static const TypeInfo mps2_an511_info = {
.name = TYPE_MPS2_AN511_MACHINE,
.parent = TYPE_MPS2_MACHINE,
@@ -468,6 +512,7 @@
type_register_static(&mps2_info);
type_register_static(&mps2_an385_info);
type_register_static(&mps2_an386_info);
+ type_register_static(&mps2_an500_info);
type_register_static(&mps2_an511_info);
}
