tree 881383c71e65e37dda854b617a91c98b6138172b
parent bfe43e3d14687f2149451f278671c2c552d96b0a
author Richard Henderson <richard.henderson@linaro.org> 1654867955 +0100
committer Peter Maydell <peter.maydell@linaro.org> 1654867955 +0100

target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12]

Since DDI0487F.a, the RW bit is RAO/WI.  When specifically
targeting such a cpu, e.g. cortex-a76, it is legitimate to
ignore the bit within the secure monitor.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1062
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609214657.1217913-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>