commit 6bc3dfa96de4173b12929824eaf80fc95d22ac28
author Frank Chang <frank.chang@sifive.com> Fri Dec 10 15:55:57 2021 +0800
committer Alistair Francis <alistair.francis@wdc.com> Mon Dec 20 14:51:36 2021 +1000
tree 651a05495cf41e0b382f85da89b175aa640a17ef
parent 2e56505475cba574ff041cd9d57d417c7d705d24

target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-12-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

target/riscv/csr.c

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5d1eec1..3dfbc17 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -48,6 +48,11 @@
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
     if (env->misa_ext & RVV) {
+#if !defined(CONFIG_USER_ONLY)
+        if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+            return RISCV_EXCP_ILLEGAL_INST;
+        }
+#endif
         return RISCV_EXCP_NONE;
     }
     return RISCV_EXCP_ILLEGAL_INST;