commit 680af1b4a523cd7f15690cad7afb069e6efbbec0
author Richard Henderson <richard.henderson@linaro.org> Sat Nov 04 18:22:42 2023 -0700
committer Richard Henderson <richard.henderson@linaro.org> Wed Jun 05 09:08:39 2024 -0700
tree bcbe4bb2b21e4f9d253d85f078f3352e78baac2a
parent 7d5ebd8ffe241c57d6857ae75b67de6c6af3429c

target/sparc: Implement UMULXHI

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/sparc/insns.decode

diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 09c8adc..508175e 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -389,6 +389,7 @@
 
     ADDXC       10 ..... 110110 ..... 0 0001 0001 .....    @r_r_r
     ADDXCcc     10 ..... 110110 ..... 0 0001 0011 .....    @r_r_r
+    UMULXHI     10 ..... 110110 ..... 0 0001 0110 .....    @r_r_r
     LZCNT       10 ..... 110110 00000 0 0001 0111 .....    @r_r2
 
     ALIGNADDR   10 ..... 110110 ..... 0 0001 1000 .....    @r_r_r

target/sparc/translate.c

diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 2480eed..2a38152 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -581,6 +581,12 @@
     gen_op_multiply(dst, src1, src2, 1);
 }
 
+static void gen_op_umulxhi(TCGv dst, TCGv src1, TCGv src2)
+{
+    TCGv discard = tcg_temp_new();
+    tcg_gen_mulu2_tl(discard, dst, src1, src2);
+}
+
 static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2)
 {
 #ifdef TARGET_SPARC64
@@ -3919,6 +3925,8 @@
 TRANS(ADDXC, VIS3, do_rrr, a, gen_op_addxc)
 TRANS(ADDXCcc, VIS3, do_rrr, a, gen_op_addxccc)
 
+TRANS(UMULXHI, VIS3, do_rrr, a, gen_op_umulxhi)
+
 static void gen_op_alignaddr(TCGv dst, TCGv s1, TCGv s2)
 {
 #ifdef TARGET_SPARC64