)]}'
{
  "commit": "64fdbae7e1bc6408204a3cf3b8e6a2e7d8e36fe2",
  "tree": "b0e863e58e9fe29dc6b1519e04c6d9804d97b04f",
  "parents": [
    "785fd1a9afd5cb894f3e53753d732c7fbbb3d74a"
  ],
  "author": {
    "name": "Philippe Mathieu-Daudé",
    "email": "philmd@linaro.org",
    "time": "Sat Nov 09 19:45:58 2024 +0100"
  },
  "committer": {
    "name": "Philippe Mathieu-Daudé",
    "email": "philmd@linaro.org",
    "time": "Mon Jan 13 17:16:03 2025 +0100"
  },
  "message": "hw/net/xilinx_ethlite: Access TX_GIE register for each port\n\nRather than accessing the registers within the mixed RAM/MMIO\nregion as indexed register, declare a per-port TX_GIE. This\nwill help to map the RAM as RAM (keeping MMIO as MMIO) in few\ncommits.\n\nPrevious s-\u003eregs[R_TX_GIE0] and s-\u003eregs[R_TX_GIE1] are now\nunused. Not a concern, this array will soon disappear.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Edgar E. Iglesias \u003cedgar.iglesias@amd.com\u003e\nMessage-Id: \u003c20241112181044.92193-13-philmd@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "67adecc0883b93f880c4a5f50ca23c5619a8b687",
      "old_mode": 33188,
      "old_path": "hw/net/xilinx_ethlite.c",
      "new_id": "3252c9d508a33464717115681be3eaf39936ccd4",
      "new_mode": 33188,
      "new_path": "hw/net/xilinx_ethlite.c"
    }
  ]
}