Merge tag 'hw-misc-20241105' of https://github.com/philmd/qemu into staging
Misc HW patch queue
- Deprecate a pair of untested microblaze big-endian machines (Philippe)
- Arch-agnostic CPU topology checks at machine level (Zhao)
- Cleanups on PPC E500 (Bernhard)
- Various conversions to DEFINE_TYPES() macro (Bernhard)
- Fix RISC-V _pext_u64() name clashing (Pierrick)
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# gpg: Signature made Tue 05 Nov 2024 23:32:55 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'hw-misc-20241105' of https://github.com/philmd/qemu: (29 commits)
hw/riscv/iommu: fix build error with clang
hw/usb/hcd-ehci-sysbus: Prefer DEFINE_TYPES() macro
hw/rtc/ds1338: Prefer DEFINE_TYPES() macro
hw/i2c/smbus_eeprom: Prefer DEFINE_TYPES() macro
hw/block/pflash_cfi01: Prefer DEFINE_TYPES() macro
hw/sd/sdhci: Prefer DEFINE_TYPES() macro
hw/ppc/mpc8544_guts: Prefer DEFINE_TYPES() macro
hw/gpio/mpc8xxx: Prefer DEFINE_TYPES() macro
hw/net/fsl_etsec/etsec: Prefer DEFINE_TYPES() macro
hw/net/fsl_etsec/miim: Reuse MII constants
hw/pci-host/ppce500: Prefer DEFINE_TYPES() macro
hw/pci-host/ppce500: Reuse TYPE_PPC_E500_PCI_BRIDGE define
hw/i2c/mpc_i2c: Prefer DEFINE_TYPES() macro
hw/i2c/mpc_i2c: Convert DPRINTF to trace events for register access
hw/ppc/mpc8544_guts: Populate POR PLL ratio status register
hw/ppc/e500: Add missing device tree properties to i2c controller node
hw/ppc/e500: Remove unused "irqs" parameter
hw/ppc/e500: Prefer QOM cast
hw/core: Add a helper to check the cache topology level
hw/core: Check smp cache topology support for machine
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/configs/devices/microblaze-softmmu/default.mak b/configs/devices/microblaze-softmmu/default.mak
index 583e395..7894106 100644
--- a/configs/devices/microblaze-softmmu/default.mak
+++ b/configs/devices/microblaze-softmmu/default.mak
@@ -2,5 +2,3 @@
# Boards are selected by default, uncomment to keep out of the build.
# CONFIG_PETALOGIX_S3ADSP1800=n
-# CONFIG_PETALOGIX_ML605=n
-# CONFIG_XLNX_ZYNQMP_PMU=n
diff --git a/configs/devices/microblazeel-softmmu/default.mak b/configs/devices/microblazeel-softmmu/default.mak
index 29f7f13..4c10864 100644
--- a/configs/devices/microblazeel-softmmu/default.mak
+++ b/configs/devices/microblazeel-softmmu/default.mak
@@ -1,3 +1,6 @@
# Default configuration for microblazeel-softmmu
-include ../microblaze-softmmu/default.mak
+# Boards are selected by default, uncomment to keep out of the build.
+# CONFIG_PETALOGIX_S3ADSP1800=n
+# CONFIG_PETALOGIX_ML605=n
+# CONFIG_XLNX_ZYNQMP_PMU=n
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 720d4ee..d8dc29d 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -271,6 +271,12 @@
of the AST2600 SoC in labs. It can be easily replaced by the
``rainier-bmc`` machine which is a real product.
+Big-Endian variants of MicroBlaze ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` machines (since 9.2)
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+Both ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` were added for little endian
+CPUs. Big endian support is not tested.
+
Backend options
---------------
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
index 7b6ec64..21a81b4 100644
--- a/hw/block/pflash_cfi01.c
+++ b/hw/block/pflash_cfi01.c
@@ -47,7 +47,6 @@
#include "qemu/bitops.h"
#include "qemu/host-utils.h"
#include "qemu/log.h"
-#include "qemu/module.h"
#include "qemu/option.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
@@ -947,20 +946,16 @@
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
-
-static const TypeInfo pflash_cfi01_info = {
- .name = TYPE_PFLASH_CFI01,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(PFlashCFI01),
- .class_init = pflash_cfi01_class_init,
+static const TypeInfo pflash_cfi01_types[] = {
+ {
+ .name = TYPE_PFLASH_CFI01,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(PFlashCFI01),
+ .class_init = pflash_cfi01_class_init,
+ },
};
-static void pflash_cfi01_register_types(void)
-{
- type_register_static(&pflash_cfi01_info);
-}
-
-type_init(pflash_cfi01_register_types)
+DEFINE_TYPES(pflash_cfi01_types)
PFlashCFI01 *pflash_cfi01_register(hwaddr base,
const char *name,
diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
index 5d8d7ed..640b211 100644
--- a/hw/core/machine-smp.c
+++ b/hw/core/machine-smp.c
@@ -261,6 +261,72 @@
}
}
+static bool machine_check_topo_support(MachineState *ms,
+ CpuTopologyLevel topo,
+ Error **errp)
+{
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
+
+ if ((topo == CPU_TOPOLOGY_LEVEL_MODULE && !mc->smp_props.modules_supported) ||
+ (topo == CPU_TOPOLOGY_LEVEL_CLUSTER && !mc->smp_props.clusters_supported) ||
+ (topo == CPU_TOPOLOGY_LEVEL_DIE && !mc->smp_props.dies_supported) ||
+ (topo == CPU_TOPOLOGY_LEVEL_BOOK && !mc->smp_props.books_supported) ||
+ (topo == CPU_TOPOLOGY_LEVEL_DRAWER && !mc->smp_props.drawers_supported)) {
+ error_setg(errp,
+ "Invalid topology level: %s. "
+ "The topology level is not supported by this machine",
+ CpuTopologyLevel_str(topo));
+ return false;
+ }
+
+ return true;
+}
+
+bool machine_parse_smp_cache(MachineState *ms,
+ const SmpCachePropertiesList *caches,
+ Error **errp)
+{
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
+ const SmpCachePropertiesList *node;
+ DECLARE_BITMAP(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX);
+
+ for (node = caches; node; node = node->next) {
+ /* Prohibit users from repeating settings. */
+ if (test_bit(node->value->cache, caches_bitmap)) {
+ error_setg(errp,
+ "Invalid cache properties: %s. "
+ "The cache properties are duplicated",
+ CacheLevelAndType_str(node->value->cache));
+ return false;
+ }
+
+ machine_set_cache_topo_level(ms, node->value->cache,
+ node->value->topology);
+ set_bit(node->value->cache, caches_bitmap);
+ }
+
+ for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) {
+ const SmpCacheProperties *props = &ms->smp_cache.props[i];
+
+ /*
+ * Reject non "default" topology level if the cache isn't
+ * supported by the machine.
+ */
+ if (props->topology != CPU_TOPOLOGY_LEVEL_DEFAULT &&
+ !mc->smp_props.cache_supported[props->cache]) {
+ error_setg(errp,
+ "%s cache topology not supported by this machine",
+ CacheLevelAndType_str(node->value->cache));
+ return false;
+ }
+
+ if (!machine_check_topo_support(ms, props->topology, errp)) {
+ return false;
+ }
+ }
+ return true;
+}
+
unsigned int machine_topo_get_cores_per_socket(const MachineState *ms)
{
return ms->smp.cores * ms->smp.modules * ms->smp.clusters * ms->smp.dies;
@@ -270,3 +336,63 @@
{
return ms->smp.threads * machine_topo_get_cores_per_socket(ms);
}
+
+CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms,
+ CacheLevelAndType cache)
+{
+ return ms->smp_cache.props[cache].topology;
+}
+
+void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache,
+ CpuTopologyLevel level)
+{
+ ms->smp_cache.props[cache].topology = level;
+}
+
+/*
+ * When both cache1 and cache2 are configured with specific topology levels
+ * (not default level), is cache1's topology level higher than cache2?
+ */
+static bool smp_cache_topo_cmp(const SmpCache *smp_cache,
+ CacheLevelAndType cache1,
+ CacheLevelAndType cache2)
+{
+ /*
+ * Before comparing, the "default" topology level should be replaced
+ * with the specific level.
+ */
+ assert(smp_cache->props[cache1].topology != CPU_TOPOLOGY_LEVEL_DEFAULT);
+
+ return smp_cache->props[cache1].topology > smp_cache->props[cache2].topology;
+}
+
+/*
+ * Currently, we have no way to expose the arch-specific default cache model
+ * because the cache model is sometimes related to the CPU model (e.g., i386).
+ *
+ * We can only check the correctness of the cache topology after the arch loads
+ * the user-configured cache model from MachineState and consumes the special
+ * "default" level by replacing it with the specific level.
+ */
+bool machine_check_smp_cache(const MachineState *ms, Error **errp)
+{
+ if (smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L1D,
+ CACHE_LEVEL_AND_TYPE_L2) ||
+ smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L1I,
+ CACHE_LEVEL_AND_TYPE_L2)) {
+ error_setg(errp,
+ "Invalid smp cache topology. "
+ "L2 cache topology level shouldn't be lower than L1 cache");
+ return false;
+ }
+
+ if (smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L2,
+ CACHE_LEVEL_AND_TYPE_L3)) {
+ error_setg(errp,
+ "Invalid smp cache topology. "
+ "L3 cache topology level shouldn't be lower than L2 cache");
+ return false;
+ }
+
+ return true;
+}
diff --git a/hw/core/machine.c b/hw/core/machine.c
index c1893fe..a35c4a8 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -11,10 +11,12 @@
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "qemu/accel.h"
#include "sysemu/replay.h"
#include "hw/boards.h"
#include "hw/loader.h"
+#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qapi/qapi-visit-machine.h"
#include "qemu/madvise.h"
@@ -907,6 +909,40 @@
machine_parse_smp_config(ms, config, errp);
}
+static void machine_get_smp_cache(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ MachineState *ms = MACHINE(obj);
+ SmpCache *cache = &ms->smp_cache;
+ SmpCachePropertiesList *head = NULL;
+ SmpCachePropertiesList **tail = &head;
+
+ for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) {
+ SmpCacheProperties *node = g_new(SmpCacheProperties, 1);
+
+ node->cache = cache->props[i].cache;
+ node->topology = cache->props[i].topology;
+ QAPI_LIST_APPEND(tail, node);
+ }
+
+ visit_type_SmpCachePropertiesList(v, name, &head, errp);
+ qapi_free_SmpCachePropertiesList(head);
+}
+
+static void machine_set_smp_cache(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ MachineState *ms = MACHINE(obj);
+ SmpCachePropertiesList *caches;
+
+ if (!visit_type_SmpCachePropertiesList(v, name, &caches, errp)) {
+ return;
+ }
+
+ machine_parse_smp_cache(ms, caches, errp);
+ qapi_free_SmpCachePropertiesList(caches);
+}
+
static void machine_get_boot(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
@@ -1067,6 +1103,11 @@
object_class_property_set_description(oc, "smp",
"CPU topology");
+ object_class_property_add(oc, "smp-cache", "SmpCachePropertiesWrapper",
+ machine_get_smp_cache, machine_set_smp_cache, NULL, NULL);
+ object_class_property_set_description(oc, "smp-cache",
+ "Cache properties list for SMP machine");
+
object_class_property_add(oc, "phandle-start", "int",
machine_get_phandle_start, machine_set_phandle_start,
NULL, NULL);
@@ -1205,6 +1246,11 @@
ms->smp.cores = 1;
ms->smp.threads = 1;
+ for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) {
+ ms->smp_cache.props[i].cache = (CacheLevelAndType)i;
+ ms->smp_cache.props[i].topology = CPU_TOPOLOGY_LEVEL_DEFAULT;
+ }
+
machine_copy_boot_config(ms, &(BootConfiguration){ 0 });
}
diff --git a/hw/gpio/mpc8xxx.c b/hw/gpio/mpc8xxx.c
index 63b7a5c..a3c1d2f 100644
--- a/hw/gpio/mpc8xxx.c
+++ b/hw/gpio/mpc8xxx.c
@@ -23,7 +23,6 @@
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
-#include "qemu/module.h"
#include "qom/object.h"
#define TYPE_MPC8XXX_GPIO "mpc8xxx_gpio"
@@ -208,17 +207,14 @@
device_class_set_legacy_reset(dc, mpc8xxx_gpio_reset);
}
-static const TypeInfo mpc8xxx_gpio_info = {
- .name = TYPE_MPC8XXX_GPIO,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(MPC8XXXGPIOState),
- .instance_init = mpc8xxx_gpio_initfn,
- .class_init = mpc8xxx_gpio_class_init,
+static const TypeInfo mpc8xxx_gpio_types[] = {
+ {
+ .name = TYPE_MPC8XXX_GPIO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MPC8XXXGPIOState),
+ .instance_init = mpc8xxx_gpio_initfn,
+ .class_init = mpc8xxx_gpio_class_init,
+ },
};
-static void mpc8xxx_gpio_register_types(void)
-{
- type_register_static(&mpc8xxx_gpio_info);
-}
-
-type_init(mpc8xxx_gpio_register_types)
+DEFINE_TYPES(mpc8xxx_gpio_types)
diff --git a/hw/i2c/mpc_i2c.c b/hw/i2c/mpc_i2c.c
index 2467d1a..913d044 100644
--- a/hw/i2c/mpc_i2c.c
+++ b/hw/i2c/mpc_i2c.c
@@ -20,10 +20,10 @@
#include "qemu/osdep.h"
#include "hw/i2c/i2c.h"
#include "hw/irq.h"
-#include "qemu/module.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qom/object.h"
+#include "trace.h"
/* #define DEBUG_I2C */
@@ -224,8 +224,8 @@
break;
}
- DPRINTF("%s: addr " HWADDR_FMT_plx " %02" PRIx32 "\n", __func__,
- addr, value);
+ trace_mpc_i2c_read(addr, value);
+
return (uint64_t)value;
}
@@ -234,8 +234,8 @@
{
MPCI2CState *s = opaque;
- DPRINTF("%s: addr " HWADDR_FMT_plx " val %08" PRIx64 "\n", __func__,
- addr, value);
+ trace_mpc_i2c_write(addr, value);
+
switch (addr) {
case MPC_I2C_ADR:
s->adr = value & CADR_MASK;
@@ -344,16 +344,13 @@
dc->desc = "MPC I2C Controller";
}
-static const TypeInfo mpc_i2c_type_info = {
- .name = TYPE_MPC_I2C,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(MPCI2CState),
- .class_init = mpc_i2c_class_init,
+static const TypeInfo mpc_i2c_types[] = {
+ {
+ .name = TYPE_MPC_I2C,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MPCI2CState),
+ .class_init = mpc_i2c_class_init,
+ },
};
-static void mpc_i2c_register_types(void)
-{
- type_register_static(&mpc_i2c_type_info);
-}
-
-type_init(mpc_i2c_register_types)
+DEFINE_TYPES(mpc_i2c_types)
diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
index 9e62c27..e3e96d4 100644
--- a/hw/i2c/smbus_eeprom.c
+++ b/hw/i2c/smbus_eeprom.c
@@ -151,19 +151,16 @@
dc->user_creatable = false;
}
-static const TypeInfo smbus_eeprom_info = {
- .name = TYPE_SMBUS_EEPROM,
- .parent = TYPE_SMBUS_DEVICE,
- .instance_size = sizeof(SMBusEEPROMDevice),
- .class_init = smbus_eeprom_class_initfn,
+static const TypeInfo smbus_eeprom_types[] = {
+ {
+ .name = TYPE_SMBUS_EEPROM,
+ .parent = TYPE_SMBUS_DEVICE,
+ .instance_size = sizeof(SMBusEEPROMDevice),
+ .class_init = smbus_eeprom_class_initfn,
+ },
};
-static void smbus_eeprom_register_types(void)
-{
- type_register_static(&smbus_eeprom_info);
-}
-
-type_init(smbus_eeprom_register_types)
+DEFINE_TYPES(smbus_eeprom_types)
void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf)
{
diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events
index 6900e06..f708a7a 100644
--- a/hw/i2c/trace-events
+++ b/hw/i2c/trace-events
@@ -35,6 +35,11 @@
aspeed_i2c_bus_send(const char *mode, int i, int count, uint8_t byte) "%s send %d/%d 0x%02x"
aspeed_i2c_bus_recv(const char *mode, int i, int count, uint8_t byte) "%s recv %d/%d 0x%02x"
+# mpc_i2c.c
+
+mpc_i2c_read(uint64_t addr, uint32_t value) "[0x%" PRIx64 "] -> 0x%02" PRIx32
+mpc_i2c_write(uint64_t addr, uint32_t value) "[0x%" PRIx64 "] <- 0x%02" PRIx32
+
# npcm7xx_smbus.c
npcm7xx_smbus_read(const char *id, uint64_t offset, uint64_t value, unsigned size) "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c
index b86c382..bc360a9 100644
--- a/hw/i386/x86-common.c
+++ b/hw/i386/x86-common.c
@@ -273,12 +273,12 @@
if (ms->smp.modules > 1) {
env->nr_modules = ms->smp.modules;
- set_bit(CPU_TOPO_LEVEL_MODULE, env->avail_cpu_topo);
+ set_bit(CPU_TOPOLOGY_LEVEL_MODULE, env->avail_cpu_topo);
}
if (ms->smp.dies > 1) {
env->nr_dies = ms->smp.dies;
- set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo);
+ set_bit(CPU_TOPOLOGY_LEVEL_DIE, env->avail_cpu_topo);
}
/*
diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index b4183c5..61e47d8 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -90,7 +90,7 @@
object_property_set_int(OBJECT(cpu), "use-fpu", 1, &error_abort);
object_property_set_bool(OBJECT(cpu), "dcache-writeback", true,
&error_abort);
- object_property_set_bool(OBJECT(cpu), "endianness", true, &error_abort);
+ object_property_set_bool(OBJECT(cpu), "little-endian", true, &error_abort);
qdev_realize(DEVICE(cpu), NULL, &error_abort);
/* Attach emulated BRAM through the LMB. */
@@ -213,7 +213,12 @@
static void petalogix_ml605_machine_init(MachineClass *mc)
{
- mc->desc = "PetaLogix linux refdesign for xilinx ml605 little endian";
+#if TARGET_BIG_ENDIAN
+ mc->desc = "PetaLogix linux refdesign for xilinx ml605 (big endian)";
+ mc->deprecation_reason = "big endian support is not tested";
+#else
+ mc->desc = "PetaLogix linux refdesign for xilinx ml605 (little endian)";
+#endif
mc->init = petalogix_ml605_init;
}
diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
index dad46bd..6c0f5c6 100644
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
@@ -55,6 +55,9 @@
#define ETHLITE_IRQ 1
#define UARTLITE_IRQ 3
+#define TYPE_PETALOGIX_S3ADSP1800_MACHINE \
+ MACHINE_TYPE_NAME("petalogix-s3adsp1800")
+
static void
petalogix_s3adsp1800_init(MachineState *machine)
{
@@ -71,6 +74,8 @@
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort);
+ object_property_set_bool(OBJECT(cpu), "little-endian",
+ !TARGET_BIG_ENDIAN, &error_abort);
qdev_realize(DEVICE(cpu), NULL, &error_abort);
/* Attach emulated BRAM through the LMB. */
@@ -122,7 +127,7 @@
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
- create_unimplemented_device("gpio", GPIO_BASEADDR, 0x10000);
+ create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000);
microblaze_load_kernel(cpu, ddr_base, ram_size,
machine->initrd_filename,
@@ -130,11 +135,21 @@
NULL);
}
-static void petalogix_s3adsp1800_machine_init(MachineClass *mc)
+static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc, void *data)
{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800";
mc->init = petalogix_s3adsp1800_init;
mc->is_default = true;
}
-DEFINE_MACHINE("petalogix-s3adsp1800", petalogix_s3adsp1800_machine_init)
+static const TypeInfo petalogix_s3adsp1800_machine_types[] = {
+ {
+ .name = TYPE_PETALOGIX_S3ADSP1800_MACHINE,
+ .parent = TYPE_MACHINE,
+ .class_init = petalogix_s3adsp1800_machine_class_init,
+ },
+};
+
+DEFINE_TYPES(petalogix_s3adsp1800_machine_types)
diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c
index 1bfc964..567aad4 100644
--- a/hw/microblaze/xlnx-zynqmp-pmu.c
+++ b/hw/microblaze/xlnx-zynqmp-pmu.c
@@ -90,7 +90,7 @@
object_property_set_bool(OBJECT(&s->cpu), "use-pcmp-instr", true,
&error_abort);
object_property_set_bool(OBJECT(&s->cpu), "use-mmu", false, &error_abort);
- object_property_set_bool(OBJECT(&s->cpu), "endianness", true,
+ object_property_set_bool(OBJECT(&s->cpu), "little-endian", true,
&error_abort);
object_property_set_str(OBJECT(&s->cpu), "version", "8.40.b",
&error_abort);
@@ -181,9 +181,13 @@
static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc)
{
- mc->desc = "Xilinx ZynqMP PMU machine";
+#if TARGET_BIG_ENDIAN
+ mc->desc = "Xilinx ZynqMP PMU machine (big endian)";
+ mc->deprecation_reason = "big endian support is not tested";
+#else
+ mc->desc = "Xilinx ZynqMP PMU machine (little endian)";
+#endif
mc->init = xlnx_zynqmp_pmu_init;
}
DEFINE_MACHINE("xlnx-zynqmp-pmu", xlnx_zynqmp_pmu_machine_init)
-
diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c
index 3fdd16e..d8076e7 100644
--- a/hw/net/fsl_etsec/etsec.c
+++ b/hw/net/fsl_etsec/etsec.c
@@ -36,7 +36,6 @@
#include "registers.h"
#include "qapi/error.h"
#include "qemu/log.h"
-#include "qemu/module.h"
/* #define HEX_DUMP */
/* #define DEBUG_REGISTER */
@@ -431,17 +430,14 @@
dc->user_creatable = true;
}
-static const TypeInfo etsec_info = {
- .name = TYPE_ETSEC_COMMON,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(eTSEC),
- .class_init = etsec_class_init,
- .instance_init = etsec_instance_init,
+static const TypeInfo etsec_types[] = {
+ {
+ .name = TYPE_ETSEC_COMMON,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(eTSEC),
+ .class_init = etsec_class_init,
+ .instance_init = etsec_instance_init,
+ },
};
-static void etsec_register_types(void)
-{
- type_register_static(&etsec_info);
-}
-
-type_init(etsec_register_types)
+DEFINE_TYPES(etsec_types)
diff --git a/hw/net/fsl_etsec/miim.c b/hw/net/fsl_etsec/miim.c
index b48d2cb..4e91699 100644
--- a/hw/net/fsl_etsec/miim.c
+++ b/hw/net/fsl_etsec/miim.c
@@ -29,13 +29,6 @@
/* #define DEBUG_MIIM */
-#define MIIM_CONTROL 0
-#define MIIM_STATUS 1
-#define MIIM_PHY_ID_1 2
-#define MIIM_PHY_ID_2 3
-#define MIIM_T2_STATUS 10
-#define MIIM_EXT_STATUS 15
-
static void miim_read_cycle(eTSEC *etsec)
{
uint8_t phy;
@@ -47,14 +40,14 @@
addr = etsec->regs[MIIMADD].value & 0x1F;
switch (addr) {
- case MIIM_CONTROL:
+ case MII_BMCR:
value = etsec->phy_control;
break;
- case MIIM_STATUS:
+ case MII_BMSR:
value = etsec->phy_status;
break;
- case MIIM_T2_STATUS:
- value = 0x1800; /* Local and remote receivers OK */
+ case MII_STAT1000:
+ value = MII_STAT1000_LOK | MII_STAT1000_ROK;
break;
default:
value = 0x0;
@@ -84,8 +77,8 @@
#endif
switch (addr) {
- case MIIM_CONTROL:
- etsec->phy_control = value & ~(0x8100);
+ case MII_BMCR:
+ etsec->phy_control = value & ~(MII_BMCR_RESET | MII_BMCR_FD);
break;
default:
break;
diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c
index 95b983b..b706310 100644
--- a/hw/pci-host/ppce500.c
+++ b/hw/pci-host/ppce500.c
@@ -22,7 +22,6 @@
#include "hw/pci/pci_device.h"
#include "hw/pci/pci_host.h"
#include "qemu/bswap.h"
-#include "qemu/module.h"
#include "hw/pci-host/ppce500.h"
#include "qom/object.h"
@@ -475,7 +474,7 @@
address_space_init(&s->bm_as, &s->bm, "pci-bm");
pci_setup_iommu(b, &ppce500_iommu_ops, s);
- pci_create_simple(b, 0, "e500-host-bridge");
+ pci_create_simple(b, 0, TYPE_PPC_E500_PCI_BRIDGE);
memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE);
memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h,
@@ -508,17 +507,6 @@
dc->user_creatable = false;
}
-static const TypeInfo e500_host_bridge_info = {
- .name = TYPE_PPC_E500_PCI_BRIDGE,
- .parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(PPCE500PCIBridgeState),
- .class_init = e500_host_bridge_class_init,
- .interfaces = (InterfaceInfo[]) {
- { INTERFACE_CONVENTIONAL_PCI_DEVICE },
- { },
- },
-};
-
static Property pcihost_properties[] = {
DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11),
DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1),
@@ -535,17 +523,23 @@
dc->vmsd = &vmstate_ppce500_pci;
}
-static const TypeInfo e500_pcihost_info = {
- .name = TYPE_PPC_E500_PCI_HOST_BRIDGE,
- .parent = TYPE_PCI_HOST_BRIDGE,
- .instance_size = sizeof(PPCE500PCIState),
- .class_init = e500_pcihost_class_init,
+static const TypeInfo e500_pci_types[] = {
+ {
+ .name = TYPE_PPC_E500_PCI_BRIDGE,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(PPCE500PCIBridgeState),
+ .class_init = e500_host_bridge_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { },
+ },
+ },
+ {
+ .name = TYPE_PPC_E500_PCI_HOST_BRIDGE,
+ .parent = TYPE_PCI_HOST_BRIDGE,
+ .instance_size = sizeof(PPCE500PCIState),
+ .class_init = e500_pcihost_class_init,
+ },
};
-static void e500_pci_register_types(void)
-{
- type_register_static(&e500_pcihost_info);
- type_register_static(&e500_host_bridge_info);
-}
-
-type_init(e500_pci_register_types)
+DEFINE_TYPES(e500_pci_types)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 6433348..4626122 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -203,6 +203,8 @@
qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0);
qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2);
qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic);
+ qemu_fdt_setprop_cell(fdt, i2c, "#size-cells", 0);
+ qemu_fdt_setprop_cell(fdt, i2c, "#address-cells", 1);
qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c);
g_free(i2c);
@@ -829,7 +831,7 @@
}
static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
- IrqLines *irqs, Error **errp)
+ Error **errp)
{
#ifdef CONFIG_KVM
DeviceState *dev;
@@ -869,7 +871,7 @@
Error *err = NULL;
if (kvm_kernel_irqchip_allowed()) {
- dev = ppce500_init_mpic_kvm(pmc, irqs, &err);
+ dev = ppce500_init_mpic_kvm(pmc, &err);
}
if (kvm_kernel_irqchip_required() && !dev) {
error_reportf_err(err,
@@ -1021,7 +1023,7 @@
sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ));
memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET,
sysbus_mmio_get_region(s, 0));
- i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
+ i2c = I2C_BUS(qdev_get_child_bus(dev, "i2c"));
i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET);
/* eSDHC */
@@ -1070,7 +1072,7 @@
memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
sysbus_mmio_get_region(s, 0));
- pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
+ pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
if (!pci_bus)
printf("couldn't create PCI controller!\n");
diff --git a/hw/ppc/mpc8544_guts.c b/hw/ppc/mpc8544_guts.c
index e3540b0..e3c5145 100644
--- a/hw/ppc/mpc8544_guts.c
+++ b/hw/ppc/mpc8544_guts.c
@@ -18,7 +18,6 @@
*/
#include "qemu/osdep.h"
-#include "qemu/module.h"
#include "qemu/log.h"
#include "sysemu/runstate.h"
#include "cpu.h"
@@ -29,6 +28,12 @@
#define MPC8544_GUTS_RSTCR_RESET 0x02
#define MPC8544_GUTS_ADDR_PORPLLSR 0x00
+REG32(GUTS_PORPLLSR, 0x00)
+ FIELD(GUTS_PORPLLSR, E500_1_RATIO, 24, 6)
+ FIELD(GUTS_PORPLLSR, E500_0_RATIO, 16, 6)
+ FIELD(GUTS_PORPLLSR, DDR_RATIO, 9, 5)
+ FIELD(GUTS_PORPLLSR, PLAT_RATIO, 1, 5)
+
#define MPC8544_GUTS_ADDR_PORBMSR 0x04
#define MPC8544_GUTS_ADDR_PORIMPSCR 0x08
#define MPC8544_GUTS_ADDR_PORDEVSR 0x0C
@@ -75,6 +80,12 @@
addr &= MPC8544_GUTS_MMIO_SIZE - 1;
switch (addr) {
+ case MPC8544_GUTS_ADDR_PORPLLSR:
+ value = FIELD_DP32(value, GUTS_PORPLLSR, E500_1_RATIO, 6); /* 3:1 */
+ value = FIELD_DP32(value, GUTS_PORPLLSR, E500_0_RATIO, 6); /* 3:1 */
+ value = FIELD_DP32(value, GUTS_PORPLLSR, DDR_RATIO, 12); /* 12:1 */
+ value = FIELD_DP32(value, GUTS_PORPLLSR, PLAT_RATIO, 6); /* 6:1 */
+ break;
case MPC8544_GUTS_ADDR_PVR:
value = env->spr[SPR_PVR];
break;
@@ -129,16 +140,13 @@
sysbus_init_mmio(d, &s->iomem);
}
-static const TypeInfo mpc8544_guts_info = {
- .name = TYPE_MPC8544_GUTS,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(GutsState),
- .instance_init = mpc8544_guts_initfn,
+static const TypeInfo mpc8544_guts_types[] = {
+ {
+ .name = TYPE_MPC8544_GUTS,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(GutsState),
+ .instance_init = mpc8544_guts_initfn,
+ },
};
-static void mpc8544_guts_register_types(void)
-{
- type_register_static(&mpc8544_guts_info);
-}
-
-type_init(mpc8544_guts_register_types)
+DEFINE_TYPES(mpc8544_guts_types)
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index feb6505..12f01a7 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -183,8 +183,25 @@
}
}
-/* Portable implementation of pext_u64, bit-mask extraction. */
-static uint64_t _pext_u64(uint64_t val, uint64_t ext)
+/*
+ * Discards all bits from 'val' whose matching bits in the same
+ * positions in the mask 'ext' are zeros, and packs the remaining
+ * bits from 'val' contiguously at the least-significant end of the
+ * result, keeping the same bit order as 'val' and filling any
+ * other bits at the most-significant end of the result with zeros.
+ *
+ * For example, for the following 'val' and 'ext', the return 'ret'
+ * will be:
+ *
+ * val = a b c d e f g h
+ * ext = 1 0 1 0 0 1 1 0
+ * ret = 0 0 0 0 a c f g
+ *
+ * This function, taken from the riscv-iommu 1.0 spec, section 2.3.3
+ * "Process to translate addresses of MSIs", is similar to bit manip
+ * function PEXT (Parallel bits extract) from x86.
+ */
+static uint64_t riscv_iommu_pext_u64(uint64_t val, uint64_t ext)
{
uint64_t ret = 0;
uint64_t rot = 1;
@@ -528,7 +545,7 @@
int cause;
/* Interrupt File Number */
- intn = _pext_u64(PPN_DOWN(gpa), ctx->msi_addr_mask);
+ intn = riscv_iommu_pext_u64(PPN_DOWN(gpa), ctx->msi_addr_mask);
if (intn >= 256) {
/* Interrupt file number out of range */
res = MEMTX_ACCESS_ERROR;
diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c
index 929a92f..c993182 100644
--- a/hw/rtc/ds1338.c
+++ b/hw/rtc/ds1338.c
@@ -14,7 +14,6 @@
#include "hw/i2c/i2c.h"
#include "migration/vmstate.h"
#include "qemu/bcd.h"
-#include "qemu/module.h"
#include "qom/object.h"
#include "sysemu/rtc.h"
#include "trace.h"
@@ -233,16 +232,13 @@
dc->vmsd = &vmstate_ds1338;
}
-static const TypeInfo ds1338_info = {
- .name = TYPE_DS1338,
- .parent = TYPE_I2C_SLAVE,
- .instance_size = sizeof(DS1338State),
- .class_init = ds1338_class_init,
+static const TypeInfo ds1338_types[] = {
+ {
+ .name = TYPE_DS1338,
+ .parent = TYPE_I2C_SLAVE,
+ .instance_size = sizeof(DS1338State),
+ .class_init = ds1338_class_init,
+ },
};
-static void ds1338_register_types(void)
-{
- type_register_static(&ds1338_info);
-}
-
-type_init(ds1338_register_types)
+DEFINE_TYPES(ds1338_types)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index ed01499..dbe5c23 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -37,7 +37,6 @@
#include "migration/vmstate.h"
#include "sdhci-internal.h"
#include "qemu/log.h"
-#include "qemu/module.h"
#include "trace.h"
#include "qom/object.h"
@@ -1598,15 +1597,6 @@
sdhci_common_class_init(klass, data);
}
-static const TypeInfo sdhci_sysbus_info = {
- .name = TYPE_SYSBUS_SDHCI,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(SDHCIState),
- .instance_init = sdhci_sysbus_init,
- .instance_finalize = sdhci_sysbus_finalize,
- .class_init = sdhci_sysbus_class_init,
-};
-
/* --- qdev bus master --- */
static void sdhci_bus_class_init(ObjectClass *klass, void *data)
@@ -1617,13 +1607,6 @@
sbc->set_readonly = sdhci_set_readonly;
}
-static const TypeInfo sdhci_bus_info = {
- .name = TYPE_SDHCI_BUS,
- .parent = TYPE_SD_BUS,
- .instance_size = sizeof(SDBus),
- .class_init = sdhci_bus_class_init,
-};
-
/* --- qdev i.MX eSDHC --- */
#define USDHC_MIX_CTRL 0x48
@@ -1882,12 +1865,6 @@
s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ;
}
-static const TypeInfo imx_usdhc_info = {
- .name = TYPE_IMX_USDHC,
- .parent = TYPE_SYSBUS_SDHCI,
- .instance_init = imx_usdhc_init,
-};
-
/* --- qdev Samsung s3c --- */
#define S3C_SDHCI_CONTROL2 0x80
@@ -1946,18 +1923,31 @@
s->io_ops = &sdhci_s3c_mmio_ops;
}
-static const TypeInfo sdhci_s3c_info = {
- .name = TYPE_S3C_SDHCI ,
- .parent = TYPE_SYSBUS_SDHCI,
- .instance_init = sdhci_s3c_init,
+static const TypeInfo sdhci_types[] = {
+ {
+ .name = TYPE_SDHCI_BUS,
+ .parent = TYPE_SD_BUS,
+ .instance_size = sizeof(SDBus),
+ .class_init = sdhci_bus_class_init,
+ },
+ {
+ .name = TYPE_SYSBUS_SDHCI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(SDHCIState),
+ .instance_init = sdhci_sysbus_init,
+ .instance_finalize = sdhci_sysbus_finalize,
+ .class_init = sdhci_sysbus_class_init,
+ },
+ {
+ .name = TYPE_IMX_USDHC,
+ .parent = TYPE_SYSBUS_SDHCI,
+ .instance_init = imx_usdhc_init,
+ },
+ {
+ .name = TYPE_S3C_SDHCI,
+ .parent = TYPE_SYSBUS_SDHCI,
+ .instance_init = sdhci_s3c_init,
+ },
};
-static void sdhci_register_types(void)
-{
- type_register_static(&sdhci_sysbus_info);
- type_register_static(&sdhci_bus_info);
- type_register_static(&imx_usdhc_info);
- type_register_static(&sdhci_s3c_info);
-}
-
-type_init(sdhci_register_types)
+DEFINE_TYPES(sdhci_types)
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
index 2b1652f..eb7df93 100644
--- a/hw/usb/hcd-ehci-sysbus.c
+++ b/hw/usb/hcd-ehci-sysbus.c
@@ -19,7 +19,6 @@
#include "hw/qdev-properties.h"
#include "hw/usb/hcd-ehci.h"
#include "migration/vmstate.h"
-#include "qemu/module.h"
static const VMStateDescription vmstate_ehci_sysbus = {
.name = "ehci-sysbus",
@@ -97,17 +96,6 @@
set_bit(DEVICE_CATEGORY_USB, dc->categories);
}
-static const TypeInfo ehci_type_info = {
- .name = TYPE_SYS_BUS_EHCI,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(EHCISysBusState),
- .instance_init = ehci_sysbus_init,
- .instance_finalize = ehci_sysbus_finalize,
- .abstract = true,
- .class_init = ehci_sysbus_class_init,
- .class_size = sizeof(SysBusEHCIClass),
-};
-
static void ehci_platform_class_init(ObjectClass *oc, void *data)
{
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
@@ -118,12 +106,6 @@
set_bit(DEVICE_CATEGORY_USB, dc->categories);
}
-static const TypeInfo ehci_platform_type_info = {
- .name = TYPE_PLATFORM_EHCI,
- .parent = TYPE_SYS_BUS_EHCI,
- .class_init = ehci_platform_class_init,
-};
-
static void ehci_exynos4210_class_init(ObjectClass *oc, void *data)
{
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
@@ -134,12 +116,6 @@
set_bit(DEVICE_CATEGORY_USB, dc->categories);
}
-static const TypeInfo ehci_exynos4210_type_info = {
- .name = TYPE_EXYNOS4210_EHCI,
- .parent = TYPE_SYS_BUS_EHCI,
- .class_init = ehci_exynos4210_class_init,
-};
-
static void ehci_aw_h3_class_init(ObjectClass *oc, void *data)
{
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
@@ -150,12 +126,6 @@
set_bit(DEVICE_CATEGORY_USB, dc->categories);
}
-static const TypeInfo ehci_aw_h3_type_info = {
- .name = TYPE_AW_H3_EHCI,
- .parent = TYPE_SYS_BUS_EHCI,
- .class_init = ehci_aw_h3_class_init,
-};
-
static void ehci_npcm7xx_class_init(ObjectClass *oc, void *data)
{
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
@@ -168,12 +138,6 @@
set_bit(DEVICE_CATEGORY_USB, dc->categories);
}
-static const TypeInfo ehci_npcm7xx_type_info = {
- .name = TYPE_NPCM7XX_EHCI,
- .parent = TYPE_SYS_BUS_EHCI,
- .class_init = ehci_npcm7xx_class_init,
-};
-
static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
{
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
@@ -184,12 +148,6 @@
set_bit(DEVICE_CATEGORY_USB, dc->categories);
}
-static const TypeInfo ehci_tegra2_type_info = {
- .name = TYPE_TEGRA2_EHCI,
- .parent = TYPE_SYS_BUS_EHCI,
- .class_init = ehci_tegra2_class_init,
-};
-
static void ehci_ppc4xx_init(Object *o)
{
EHCISysBusState *s = SYS_BUS_EHCI(o);
@@ -207,13 +165,6 @@
set_bit(DEVICE_CATEGORY_USB, dc->categories);
}
-static const TypeInfo ehci_ppc4xx_type_info = {
- .name = TYPE_PPC4xx_EHCI,
- .parent = TYPE_SYS_BUS_EHCI,
- .class_init = ehci_ppc4xx_class_init,
- .instance_init = ehci_ppc4xx_init,
-};
-
/*
* Faraday FUSBH200 USB 2.0 EHCI
*/
@@ -282,24 +233,55 @@
set_bit(DEVICE_CATEGORY_USB, dc->categories);
}
-static const TypeInfo ehci_fusbh200_type_info = {
- .name = TYPE_FUSBH200_EHCI,
- .parent = TYPE_SYS_BUS_EHCI,
- .instance_size = sizeof(FUSBH200EHCIState),
- .instance_init = fusbh200_ehci_init,
- .class_init = fusbh200_ehci_class_init,
+static const TypeInfo ehci_sysbus_types[] = {
+ {
+ .name = TYPE_SYS_BUS_EHCI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(EHCISysBusState),
+ .instance_init = ehci_sysbus_init,
+ .instance_finalize = ehci_sysbus_finalize,
+ .abstract = true,
+ .class_init = ehci_sysbus_class_init,
+ .class_size = sizeof(SysBusEHCIClass),
+ },
+ {
+ .name = TYPE_PLATFORM_EHCI,
+ .parent = TYPE_SYS_BUS_EHCI,
+ .class_init = ehci_platform_class_init,
+ },
+ {
+ .name = TYPE_EXYNOS4210_EHCI,
+ .parent = TYPE_SYS_BUS_EHCI,
+ .class_init = ehci_exynos4210_class_init,
+ },
+ {
+ .name = TYPE_AW_H3_EHCI,
+ .parent = TYPE_SYS_BUS_EHCI,
+ .class_init = ehci_aw_h3_class_init,
+ },
+ {
+ .name = TYPE_NPCM7XX_EHCI,
+ .parent = TYPE_SYS_BUS_EHCI,
+ .class_init = ehci_npcm7xx_class_init,
+ },
+ {
+ .name = TYPE_TEGRA2_EHCI,
+ .parent = TYPE_SYS_BUS_EHCI,
+ .class_init = ehci_tegra2_class_init,
+ },
+ {
+ .name = TYPE_PPC4xx_EHCI,
+ .parent = TYPE_SYS_BUS_EHCI,
+ .class_init = ehci_ppc4xx_class_init,
+ .instance_init = ehci_ppc4xx_init,
+ },
+ {
+ .name = TYPE_FUSBH200_EHCI,
+ .parent = TYPE_SYS_BUS_EHCI,
+ .instance_size = sizeof(FUSBH200EHCIState),
+ .instance_init = fusbh200_ehci_init,
+ .class_init = fusbh200_ehci_class_init,
+ },
};
-static void ehci_sysbus_register_types(void)
-{
- type_register_static(&ehci_type_info);
- type_register_static(&ehci_platform_type_info);
- type_register_static(&ehci_exynos4210_type_info);
- type_register_static(&ehci_aw_h3_type_info);
- type_register_static(&ehci_npcm7xx_type_info);
- type_register_static(&ehci_tegra2_type_info);
- type_register_static(&ehci_ppc4xx_type_info);
- type_register_static(&ehci_fusbh200_type_info);
-}
-
-type_init(ehci_sysbus_register_types)
+DEFINE_TYPES(ehci_sysbus_types)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index a8f001f..36fbb9b 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -44,8 +44,16 @@
Error **errp);
void machine_parse_smp_config(MachineState *ms,
const SMPConfiguration *config, Error **errp);
+bool machine_parse_smp_cache(MachineState *ms,
+ const SmpCachePropertiesList *caches,
+ Error **errp);
unsigned int machine_topo_get_cores_per_socket(const MachineState *ms);
unsigned int machine_topo_get_threads_per_socket(const MachineState *ms);
+CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms,
+ CacheLevelAndType cache);
+void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache,
+ CpuTopologyLevel level);
+bool machine_check_smp_cache(const MachineState *ms, Error **errp);
void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t size);
/**
@@ -146,6 +154,8 @@
* @books_supported - whether books are supported by the machine
* @drawers_supported - whether drawers are supported by the machine
* @modules_supported - whether modules are supported by the machine
+ * @cache_supported - whether cache (l1d, l1i, l2 and l3) configuration are
+ * supported by the machine
*/
typedef struct {
bool prefer_sockets;
@@ -155,6 +165,7 @@
bool books_supported;
bool drawers_supported;
bool modules_supported;
+ bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX];
} SMPCompatProps;
/**
@@ -371,6 +382,10 @@
unsigned int max_cpus;
} CpuTopology;
+typedef struct SmpCache {
+ SmpCacheProperties props[CACHE_LEVEL_AND_TYPE__MAX];
+} SmpCache;
+
/**
* MachineState:
*/
@@ -421,6 +436,7 @@
AccelState *accelerator;
CPUArchIdList *possible_cpus;
CpuTopology smp;
+ SmpCache smp_cache;
struct NVDIMMState *nvdimms_state;
struct NumaState *numa_state;
};
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index dff49fc..b2c8bf2 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -39,7 +39,7 @@
* CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width().
*/
-
+#include "qapi/qapi-types-machine-common.h"
#include "qemu/bitops.h"
/*
@@ -62,21 +62,7 @@
unsigned threads_per_core;
} X86CPUTopoInfo;
-/*
- * CPUTopoLevel is the general i386 topology hierarchical representation,
- * ordered by increasing hierarchical relationship.
- * Its enumeration value is not bound to the type value of Intel (CPUID[0x1F])
- * or AMD (CPUID[0x80000026]).
- */
-enum CPUTopoLevel {
- CPU_TOPO_LEVEL_INVALID,
- CPU_TOPO_LEVEL_SMT,
- CPU_TOPO_LEVEL_CORE,
- CPU_TOPO_LEVEL_MODULE,
- CPU_TOPO_LEVEL_DIE,
- CPU_TOPO_LEVEL_PACKAGE,
- CPU_TOPO_LEVEL_MAX,
-};
+#define CPU_TOPOLOGY_LEVEL_INVALID CPU_TOPOLOGY_LEVEL__MAX
/* Return the bit width needed for 'count' IDs */
static unsigned apicid_bitwidth_for_count(unsigned count)
@@ -212,8 +198,8 @@
*/
static inline bool x86_has_extended_topo(unsigned long *topo_bitmap)
{
- return test_bit(CPU_TOPO_LEVEL_MODULE, topo_bitmap) ||
- test_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap);
+ return test_bit(CPU_TOPOLOGY_LEVEL_MODULE, topo_bitmap) ||
+ test_bit(CPU_TOPOLOGY_LEVEL_DIE, topo_bitmap);
}
#endif /* HW_I386_TOPOLOGY_H */
diff --git a/qapi/machine-common.json b/qapi/machine-common.json
index b64e489..298e51f 100644
--- a/qapi/machine-common.json
+++ b/qapi/machine-common.json
@@ -5,7 +5,7 @@
# See the COPYING file in the top-level directory.
##
-# = Machines S390 data types
+# = Common machine types
##
##
@@ -18,3 +18,95 @@
##
{ 'enum': 'S390CpuEntitlement',
'data': [ 'auto', 'low', 'medium', 'high' ] }
+
+##
+# @CpuTopologyLevel:
+#
+# An enumeration of CPU topology levels.
+#
+# @thread: thread level, which would also be called SMT level or
+# logical processor level. The @threads option in
+# SMPConfiguration is used to configure the topology of this
+# level.
+#
+# @core: core level. The @cores option in SMPConfiguration is used
+# to configure the topology of this level.
+#
+# @module: module level. The @modules option in SMPConfiguration is
+# used to configure the topology of this level.
+#
+# @cluster: cluster level. The @clusters option in SMPConfiguration
+# is used to configure the topology of this level.
+#
+# @die: die level. The @dies option in SMPConfiguration is used to
+# configure the topology of this level.
+#
+# @socket: socket level, which would also be called package level.
+# The @sockets option in SMPConfiguration is used to configure
+# the topology of this level.
+#
+# @book: book level. The @books option in SMPConfiguration is used
+# to configure the topology of this level.
+#
+# @drawer: drawer level. The @drawers option in SMPConfiguration is
+# used to configure the topology of this level.
+#
+# @default: default level. Some architectures will have default
+# topology settings (e.g., cache topology), and this special
+# level means following the architecture-specific settings.
+#
+# Since: 9.2
+##
+{ 'enum': 'CpuTopologyLevel',
+ 'data': [ 'thread', 'core', 'module', 'cluster', 'die',
+ 'socket', 'book', 'drawer', 'default' ] }
+
+##
+# @CacheLevelAndType:
+#
+# Caches a system may have. The enumeration value here is the
+# combination of cache level and cache type.
+#
+# @l1d: L1 data cache.
+#
+# @l1i: L1 instruction cache.
+#
+# @l2: L2 (unified) cache.
+#
+# @l3: L3 (unified) cache
+#
+# Since: 9.2
+##
+{ 'enum': 'CacheLevelAndType',
+ 'data': [ 'l1d', 'l1i', 'l2', 'l3' ] }
+
+##
+# @SmpCacheProperties:
+#
+# Cache information for SMP system.
+#
+# @cache: Cache name, which is the combination of cache level
+# and cache type.
+#
+# @topology: Cache topology level. It accepts the CPU topology
+# enumeration as the parameter, i.e., CPUs in the same
+# topology container share the same cache.
+#
+# Since: 9.2
+##
+{ 'struct': 'SmpCacheProperties',
+ 'data': {
+ 'cache': 'CacheLevelAndType',
+ 'topology': 'CpuTopologyLevel' } }
+
+##
+# @SmpCachePropertiesWrapper:
+#
+# List wrapper of SmpCacheProperties.
+#
+# @caches: the list of SmpCacheProperties.
+#
+# Since 9.2
+##
+{ 'struct': 'SmpCachePropertiesWrapper',
+ 'data': { 'caches': ['SmpCacheProperties'] } }
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3d2874c..58c96ea 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -238,23 +238,23 @@
0 /* Invalid value */)
static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info,
- enum CPUTopoLevel share_level)
+ enum CpuTopologyLevel share_level)
{
uint32_t num_ids = 0;
switch (share_level) {
- case CPU_TOPO_LEVEL_CORE:
+ case CPU_TOPOLOGY_LEVEL_CORE:
num_ids = 1 << apicid_core_offset(topo_info);
break;
- case CPU_TOPO_LEVEL_DIE:
+ case CPU_TOPOLOGY_LEVEL_DIE:
num_ids = 1 << apicid_die_offset(topo_info);
break;
- case CPU_TOPO_LEVEL_PACKAGE:
+ case CPU_TOPOLOGY_LEVEL_SOCKET:
num_ids = 1 << apicid_pkg_offset(topo_info);
break;
default:
/*
- * Currently there is no use case for SMT and MODULE, so use
+ * Currently there is no use case for THREAD and MODULE, so use
* assert directly to facilitate debugging.
*/
g_assert_not_reached();
@@ -303,19 +303,19 @@
}
static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info,
- enum CPUTopoLevel topo_level)
+ enum CpuTopologyLevel topo_level)
{
switch (topo_level) {
- case CPU_TOPO_LEVEL_SMT:
+ case CPU_TOPOLOGY_LEVEL_THREAD:
return 1;
- case CPU_TOPO_LEVEL_CORE:
+ case CPU_TOPOLOGY_LEVEL_CORE:
return topo_info->threads_per_core;
- case CPU_TOPO_LEVEL_MODULE:
+ case CPU_TOPOLOGY_LEVEL_MODULE:
return topo_info->threads_per_core * topo_info->cores_per_module;
- case CPU_TOPO_LEVEL_DIE:
+ case CPU_TOPOLOGY_LEVEL_DIE:
return topo_info->threads_per_core * topo_info->cores_per_module *
topo_info->modules_per_die;
- case CPU_TOPO_LEVEL_PACKAGE:
+ case CPU_TOPOLOGY_LEVEL_SOCKET:
return topo_info->threads_per_core * topo_info->cores_per_module *
topo_info->modules_per_die * topo_info->dies_per_pkg;
default:
@@ -325,18 +325,18 @@
}
static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info,
- enum CPUTopoLevel topo_level)
+ enum CpuTopologyLevel topo_level)
{
switch (topo_level) {
- case CPU_TOPO_LEVEL_SMT:
+ case CPU_TOPOLOGY_LEVEL_THREAD:
return 0;
- case CPU_TOPO_LEVEL_CORE:
+ case CPU_TOPOLOGY_LEVEL_CORE:
return apicid_core_offset(topo_info);
- case CPU_TOPO_LEVEL_MODULE:
+ case CPU_TOPOLOGY_LEVEL_MODULE:
return apicid_module_offset(topo_info);
- case CPU_TOPO_LEVEL_DIE:
+ case CPU_TOPOLOGY_LEVEL_DIE:
return apicid_die_offset(topo_info);
- case CPU_TOPO_LEVEL_PACKAGE:
+ case CPU_TOPOLOGY_LEVEL_SOCKET:
return apicid_pkg_offset(topo_info);
default:
g_assert_not_reached();
@@ -344,18 +344,18 @@
return 0;
}
-static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level)
+static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level)
{
switch (topo_level) {
- case CPU_TOPO_LEVEL_INVALID:
+ case CPU_TOPOLOGY_LEVEL_INVALID:
return CPUID_1F_ECX_TOPO_LEVEL_INVALID;
- case CPU_TOPO_LEVEL_SMT:
+ case CPU_TOPOLOGY_LEVEL_THREAD:
return CPUID_1F_ECX_TOPO_LEVEL_SMT;
- case CPU_TOPO_LEVEL_CORE:
+ case CPU_TOPOLOGY_LEVEL_CORE:
return CPUID_1F_ECX_TOPO_LEVEL_CORE;
- case CPU_TOPO_LEVEL_MODULE:
+ case CPU_TOPOLOGY_LEVEL_MODULE:
return CPUID_1F_ECX_TOPO_LEVEL_MODULE;
- case CPU_TOPO_LEVEL_DIE:
+ case CPU_TOPOLOGY_LEVEL_DIE:
return CPUID_1F_ECX_TOPO_LEVEL_DIE;
default:
/* Other types are not supported in QEMU. */
@@ -370,38 +370,41 @@
uint32_t *ecx, uint32_t *edx)
{
X86CPU *cpu = env_archcpu(env);
- unsigned long level, next_level;
+ unsigned long level, base_level, next_level;
uint32_t num_threads_next_level, offset_next_level;
- assert(count + 1 < CPU_TOPO_LEVEL_MAX);
+ assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET);
/*
* Find the No.(count + 1) topology level in avail_cpu_topo bitmap.
- * The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1).
+ * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD).
*/
- level = CPU_TOPO_LEVEL_INVALID;
+ level = CPU_TOPOLOGY_LEVEL_THREAD;
+ base_level = level;
for (int i = 0; i <= count; i++) {
level = find_next_bit(env->avail_cpu_topo,
- CPU_TOPO_LEVEL_PACKAGE,
- level + 1);
+ CPU_TOPOLOGY_LEVEL_SOCKET,
+ base_level);
/*
* CPUID[0x1f] doesn't explicitly encode the package level,
* and it just encodes the invalid level (all fields are 0)
* into the last subleaf of 0x1f.
*/
- if (level == CPU_TOPO_LEVEL_PACKAGE) {
- level = CPU_TOPO_LEVEL_INVALID;
+ if (level == CPU_TOPOLOGY_LEVEL_SOCKET) {
+ level = CPU_TOPOLOGY_LEVEL_INVALID;
break;
}
+ /* Search the next level. */
+ base_level = level + 1;
}
- if (level == CPU_TOPO_LEVEL_INVALID) {
+ if (level == CPU_TOPOLOGY_LEVEL_INVALID) {
num_threads_next_level = 0;
offset_next_level = 0;
} else {
next_level = find_next_bit(env->avail_cpu_topo,
- CPU_TOPO_LEVEL_PACKAGE,
+ CPU_TOPOLOGY_LEVEL_SOCKET,
level + 1);
num_threads_next_level = num_threads_by_topo_level(topo_info,
next_level);
@@ -577,7 +580,7 @@
.sets = 64,
.partitions = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
@@ -592,7 +595,7 @@
.partitions = 1,
.lines_per_tag = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/* L1 instruction cache: */
@@ -606,7 +609,7 @@
.sets = 64,
.partitions = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
@@ -621,7 +624,7 @@
.partitions = 1,
.lines_per_tag = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/* Level 2 unified cache: */
@@ -635,7 +638,7 @@
.sets = 4096,
.partitions = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
@@ -645,7 +648,7 @@
.size = 2 * MiB,
.line_size = 64,
.associativity = 8,
- .share_level = CPU_TOPO_LEVEL_INVALID,
+ .share_level = CPU_TOPOLOGY_LEVEL_INVALID,
};
@@ -659,7 +662,7 @@
.associativity = 16,
.sets = 512,
.partitions = 1,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/* Level 3 unified cache: */
@@ -675,7 +678,7 @@
.self_init = true,
.inclusive = true,
.complex_indexing = true,
- .share_level = CPU_TOPO_LEVEL_DIE,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
};
/* TLB definitions: */
@@ -2082,7 +2085,7 @@
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2095,7 +2098,7 @@
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2106,7 +2109,7 @@
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2120,7 +2123,7 @@
.self_init = true,
.inclusive = true,
.complex_indexing = true,
- .share_level = CPU_TOPO_LEVEL_DIE,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@@ -2136,7 +2139,7 @@
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2149,7 +2152,7 @@
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2160,7 +2163,7 @@
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2174,7 +2177,7 @@
.self_init = true,
.inclusive = true,
.complex_indexing = false,
- .share_level = CPU_TOPO_LEVEL_DIE,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@@ -2190,7 +2193,7 @@
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2203,7 +2206,7 @@
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2214,7 +2217,7 @@
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2228,7 +2231,7 @@
.self_init = true,
.inclusive = true,
.complex_indexing = true,
- .share_level = CPU_TOPO_LEVEL_DIE,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@@ -2244,7 +2247,7 @@
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2257,7 +2260,7 @@
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2268,7 +2271,7 @@
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2282,7 +2285,7 @@
.self_init = true,
.inclusive = true,
.complex_indexing = false,
- .share_level = CPU_TOPO_LEVEL_DIE,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@@ -2298,7 +2301,7 @@
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2311,7 +2314,7 @@
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2322,7 +2325,7 @@
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2336,7 +2339,7 @@
.self_init = true,
.inclusive = true,
.complex_indexing = true,
- .share_level = CPU_TOPO_LEVEL_DIE,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@@ -2352,7 +2355,7 @@
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2365,7 +2368,7 @@
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2376,7 +2379,7 @@
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2390,7 +2393,7 @@
.self_init = true,
.inclusive = true,
.complex_indexing = false,
- .share_level = CPU_TOPO_LEVEL_DIE,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@@ -2406,7 +2409,7 @@
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2419,7 +2422,7 @@
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2430,7 +2433,7 @@
.partitions = 1,
.sets = 2048,
.lines_per_tag = 1,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2444,7 +2447,7 @@
.self_init = true,
.inclusive = true,
.complex_indexing = false,
- .share_level = CPU_TOPO_LEVEL_DIE,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@@ -6588,7 +6591,7 @@
/* Share the cache at package level. */
*eax |= max_thread_ids_for_cache(&topo_info,
- CPU_TOPO_LEVEL_PACKAGE) << 14;
+ CPU_TOPOLOGY_LEVEL_SOCKET) << 14;
}
}
} else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
@@ -8170,10 +8173,10 @@
env->nr_modules = 1;
env->nr_dies = 1;
- /* SMT, core and package levels are set by default. */
- set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo);
- set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo);
- set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo);
+ /* thread, core and socket levels are set by default. */
+ set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo);
+ set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo);
+ set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo);
}
static void x86_cpu_initfn(Object *obj)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index c24d81b..b65eedb 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1716,7 +1716,7 @@
* Used to encode CPUID[4].EAX[bits 25:14] or
* CPUID[0x8000001D].EAX[bits 25:14].
*/
- enum CPUTopoLevel share_level;
+ CpuTopologyLevel share_level;
} CPUCacheInfo;
@@ -2051,7 +2051,7 @@
unsigned nr_modules;
/* Bitmap of available CPU topology levels for this CPU. */
- DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX);
+ DECLARE_BITMAP(avail_cpu_topo, CPU_TOPOLOGY_LEVEL__MAX);
} CPUX86State;
struct kvm_msrs;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 14286de..710eb11 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -332,9 +332,16 @@
qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1);
qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1);
#endif
+
+ /* Restricted 'endianness' property is equivalent of 'little-endian' */
+ object_property_add_alias(obj, "little-endian", obj, "endianness");
}
static Property mb_properties[] = {
+ /*
+ * Following properties are used by Xilinx DTS conversion tool
+ * do not rename them.
+ */
DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
false),
@@ -391,6 +398,9 @@
DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
+ /*
+ * End of properties reserved by Xilinx DTS conversion tool.
+ */
DEFINE_PROP_END_OF_LIST(),
};
