)]}'
{
  "commit": "61f93767751341e29445c052d4db53791aeab035",
  "tree": "fb8b152e5d1d3a06f5d3609d533cbce727a6e5f7",
  "parents": [
    "f2146bc6cb98e3e6d5749a6a974a53a1a1a754fc"
  ],
  "author": {
    "name": "Jamin Lin",
    "email": "jamin_lin@aspeedtech.com",
    "time": "Thu Jul 04 16:29:20 2024 +0800"
  },
  "committer": {
    "name": "Cédric Le Goater",
    "email": "clg@redhat.com",
    "time": "Tue Jul 09 08:05:44 2024 +0200"
  },
  "message": "hw/block: m25p80: support quad mode for w25q01jvq\n\nAccording to the w25q01jv datasheet at page 16,\nit is required to set QE bit in \"Status Register 2\".\nBesides, users are able to utilize \"Write Status Register 1(0x01)\"\ncommand to set QE bit in \"Status Register 2\" and\nutilize \"Read Status Register 2(0x35)\" command to get the QE bit status.\n\nTo support quad mode for w25q01jvq, update collecting data needed\n2 bytes for WRSR command in decode_new_cmd function and\nverify QE bit at the second byte of collecting data bit 2\nin complete_collecting_data.\n\nUpdate RDCR_EQIO command to set bit 2 of return data\nif quad mode enable in decode_new_cmd.\n\nSigned-off-by: Troy Lee \u003ctroy_lee@aspeedtech.com\u003e\nSigned-off-by: Jamin Lin \u003cjamin_lin@aspeedtech.com\u003e\nReviewed-by: Cédric Le Goater \u003cclg@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8dec134832a14b03d065080db49a029d0450acdd",
      "old_mode": 33188,
      "old_path": "hw/block/m25p80.c",
      "new_id": "9e99107b42e2255770394bc51a259c536640c441",
      "new_mode": 33188,
      "new_path": "hw/block/m25p80.c"
    }
  ]
}