)]}'
{
  "commit": "5fe2800b85fc44ffce749fb03c0ace085bd8a7b8",
  "tree": "cfa9c93b2a58703d3a5b6321236cc8b6d05cd449",
  "parents": [
    "cc2bf69a36e05e22a1dca9bf6305ef5e0cad993e"
  ],
  "author": {
    "name": "Daniel Henrique Barboza",
    "email": "dbarboza@ventanamicro.com",
    "time": "Mon Dec 18 09:53:14 2023 -0300"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Wed Jan 10 18:47:47 2024 +1000"
  },
  "message": "target/riscv/tcg: add \u0027zic64b\u0027 support\n\nzic64b is defined in the RVA22U64 profile [1] as a named feature for\n\"Cache blocks must be 64 bytes in size, naturally aligned in the address\nspace\". It\u0027s a fantasy name for 64 bytes cache blocks. The RVA22U64\nprofile mandates this feature, meaning that applications using this\nprofile expects 64 bytes cache blocks.\n\nTo make the upcoming RVA22U64 implementation complete, we\u0027ll zic64b as\na \u0027named feature\u0027, not a regular extension. This means that:\n\n- it won\u0027t be exposed to users;\n- it won\u0027t be written in riscv,isa.\n\nThis will be extended to other named extensions in the future, so we\u0027re\ncreating some common boilerplate for them as well.\n\nzic64b is default to \u0027true\u0027 since we\u0027re already using 64 bytes blocks.\nIf any cache block size (cbo{m,p,z}_blocksize) is changed to something\ndifferent than 64, zic64b is set to \u0027false\u0027.\n\nOur profile implementation will then be able to check the current state\nof zic64b and take the appropriate action (e.g. throw a warning).\n\n[1] https://github.com/riscv/riscv-profiles/releases/download/v1.0/profiles.pdf\n\nSigned-off-by: Daniel Henrique Barboza \u003cdbarboza@ventanamicro.com\u003e\nReviewed-by: Andrew Jones \u003cajones@ventanamicro.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nMessage-ID: \u003c20231218125334.37184-7-dbarboza@ventanamicro.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ce0a3ded042494b5ad67eae2c771d16bcbcff5b3",
      "old_mode": 33188,
      "old_path": "target/riscv/cpu.c",
      "new_id": "29fdd64298bf40837c586871a23e151ea5575f4f",
      "new_mode": 33188,
      "new_path": "target/riscv/cpu.c"
    },
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      "new_mode": 33188,
      "new_path": "target/riscv/cpu.h"
    },
    {
      "type": "modify",
      "old_id": "2da8ac958235407afa48c3d7474efdb53c090b25",
      "old_mode": 33188,
      "old_path": "target/riscv/cpu_cfg.h",
      "new_id": "350ea44e50ad8c18cdb59f4a6803fde70e7e9ec1",
      "new_mode": 33188,
      "new_path": "target/riscv/cpu_cfg.h"
    },
    {
      "type": "modify",
      "old_id": "e9f980805e4b03085dc7bd7d397433ab68d434af",
      "old_mode": 33188,
      "old_path": "target/riscv/tcg/tcg-cpu.c",
      "new_id": "f12e0620e5fb565815d9ad2453e53ea18ca2b99a",
      "new_mode": 33188,
      "new_path": "target/riscv/tcg/tcg-cpu.c"
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  ]
}