Merge tag 'misc-next-pull-request' of https://gitlab.com/berrange/qemu into staging
Miscellaneous fixes
* Switch canokey license from Apache to GPLv2+
* Fix uninitialized variable in LUKS driver
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# gpg: Signature made Tue 25 Jul 2023 09:24:51 AM PDT
# gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF
# gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full]
# gpg: aka "Daniel P. Berrange <berrange@redhat.com>" [full]
* tag 'misc-next-pull-request' of https://gitlab.com/berrange/qemu:
hw/usb/canokey: change license to GPLv2+
crypto: Always initialize splitkeylen
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/VERSION b/VERSION
index 46a6526..cbe9ed9 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-8.0.90
+8.0.91
diff --git a/host/include/aarch64/host/cpuinfo.h b/host/include/aarch64/host/cpuinfo.h
index 05feeb4..769626b 100644
--- a/host/include/aarch64/host/cpuinfo.h
+++ b/host/include/aarch64/host/cpuinfo.h
@@ -1,6 +1,6 @@
/*
* SPDX-License-Identifier: GPL-2.0-or-later
- * Host specific cpu indentification for AArch64.
+ * Host specific cpu identification for AArch64.
*/
#ifndef HOST_CPUINFO_H
diff --git a/host/include/generic/host/cpuinfo.h b/host/include/generic/host/cpuinfo.h
index eca6720..67ad410 100644
--- a/host/include/generic/host/cpuinfo.h
+++ b/host/include/generic/host/cpuinfo.h
@@ -1,4 +1,4 @@
/*
- * No host specific cpu indentification.
+ * No host specific cpu identification.
* SPDX-License-Identifier: GPL-2.0-or-later
*/
diff --git a/hw/9pfs/9p-local.c b/hw/9pfs/9p-local.c
index 9d07620..1b1f3b9 100644
--- a/hw/9pfs/9p-local.c
+++ b/hw/9pfs/9p-local.c
@@ -624,7 +624,7 @@
/*
* Initiate a writeback. This is not a data integrity sync.
* We want to ensure that we don't leave dirty pages in the cache
- * after write when writeout=immediate is sepcified.
+ * after write when writeout=immediate is specified.
*/
sync_file_range(fs->fd, offset, ret,
SYNC_FILE_RANGE_WAIT_BEFORE | SYNC_FILE_RANGE_WRITE);
@@ -843,7 +843,7 @@
}
credp->fc_mode = credp->fc_mode | S_IFREG;
if (fs_ctx->export_flags & V9FS_SM_MAPPED) {
- /* Set cleint credentials in xattr */
+ /* Set client credentials in xattr */
err = local_set_xattrat(dirfd, name, credp);
} else {
err = local_set_mapped_file_attrat(dirfd, name, credp);
@@ -912,7 +912,7 @@
if (write_size != oldpath_size) {
goto err_end;
}
- /* Set cleint credentials in symlink's xattr */
+ /* Set client credentials in symlink's xattr */
credp->fc_mode = credp->fc_mode | S_IFLNK;
if (fs_ctx->export_flags & V9FS_SM_MAPPED) {
@@ -1418,7 +1418,7 @@
struct statfs stbuf;
/*
- * use ioc_getversion only if the ioctl is definied
+ * use ioc_getversion only if the ioctl is defined
*/
if (fstatfs(data->mountfd, &stbuf) < 0) {
error_setg_errno(errp, errno,
diff --git a/hw/9pfs/9p-proxy.c b/hw/9pfs/9p-proxy.c
index 905cae6..7aac49a 100644
--- a/hw/9pfs/9p-proxy.c
+++ b/hw/9pfs/9p-proxy.c
@@ -767,7 +767,7 @@
/*
* Initiate a writeback. This is not a data integrity sync.
* We want to ensure that we don't leave dirty pages in the cache
- * after write when writeout=immediate is sepcified.
+ * after write when writeout=immediate is specified.
*/
sync_file_range(fs->fd, offset, ret,
SYNC_FILE_RANGE_WAIT_BEFORE | SYNC_FILE_RANGE_WRITE);
diff --git a/hw/9pfs/9p-synth.c b/hw/9pfs/9p-synth.c
index f62c40b..0ac79a5 100644
--- a/hw/9pfs/9p-synth.c
+++ b/hw/9pfs/9p-synth.c
@@ -493,7 +493,7 @@
node = dir_node;
goto out;
}
- /* search for the name in the childern */
+ /* search for the name in the children */
rcu_read_lock();
QLIST_FOREACH(node, &dir_node->child, sibling) {
if (!strcmp(node->name, name)) {
diff --git a/hw/9pfs/9p-util.h b/hw/9pfs/9p-util.h
index df1b583..51c94b0 100644
--- a/hw/9pfs/9p-util.h
+++ b/hw/9pfs/9p-util.h
@@ -48,7 +48,7 @@
/*
* Converts given device number from host's device number format to Linux
* device number format. As both the size of type dev_t and encoding of
- * dev_t is system dependant, we have to convert them for Linux guests if
+ * dev_t is system dependent, we have to convert them for Linux guests if
* host is not running Linux.
*/
static inline uint64_t host_dev_to_dotl_dev(dev_t dev)
diff --git a/hw/9pfs/9p.c b/hw/9pfs/9p.c
index 991645a..323f042 100644
--- a/hw/9pfs/9p.c
+++ b/hw/9pfs/9p.c
@@ -644,7 +644,7 @@
}
/*
- * Parameter k for the Exponential Golomb algorihm to be used.
+ * Parameter k for the Exponential Golomb algorithm to be used.
*
* The smaller this value, the smaller the minimum bit count for the Exp.
* Golomb generated affixes will be (at lowest index) however for the
@@ -1039,7 +1039,7 @@
* Sending a reply would confuse clients because they would
* assume that any EINTR is the actual result of the operation,
* rather than a consequence of the cancellation. However, if
- * the operation completed (succesfully or with an error other
+ * the operation completed (successfully or with an error other
* than caused be cancellation), we do send out that reply, both
* for efficiency and to avoid confusing the rest of the state machine
* that assumes passing a non-error here will mean a successful
diff --git a/hw/9pfs/9p.h b/hw/9pfs/9p.h
index 1b0d805..a6f59ab 100644
--- a/hw/9pfs/9p.h
+++ b/hw/9pfs/9p.h
@@ -304,7 +304,7 @@
AffixType_t type; /* Whether this affix is a suffix or a prefix. */
uint64_t value; /* Actual numerical value of this affix. */
/*
- * Lenght of the affix, that is how many (of the lowest) bits of ``value``
+ * Length of the affix, that is how many (of the lowest) bits of ``value``
* must be used for appending/prepending this affix to its final resulting,
* unique number.
*/
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 6880998..263626a 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1565,7 +1565,7 @@
{
AspeedSoCState *soc = &bmc->soc;
- /* U10 24C08 connects to SDA/SCL Groupt 1 by default */
+ /* U10 24C08 connects to SDA/SCL Group 1 by default */
uint8_t *eeprom_buf = g_malloc0(32 * 1024);
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 07aecd9..5873107 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -1205,7 +1205,7 @@
{
/*
* The MPS2 TZ FPGA images have IDAUs in them which are connected to
- * the Master Security Controllers. Thes have the same logic as
+ * the Master Security Controllers. These have the same logic as
* is used by the IoTKit for the IDAU connected to the CPU, except
* that MSCs don't care about the NSC attribute.
*/
diff --git a/hw/char/escc.c b/hw/char/escc.c
index 4f3872b..4be6605 100644
--- a/hw/char/escc.c
+++ b/hw/char/escc.c
@@ -653,7 +653,9 @@
escc_update_irq(s);
s->tx = val;
if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { /* tx enabled */
- if (qemu_chr_fe_backend_connected(&s->chr)) {
+ if (s->wregs[W_MISC2] & MISC2_LCL_LOOP) {
+ serial_receive_byte(s, s->tx);
+ } else if (qemu_chr_fe_backend_connected(&s->chr)) {
/*
* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 7a34bc0..074cf50 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -239,7 +239,7 @@
}
/* Return true if this LR should trigger an EOI maintenance interrupt, i.e. the
- * corrsponding bit in EISR is set.
+ * corresponding bit in EISR is set.
*/
static inline bool gic_lr_entry_is_eoi(uint32_t entry)
{
@@ -1333,7 +1333,7 @@
/* ??? This currently clears the pending bit for all CPUs, even
for per-CPU interrupts. It's unclear whether this is the
- corect behavior. */
+ correct behavior. */
if (value & (1 << i)) {
GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
}
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 297f7f0..8153525 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -494,7 +494,7 @@
/* Only the ProcessorSleep bit is writable. When the guest sets
* it, it requests that we transition the channel between the
* redistributor and the cpu interface to quiescent, and that
- * we set the ChildrenAsleep bit once the inteface has reached the
+ * we set the ChildrenAsleep bit once the interface has reached the
* quiescent state.
* Setting the ProcessorSleep to 0 reverses the quiescing, and
* ChildrenAsleep is cleared once the transition is complete.
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 63afe1f..03b6b8c 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -894,7 +894,7 @@
vec->active = 0;
if (vec->level) {
/* Re-pend the exception if it's still held high; only
- * happens for extenal IRQs
+ * happens for external IRQs
*/
assert(irq >= NVIC_FIRST_IRQ);
vec->pending = 1;
diff --git a/hw/intc/s390_flic_kvm.c b/hw/intc/s390_flic_kvm.c
index 4e86d2d..28364b2 100644
--- a/hw/intc/s390_flic_kvm.c
+++ b/hw/intc/s390_flic_kvm.c
@@ -380,7 +380,7 @@
* @size: ignored
*
* Note: Pass buf and len to kernel. Start with one page and
- * increase until buffer is sufficient or maxium size is
+ * increase until buffer is sufficient or maximum size is
* reached
*/
static int kvm_flic_save(QEMUFile *f, void *opaque, size_t size,
diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c
index ce8ee50..5d244b3 100644
--- a/hw/m68k/next-cube.c
+++ b/hw/m68k/next-cube.c
@@ -734,7 +734,7 @@
M68kCPU *cpu = s->cpu;
int shift = 0;
- /* first switch sets interupt status */
+ /* first switch sets interrupt status */
/* DPRINTF("IRQ %i\n",number); */
switch (number) {
/* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */
diff --git a/hw/m68k/next-kbd.c b/hw/m68k/next-kbd.c
index 0544160..0c348c1 100644
--- a/hw/m68k/next-kbd.c
+++ b/hw/m68k/next-kbd.c
@@ -37,7 +37,7 @@
OBJECT_DECLARE_SIMPLE_TYPE(NextKBDState, NEXTKBD)
-/* following defintions from next68k netbsd */
+/* following definitions from next68k netbsd */
#define CSR_INT 0x00800000
#define CSR_DATA 0x00400000
diff --git a/hw/m68k/virt.c b/hw/m68k/virt.c
index 731205b..de91726 100644
--- a/hw/m68k/virt.c
+++ b/hw/m68k/virt.c
@@ -1,7 +1,7 @@
/*
* SPDX-License-Identifier: GPL-2.0-or-later
*
- * QEMU Vitual M68K Machine
+ * QEMU Virtual M68K Machine
*
* (c) 2020 Laurent Vivier <laurent@vivier.eu>
*
diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index a24fadd..babb053 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -104,7 +104,7 @@
dinfo = drive_get(IF_PFLASH, 0, 0);
/* 5th parameter 2 means bank-width
- * 10th paremeter 0 means little-endian */
+ * 10th parameter 0 means little-endian */
pflash_cfi01_register(FLASH_BASEADDR, "petalogix_ml605.flash", FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
64 * KiB, 2, 0x89, 0x18, 0x0000, 0x0, 0);
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
index 4018b8c..3ad0a22 100644
--- a/hw/mips/loongson3_virt.c
+++ b/hw/mips/loongson3_virt.c
@@ -447,7 +447,7 @@
pci_vga_init(pci_bus);
- if (defaults_enabled()) {
+ if (defaults_enabled() && object_class_by_name("pci-ohci")) {
pci_create_simple(pci_bus, -1, "pci-ohci");
usb_create_simple(usb_bus_find(-1), "usb-kbd");
usb_create_simple(usb_bus_find(-1), "usb-tablet");
diff --git a/hw/misc/allwinner-r40-dramc.c b/hw/misc/allwinner-r40-dramc.c
index ea61247..6944f84 100644
--- a/hw/misc/allwinner-r40-dramc.c
+++ b/hw/misc/allwinner-r40-dramc.c
@@ -368,7 +368,7 @@
/*
* mctl_r40_detect_rank_count in u-boot will write the high 1G of DDR
- * to detect wether the board support dual_rank or not. Create a virtual memory
+ * to detect whether the board support dual_rank or not. Create a virtual memory
* if the board's ram_size less or equal than 1G, and set read time out flag of
* REG_DRAMCTL_PGSR when the user touch this high dram.
*/
diff --git a/hw/misc/exynos4210_rng.c b/hw/misc/exynos4210_rng.c
index 1b9e834..9214ec1 100644
--- a/hw/misc/exynos4210_rng.c
+++ b/hw/misc/exynos4210_rng.c
@@ -1,5 +1,5 @@
/*
- * Exynos4210 Pseudo Random Nubmer Generator Emulation
+ * Exynos4210 Pseudo Random Number Generator Emulation
*
* Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
*
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 784c02a..b8d22e2 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -1183,9 +1183,14 @@
PCI_SLOT(devfn), PCI_FUNC(devfn), name,
bus->devices[devfn]->name, bus->devices[devfn]->qdev.id);
return NULL;
- } else if (dev->hotplugged &&
- !pci_is_vf(pci_dev) &&
- pci_get_function_0(pci_dev)) {
+ } /*
+ * Populating function 0 triggers a scan from the guest that
+ * exposes other non-zero functions. Hence we need to ensure that
+ * function 0 wasn't added yet.
+ */
+ else if (dev->hotplugged &&
+ !pci_is_vf(pci_dev) &&
+ pci_get_function_0(pci_dev)) {
error_setg(errp, "PCI: slot %d function 0 already occupied by %s,"
" new func %s cannot be exposed to guest.",
PCI_SLOT(pci_get_function_0(pci_dev)->devfn),
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 6811f0f..362c2c8 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1382,6 +1382,8 @@
s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
+
+ s->io_ops = &sdhci_mmio_le_ops;
}
void sdhci_uninitfn(SDHCIState *s)
@@ -1399,9 +1401,13 @@
switch (s->endianness) {
case DEVICE_LITTLE_ENDIAN:
- s->io_ops = &sdhci_mmio_le_ops;
+ /* s->io_ops is little endian by default */
break;
case DEVICE_BIG_ENDIAN:
+ if (s->io_ops != &sdhci_mmio_le_ops) {
+ error_setg(errp, "SD controller doesn't support big endianness");
+ return;
+ }
s->io_ops = &sdhci_mmio_be_ops;
break;
default:
diff --git a/hw/sparc/sun4m_iommu.c b/hw/sparc/sun4m_iommu.c
index 71f5465..eb40f93 100644
--- a/hw/sparc/sun4m_iommu.c
+++ b/hw/sparc/sun4m_iommu.c
@@ -96,10 +96,10 @@
#define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */
#define IOMMU_AER_MASK 0x801f000f
-#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
-#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
-#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
-#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
+#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configuration per-slot */
+#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configuration per-slot */
+#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configuration per-slot */
+#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configuration per-slot */
#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
bypass enabled */
#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index 54ea2f0..fcce642 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -165,7 +165,7 @@
* Some versions of the reference manual claim that UART2 is @
* 0x30870000, but experiments with HW + DT files in upstream
* Linux kernel show that not to be true and that block is
- * acutally located @ 0x30890000
+ * actually located @ 0x30890000
*/
FSL_IMX7_UART2_ADDR = 0x30890000,
FSL_IMX7_UART3_ADDR = 0x30880000,
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index 1ca262f..6b4ae56 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -74,7 +74,7 @@
*/
bool vectpending_is_s_banked;
int exception_prio; /* group prio of the highest prio active exception */
- int vectpending_prio; /* group prio of the exeception in vectpending */
+ int vectpending_prio; /* group prio of the exception in vectpending */
MemoryRegion sysregmem;
diff --git a/include/hw/s390x/s390-pci-bus.h b/include/hw/s390x/s390-pci-bus.h
index e0a9f93..b1bdbea 100644
--- a/include/hw/s390x/s390-pci-bus.h
+++ b/include/hw/s390x/s390-pci-bus.h
@@ -184,7 +184,7 @@
* The following states make up the "configured" meta-state:
* disabled: device is configured but not enabled; transition between this
* state and enabled via clp enable/disable
- * enbaled: device is ready for use; transition to disabled via clp disable;
+ * enabled: device is ready for use; transition to disabled via clp disable;
* may enter an error state
* blocked: ignore all DMA and interrupts; transition back to enabled or from
* error state via mpcifc
diff --git a/include/hw/s390x/sclp.h b/include/hw/s390x/sclp.h
index d3ade40..cf1f2ef 100644
--- a/include/hw/s390x/sclp.h
+++ b/include/hw/s390x/sclp.h
@@ -87,7 +87,7 @@
* - we work on a private copy of the SCCB, since there are several length
* fields, that would cause a security nightmare if we allow the guest to
* alter the structure while we parse it. We cannot use ldl_p and friends
- * either without doing pointer arithmetics
+ * either without doing pointer arithmetic
* So we have to double check that all users of sclp data structures use the
* right endianness wrappers.
*/
diff --git a/migration/migration-stats.c b/migration/migration-stats.c
index f98c826..095d6d7 100644
--- a/migration/migration-stats.c
+++ b/migration/migration-stats.c
@@ -48,7 +48,7 @@
void migration_rate_set(uint64_t limit)
{
/*
- * 'limit' is per second. But we check it each BUFER_DELAY miliseconds.
+ * 'limit' is per second. But we check it each BUFFER_DELAY milliseconds.
*/
stat64_set(&mig_stats.rate_limit_max, limit / XFER_LIMIT_RATIO);
}
diff --git a/migration/migration.h b/migration/migration.h
index b7c8b67..6eea18d 100644
--- a/migration/migration.h
+++ b/migration/migration.h
@@ -134,7 +134,7 @@
/*
* Always set by the main vm load thread only, but can be read by the
* postcopy preempt thread. "volatile" makes sure all reads will be
- * uptodate across cores.
+ * up-to-date across cores.
*/
volatile PreemptThreadStatus preempt_thread_status;
/*
@@ -409,7 +409,7 @@
* channel itself.
*
* - postcopy preempt channel will be created at the switching phase
- * from precopy -> postcopy (to avoid race condtion of misordered
+ * from precopy -> postcopy (to avoid race condition of misordered
* creation of channels).
*
* NOTE: See message-id <ZBoShWArKDPpX/D7@work-vm> on qemu-devel
diff --git a/migration/multifd-zlib.c b/migration/multifd-zlib.c
index 8170125..37ce486 100644
--- a/migration/multifd-zlib.c
+++ b/migration/multifd-zlib.c
@@ -57,7 +57,7 @@
err_msg = "deflate init failed";
goto err_free_z;
}
- /* This is the maxium size of the compressed buffer */
+ /* This is the maximum size of the compressed buffer */
z->zbuff_len = compressBound(MULTIFD_PACKET_SIZE);
z->zbuff = g_try_malloc(z->zbuff_len);
if (!z->zbuff) {
diff --git a/migration/multifd-zstd.c b/migration/multifd-zstd.c
index d1d29e7..b471daa 100644
--- a/migration/multifd-zstd.c
+++ b/migration/multifd-zstd.c
@@ -68,7 +68,7 @@
p->id, ZSTD_getErrorName(res));
return -1;
}
- /* This is the maxium size of the compressed buffer */
+ /* This is the maximum size of the compressed buffer */
z->zbuff_len = ZSTD_compressBound(MULTIFD_PACKET_SIZE);
z->zbuff = g_try_malloc(z->zbuff_len);
if (!z->zbuff) {
diff --git a/migration/multifd.c b/migration/multifd.c
index 3387d82..0e3ae87 100644
--- a/migration/multifd.c
+++ b/migration/multifd.c
@@ -878,7 +878,7 @@
qemu_sem_post(&p->sem_sync);
/*
* Although multifd_send_thread is not created, but main migration
- * thread neet to judge whether it is running, so we need to mark
+ * thread need to judge whether it is running, so we need to mark
* its status.
*/
p->quit = true;
diff --git a/migration/savevm.c b/migration/savevm.c
index 95c2abf4..51e40e3 100644
--- a/migration/savevm.c
+++ b/migration/savevm.c
@@ -117,7 +117,7 @@
* The format of arguments is depending on postcopy mode:
* - postcopy RAM only
* uint64_t host page size
- * uint64_t taget page size
+ * uint64_t target page size
*
* - postcopy RAM and postcopy dirty bitmaps
* format is the same as for postcopy RAM only
diff --git a/migration/trace-events b/migration/trace-events
index 5259c10..4e43fe2 100644
--- a/migration/trace-events
+++ b/migration/trace-events
@@ -184,7 +184,7 @@
source_return_path_thread_resume_ack(uint32_t v) "%"PRIu32
source_return_path_thread_switchover_acked(void) ""
migration_thread_low_pending(uint64_t pending) "%" PRIu64
-migrate_transferred(uint64_t tranferred, uint64_t time_spent, uint64_t bandwidth, uint64_t size) "transferred %" PRIu64 " time_spent %" PRIu64 " bandwidth %" PRIu64 " max_size %" PRId64
+migrate_transferred(uint64_t transferred, uint64_t time_spent, uint64_t bandwidth, uint64_t size) "transferred %" PRIu64 " time_spent %" PRIu64 " bandwidth %" PRIu64 " max_size %" PRId64
process_incoming_migration_co_end(int ret, int ps) "ret=%d postcopy-state=%d"
process_incoming_migration_co_postcopy_end_main(void) ""
postcopy_preempt_enabled(bool value) "%d"
diff --git a/qapi/char.json b/qapi/char.json
index e413ac2..52aaff2 100644
--- a/qapi/char.json
+++ b/qapi/char.json
@@ -18,7 +18,7 @@
# @filename: the filename of the character device
#
# @frontend-open: shows whether the frontend device attached to this
-# backend (eg. with the chardev=... option) is in open or closed
+# backend (e.g. with the chardev=... option) is in open or closed
# state (since 2.1)
#
# Notes: @filename is encoded using the QEMU command line character
diff --git a/qapi/misc.json b/qapi/misc.json
index ff070ec..cda2eff 100644
--- a/qapi/misc.json
+++ b/qapi/misc.json
@@ -18,7 +18,7 @@
# fail and the FD will be closed.
#
# @protocol: protocol name. Valid names are "vnc", "spice",
-# "@dbus-display" or the name of a character device (eg. from
+# "@dbus-display" or the name of a character device (e.g. from
# -chardev id=XXXX)
#
# @fdname: file descriptor name previously passed via 'getfd' command
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index fcd20bf..1330666 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -191,7 +191,7 @@
That said, we're only emulating Unix PALcode, and not attempting VMS,
so we don't need to implement Executive and Supervisor. QEMU's own
- PALcode cheats and usees the KSEG mapping for its code+data rather than
+ PALcode cheats and uses the KSEG mapping for its code+data rather than
physical addresses. */
#define MMU_KERNEL_IDX 0
@@ -362,7 +362,7 @@
The Unix PALcode only uses bit 4. */
#define PS_USER_MODE 8u
-/* CPUAlphaState->flags constants. These are layed out so that we
+/* CPUAlphaState->flags constants. These are laid out so that we
can set or reset the pieces individually by assigning to the byte,
or manipulated as a whole. */
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 1f7dd07..846f3d8 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2893,7 +2893,7 @@
the first fp insn of the TB. Alternately we could define a proper
default for every TB (e.g. QUAL_RM_N or QUAL_RM_D) and make sure
to reset the FP_STATUS to that default at the end of any TB that
- changes the default. We could even (gasp) dynamiclly figure out
+ changes the default. We could even (gasp) dynamically figure out
what default would be most efficient given the running program. */
ctx->tb_rm = -1;
/* Similarly for flush-to-zero. */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 69e2bde..93c28d5 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -677,7 +677,7 @@
}
/*
- * The PSTATE bits only mask the interrupt if we have not overriden the
+ * The PSTATE bits only mask the interrupt if we have not overridden the
* ability above.
*/
return unmasked || pstate_unmasked;
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 4d6c0f9..88e5acc 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2592,7 +2592,7 @@
return aa64;
}
-/* Function for determing whether guest cp register reads and writes should
+/* Function for determining whether guest cp register reads and writes should
* access the secure or non-secure bank of a cp register. When EL3 is
* operating in AArch32 state, the NS-bit determines whether the secure
* instance of a cp register should be used. When EL3 is AArch64 (or if
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 6012e4e..9615809 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -95,7 +95,7 @@
if (kvm_enabled()) {
/*
- * For KVM we have to automatically enable all supported unitialized
+ * For KVM we have to automatically enable all supported uninitialized
* lengths, even when the smaller lengths are not all powers-of-two.
*/
vq_map |= vq_supported & ~vq_init & vq_mask;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8e836aa..50f61e4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1674,7 +1674,7 @@
* pmevtyper_rawwrite is called between a pair of pmu_op_start and
* pmu_op_finish calls when loading saved state for a migration. Because
* we're potentially updating the type of event here, the value written to
- * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
+ * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a
* different counter type. Therefore, we need to set this value to the
* current count for the counter type we're writing so that pmu_op_finish
* has the correct count for its calculation.
@@ -7009,7 +7009,7 @@
/*
* QEMU does not have a way to invalidate by physical address, thus
* invalidating a range of physical addresses is accomplished by
- * flushing all tlb entries in the outer sharable domain,
+ * flushing all tlb entries in the outer shareable domain,
* just like PAALLOS.
*/
{ .name = "TLBI_RPALOS", .state = ARM_CP_STATE_AA64,
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
index 9cef70e..0045c18 100644
--- a/target/arm/tcg/m_helper.c
+++ b/target/arm/tcg/m_helper.c
@@ -148,7 +148,7 @@
* R: 0 because unpriv and A flag not set
* SRVALID: 0 because NS
* MRVALID: 0 because unpriv and A flag not set
- * SREGION: 0 becaus SRVALID is 0
+ * SREGION: 0 because SRVALID is 0
* MREGION: 0 because MRVALID is 0
*/
return 0;
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 7d0c8f7..ef0c474 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -182,7 +182,7 @@
* + for EL2 and EL3 there is only one TBI bit, and if it is set
* then the address is zero-extended, clearing bits [63:56]
* + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
- * and TBI1 controls addressses with bit 55 == 1.
+ * and TBI1 controls addresses with bit 55 == 1.
* If the appropriate TBI bit is set for the address then
* the address is sign-extended from bit 55 into bits [63:56]
*
@@ -2313,7 +2313,7 @@
if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
/*
- * A write to any coprocessor regiser that ends a TB
+ * A write to any coprocessor register that ends a TB
* must rebuild the hflags for the next TB.
*/
gen_rebuild_hflags(s);
diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c
index bbc7b3f..17d8e68 100644
--- a/target/arm/tcg/translate-mve.c
+++ b/target/arm/tcg/translate-mve.c
@@ -2182,7 +2182,7 @@
* execution if it is not in an IT block. For us this means
* only that if PSR.ECI says we should not be executing the beat
* corresponding to the lane of the vector register being accessed
- * then we should skip perfoming the move, and that we need to do
+ * then we should skip performing the move, and that we need to do
* the usual check for bad ECI state and advance of ECI state.
* (If PSR.ECI is non-zero then we cannot be in an IT block.)
*/
@@ -2225,7 +2225,7 @@
* execution if it is not in an IT block. For us this means
* only that if PSR.ECI says we should not be executing the beat
* corresponding to the lane of the vector register being accessed
- * then we should skip perfoming the move, and that we need to do
+ * then we should skip performing the move, and that we need to do
* the usual check for bad ECI state and advance of ECI state.
* (If PSR.ECI is non-zero then we cannot be in an IT block.)
*/
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 8350a65..2ba5efa 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -1841,7 +1841,7 @@
/* Perform an inline saturating addition of a 32-bit value within
* a 64-bit register. The second operand is known to be positive,
- * which halves the comparisions we must perform to bound the result.
+ * which halves the comparisons we must perform to bound the result.
*/
static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
{
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
index 359b1e3..d3e89fd 100644
--- a/target/arm/tcg/translate-vfp.c
+++ b/target/arm/tcg/translate-vfp.c
@@ -144,7 +144,7 @@
* Generate code for M-profile FP context handling: update the
* ownership of the FP context, and create a new context if
* necessary. This corresponds to the parts of the pseudocode
- * ExecuteFPCheck() after the inital PreserveFPState() call.
+ * ExecuteFPCheck() after the initial PreserveFPState() call.
*/
static void gen_update_fp_context(DisasContext *s)
{
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index f59d3b2..6712a2c 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2626,7 +2626,7 @@
* Process the entire segment at once, writing back the
* results only after we've consumed all of the inputs.
*
- * Key to indicies by column:
+ * Key to indices by column:
* i j i k j k
*/
sum00 = a[s + H4(0 + 0)];
diff --git a/target/cris/helper.c b/target/cris/helper.c
index 81a7269..c0bf987 100644
--- a/target/cris/helper.c
+++ b/target/cris/helper.c
@@ -113,7 +113,7 @@
assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
switch (cs->exception_index) {
case EXCP_BREAK:
- /* These exceptions are genereated by the core itself.
+ /* These exceptions are generated by the core itself.
ERP should point to the insn following the brk. */
ex_vec = env->trap_vector;
env->pregs[PRV10_BRP] = env->pc;
@@ -169,7 +169,7 @@
switch (cs->exception_index) {
case EXCP_BREAK:
- /* These exceptions are genereated by the core itself.
+ /* These exceptions are generated by the core itself.
ERP should point to the insn following the brk. */
ex_vec = env->trap_vector;
env->pregs[PR_ERP] = env->pc;
@@ -228,7 +228,7 @@
undefined. */
env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
- /* Clear the excption_index to avoid spurios hw_aborts for recursive
+ /* Clear the excption_index to avoid spurious hw_aborts for recursive
bus faults. */
cs->exception_index = -1;
diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c
index d55a18a..40cb74c 100644
--- a/target/cris/op_helper.c
+++ b/target/cris/op_helper.c
@@ -231,7 +231,7 @@
{
unsigned int x, z, mask;
- /* Extended arithmetics, leave the z flag alone. */
+ /* Extended arithmetic, leave the z flag alone. */
x = env->cc_x;
mask = env->cc_mask | X_FLAG;
if (x) {
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 1445cd8..0b3d724 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -342,7 +342,7 @@
tcg_gen_add_tl(d, d, t);
}
-/* Extended arithmetics on CRIS. */
+/* Extended arithmetic on CRIS. */
static inline void t_gen_add_flag(TCGv d, int flag)
{
TCGv c;
@@ -646,7 +646,7 @@
switch (op) {
case CC_OP_ADD:
tcg_gen_add_tl(dst, a, b);
- /* Extended arithmetics. */
+ /* Extended arithmetic. */
t_gen_addx_carry(dc, dst);
break;
case CC_OP_ADDC:
@@ -659,7 +659,7 @@
break;
case CC_OP_SUB:
tcg_gen_sub_tl(dst, a, b);
- /* Extended arithmetics. */
+ /* Extended arithmetic. */
t_gen_subx_carry(dc, dst);
break;
case CC_OP_MOVE:
@@ -685,7 +685,7 @@
break;
case CC_OP_NEG:
tcg_gen_neg_tl(dst, b);
- /* Extended arithmetics. */
+ /* Extended arithmetic. */
t_gen_subx_carry(dc, dst);
break;
case CC_OP_LZ:
@@ -708,7 +708,7 @@
break;
case CC_OP_CMP:
tcg_gen_sub_tl(dst, a, b);
- /* Extended arithmetics. */
+ /* Extended arithmetic. */
t_gen_subx_carry(dc, dst);
break;
default:
@@ -2924,12 +2924,12 @@
* On QEMU care needs to be taken when a branch+delayslot sequence is broken
* and the branch and delayslot don't share pages.
*
- * The TB contaning the branch insn will set up env->btarget and evaluate
+ * The TB containing the branch insn will set up env->btarget and evaluate
* env->btaken. When the translation loop exits we will note that the branch
* sequence is broken and let env->dslot be the size of the branch insn (those
* vary in length).
*
- * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
+ * The TB containing the delayslot will have the PC of its real insn (i.e no lsb
* set). It will also expect to have env->dslot setup with the size of the
* delay slot so that env->pc - env->dslot point to the branch insn. This TB
* will execute the dslot and take the branch, either to btarget or just one
@@ -3143,7 +3143,7 @@
tcg_gen_lookup_and_goto_ptr();
break;
case DISAS_UPDATE:
- /* Indicate that interupts must be re-evaluated before the next TB. */
+ /* Indicate that interrupts must be re-evaluated before the next TB. */
tcg_gen_exit_tb(NULL, 0);
break;
default:
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 7373177..9fe79b1 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -35,7 +35,7 @@
#define MMU_PHYS_IDX 4
#define TARGET_INSN_START_EXTRA_WORDS 1
-/* Hardware exceptions, interupts, faults, and traps. */
+/* Hardware exceptions, interrupts, faults, and traps. */
#define EXCP_HPMC 1 /* high priority machine check */
#define EXCP_POWER_FAIL 2
#define EXCP_RC 3 /* recovery counter */
@@ -276,7 +276,7 @@
/* TB lookup assumes that PC contains the complete virtual address.
If we leave space+offset separate, we'll get ITLB misses to an
incomplete virtual address. This also means that we must separate
- out current cpu priviledge from the low bits of IAOQ_F. */
+ out current cpu privilege from the low bits of IAOQ_F. */
#ifdef CONFIG_USER_ONLY
*pc = env->iaoq_f & -4;
*cs_base = env->iaoq_b & -4;
diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c
index d2480b1..bebc732 100644
--- a/target/hppa/int_helper.c
+++ b/target/hppa/int_helper.c
@@ -37,7 +37,7 @@
/* Each CPU has a word mapped into the GSC bus. Anything on the GSC bus
* can write to this word to raise an external interrupt on the target CPU.
- * This includes the system controler (DINO) for regular devices, or
+ * This includes the system controller (DINO) for regular devices, or
* another CPU for SMP interprocessor interrupts.
*/
static uint64_t io_eir_read(void *opaque, hwaddr addr, unsigned size)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index d33813d..d66fcb3 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1964,7 +1964,7 @@
{
/* If by some means we get here with PSW[N]=1, that implies that
the B,GATE instruction would be skipped, and we'd fault on the
- next insn within the privilaged page. */
+ next insn within the privileged page. */
switch (ctx->null_cond.c) {
case TCG_COND_NEVER:
break;
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index 4c8ce7f..f8f2403 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -10,7 +10,7 @@
#include "hw/registerfields.h"
-/* Base on kernal definitions: arch/loongarch/include/asm/loongarch.h */
+/* Based on kernel definitions: arch/loongarch/include/asm/loongarch.h */
/* Basic CSRs */
#define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 01c18a7..0a1544c 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -590,10 +590,10 @@
#define DUMP_CACHEFLAGS(a) \
switch (a & M68K_DESC_CACHEMODE) { \
- case M68K_DESC_CM_WRTHRU: /* cachable, write-through */ \
+ case M68K_DESC_CM_WRTHRU: /* cacheable, write-through */ \
qemu_printf("T"); \
break; \
- case M68K_DESC_CM_COPYBK: /* cachable, copyback */ \
+ case M68K_DESC_CM_COPYBK: /* cacheable, copyback */ \
qemu_printf("C"); \
break; \
case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index a7b040a..f6cab6c 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -205,7 +205,7 @@
#define PVR10_TARGET_FAMILY_MASK 0xFF000000
#define PVR10_ASIZE_SHIFT 18
-/* MMU descrtiption */
+/* MMU description */
#define PVR11_USE_MMU 0xC0000000
#define PVR11_MMU_ITLB_SIZE 0x38000000
#define PVR11_MMU_DTLB_SIZE 0x07000000
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index deb8060..e662acd 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -609,7 +609,7 @@
static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
static TCGv mxu_CR;
-static const char mxuregnames[][4] = {
+static const char mxuregnames[NUMBER_OF_MXU_REGISTERS][4] = {
"XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8",
"XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "XCR",
};
@@ -644,6 +644,16 @@
}
}
+static inline void gen_extract_mxu_gpr(TCGv t, unsigned int reg,
+ unsigned int ofs, unsigned int len)
+{
+ if (reg == 0) {
+ tcg_gen_movi_tl(t, 0);
+ } else if (reg <= 15) {
+ tcg_gen_extract_tl(t, mxu_gpr[reg - 1], ofs, len);
+ }
+}
+
/* MXU control register moves. */
static inline void gen_load_mxu_cr(TCGv t)
{
@@ -2434,8 +2444,12 @@
tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
} else {
/* the most general case */
- tcg_gen_setcond_tl(TCG_COND_LT, mxu_gpr[XRa - 1],
- mxu_gpr[XRb - 1], mxu_gpr[XRc - 1]);
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+
+ gen_load_mxu_gpr(t0, XRb);
+ gen_load_mxu_gpr(t1, XRc);
+ tcg_gen_setcond_tl(TCG_COND_LT, mxu_gpr[XRa - 1], t0, t1);
}
}
@@ -3000,10 +3014,10 @@
TCGv t5 = tcg_temp_new();
if (XRa != 0) {
- tcg_gen_extract_tl(t0, mxu_gpr[XRb - 1], 16, 8);
- tcg_gen_extract_tl(t1, mxu_gpr[XRc - 1], 16, 8);
- tcg_gen_extract_tl(t2, mxu_gpr[XRb - 1], 24, 8);
- tcg_gen_extract_tl(t3, mxu_gpr[XRc - 1], 24, 8);
+ gen_extract_mxu_gpr(t0, XRb, 16, 8);
+ gen_extract_mxu_gpr(t1, XRc, 16, 8);
+ gen_extract_mxu_gpr(t2, XRb, 24, 8);
+ gen_extract_mxu_gpr(t3, XRc, 24, 8);
if (aptn2 & 2) {
tcg_gen_sub_tl(t0, t0, t1);
tcg_gen_sub_tl(t2, t2, t3);
@@ -3023,10 +3037,10 @@
tcg_gen_or_tl(t4, t2, t0);
}
if (XRd != 0) {
- tcg_gen_extract_tl(t0, mxu_gpr[XRb - 1], 0, 8);
- tcg_gen_extract_tl(t1, mxu_gpr[XRc - 1], 0, 8);
- tcg_gen_extract_tl(t2, mxu_gpr[XRb - 1], 8, 8);
- tcg_gen_extract_tl(t3, mxu_gpr[XRc - 1], 8, 8);
+ gen_extract_mxu_gpr(t0, XRb, 0, 8);
+ gen_extract_mxu_gpr(t1, XRc, 0, 8);
+ gen_extract_mxu_gpr(t2, XRb, 8, 8);
+ gen_extract_mxu_gpr(t3, XRc, 8, 8);
if (aptn2 & 1) {
tcg_gen_sub_tl(t0, t0, t1);
tcg_gen_sub_tl(t2, t2, t3);
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
index e5e1e9d..7dbc2e2 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -623,18 +623,13 @@
static int walk_directory(CPUMIPSState *env, uint64_t *vaddr,
int directory_index, bool *huge_page, bool *hgpg_directory_hit,
- uint64_t *pw_entrylo0, uint64_t *pw_entrylo1)
+ uint64_t *pw_entrylo0, uint64_t *pw_entrylo1,
+ unsigned directory_shift, unsigned leaf_shift)
{
int dph = (env->CP0_PWCtl >> CP0PC_DPH) & 0x1;
int psn = (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F;
int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
- int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
- int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
- int directory_shift = (ptew > 1) ? -1 :
- (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
- int leaf_shift = (ptew > 1) ? -1 :
- (ptew == 1) ? native_shift + 1 : native_shift;
uint32_t direntry_size = 1 << (directory_shift + 3);
uint32_t leafentry_size = 1 << (leaf_shift + 3);
uint64_t entry;
@@ -735,21 +730,11 @@
/* Other HTW configs */
int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
-
- /* HTW Shift values (depend on entry size) */
- int directory_shift = (ptew > 1) ? -1 :
- (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
- int leaf_shift = (ptew > 1) ? -1 :
- (ptew == 1) ? native_shift + 1 : native_shift;
+ unsigned directory_shift, leaf_shift;
/* Offsets into tables */
- int goffset = gindex << directory_shift;
- int uoffset = uindex << directory_shift;
- int moffset = mindex << directory_shift;
- int ptoffset0 = (ptindex >> 1) << (leaf_shift + 1);
- int ptoffset1 = ptoffset0 | (1 << (leaf_shift));
-
- uint32_t leafentry_size = 1 << (leaf_shift + 3);
+ unsigned goffset, uoffset, moffset, ptoffset0, ptoffset1;
+ uint32_t leafentry_size;
/* Starting address - Page Table Base */
uint64_t vaddr = env->CP0_PWBase;
@@ -771,15 +756,28 @@
/* no structure to walk */
return false;
}
- if ((directory_shift == -1) || (leaf_shift == -1)) {
+ if (ptew > 1) {
return false;
}
+ /* HTW Shift values (depend on entry size) */
+ directory_shift = (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
+ leaf_shift = (ptew == 1) ? native_shift + 1 : native_shift;
+
+ goffset = gindex << directory_shift;
+ uoffset = uindex << directory_shift;
+ moffset = mindex << directory_shift;
+ ptoffset0 = (ptindex >> 1) << (leaf_shift + 1);
+ ptoffset1 = ptoffset0 | (1 << (leaf_shift));
+
+ leafentry_size = 1 << (leaf_shift + 3);
+
/* Global Directory */
if (gdw > 0) {
vaddr |= goffset;
switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhit,
- &pw_entrylo0, &pw_entrylo1))
+ &pw_entrylo0, &pw_entrylo1,
+ directory_shift, leaf_shift))
{
case 0:
return false;
@@ -795,7 +793,8 @@
if (udw > 0) {
vaddr |= uoffset;
switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhit,
- &pw_entrylo0, &pw_entrylo1))
+ &pw_entrylo0, &pw_entrylo1,
+ directory_shift, leaf_shift))
{
case 0:
return false;
@@ -811,7 +810,8 @@
if (mdw > 0) {
vaddr |= moffset;
switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhit,
- &pw_entrylo0, &pw_entrylo1))
+ &pw_entrylo0, &pw_entrylo1,
+ directory_shift, leaf_shift))
{
case 0:
return false;
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 92c38f5..ce4d605 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -290,7 +290,7 @@
int is_counting;
uint32_t picmr; /* Interrupt mask register */
- uint32_t picsr; /* Interrupt contrl register*/
+ uint32_t picsr; /* Interrupt control register */
#endif
} CPUOpenRISCState;
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 7760329..a86360d 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -273,7 +273,7 @@
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_ov, srcb, 0);
/* The result of divide-by-zero is undefined.
- Supress the host-side exception by dividing by 1. */
+ Suppress the host-side exception by dividing by 1. */
tcg_gen_or_tl(t0, srcb, cpu_sr_ov);
tcg_gen_div_tl(dest, srca, t0);
@@ -287,7 +287,7 @@
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_cy, srcb, 0);
/* The result of divide-by-zero is undefined.
- Supress the host-side exception by dividing by 1. */
+ Suppress the host-side exception by dividing by 1. */
tcg_gen_or_tl(t0, srcb, cpu_sr_cy);
tcg_gen_divu_tl(dest, srca, t0);
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 08cabbd..f552a03 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -2066,7 +2066,7 @@
tcg_gen_movi_i32(cpu_psw_o, val << 31);
break;
default:
- qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb);
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid destination %d", cb);
break;
}
} else if (is_privileged(ctx, 0)) {
@@ -2084,7 +2084,7 @@
}
break;
default:
- qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb);
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid destination %d", cb);
break;
}
}
diff --git a/target/s390x/cpu_features.c b/target/s390x/cpu_features.c
index ebb155c..d28eb65 100644
--- a/target/s390x/cpu_features.c
+++ b/target/s390x/cpu_features.c
@@ -249,7 +249,7 @@
{
int i;
- /* init all bitmaps from gnerated data initially */
+ /* init all bitmaps from generated data initially */
for (i = 0; i < ARRAY_SIZE(s390_feature_groups); i++) {
s390_init_feat_bitmap(s390_feature_groups[i].init,
s390_feature_groups[i].feat);
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index 42b52af..91ce896 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@ -975,7 +975,7 @@
init_ignored_base_feat();
- /* init all bitmaps from gnerated data initially */
+ /* init all bitmaps from generated data initially */
s390_init_feat_bitmap(qemu_max_init, qemu_max_cpu_feat);
for (i = 0; i < ARRAY_SIZE(s390_cpu_defs); i++) {
s390_init_feat_bitmap(s390_cpu_defs[i].base_init,
diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c
index 3d941ed..c329b31 100644
--- a/target/s390x/tcg/fpu_helper.c
+++ b/target/s390x/tcg/fpu_helper.c
@@ -87,7 +87,7 @@
/*
* FIXME:
- * 1. Right now, all inexact conditions are inidicated as
+ * 1. Right now, all inexact conditions are indicated as
* "truncated" (0) and never as "incremented" (1) in the DXC.
* 2. Only traps due to invalid/divbyzero are suppressing. Other traps
* are completing, meaning the target register has to be written!
diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc
index 86a509b..0bfd88d 100644
--- a/target/s390x/tcg/insn-data.h.inc
+++ b/target/s390x/tcg/insn-data.h.inc
@@ -529,7 +529,7 @@
/* LOAD LOGICAL HALFWORD RELATIVE LONG */
C(0xc402, LLHRL, RIL_b, GIE, 0, ri2, new, r1_32, ld16u, 0)
C(0xc406, LLGHRL, RIL_b, GIE, 0, ri2, r1, 0, ld16u, 0)
-/* LOAD LOGICAL IMMEDATE */
+/* LOAD LOGICAL IMMEDIATE */
D(0xc00e, LLIHF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 32)
D(0xc00f, LLILF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 0)
D(0xa50c, LLIHH, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 48)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 84d76f1..dc7041e 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -429,7 +429,7 @@
static void gen_program_exception(DisasContext *s, int code)
{
- /* Remember what pgm exeption this was. */
+ /* Remember what pgm exception this was. */
tcg_gen_st_i32(tcg_constant_i32(code), cpu_env,
offsetof(CPUS390XState, int_pgm_code));
diff --git a/target/sparc/asi.h b/target/sparc/asi.h
index bb58735..3270ed0 100644
--- a/target/sparc/asi.h
+++ b/target/sparc/asi.h
@@ -144,13 +144,13 @@
* ASIs, "(4V)" designates SUN4V specific ASIs. "(NG4)" designates SPARC-T4
* and later ASIs.
*/
-#define ASI_REAL 0x14 /* Real address, cachable */
+#define ASI_REAL 0x14 /* Real address, cacheable */
#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */
#define ASI_REAL_IO 0x15 /* Real address, non-cachable */
#define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */
#define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */
#define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */
-#define ASI_REAL_L 0x1c /* Real address, cachable, LE */
+#define ASI_REAL_L 0x1c /* Real address, cacheable, LE */
#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/
#define ASI_REAL_IO_L 0x1d /* Real address, non-cachable, LE */
#define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */
@@ -163,15 +163,15 @@
#define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load,
* secondary, user
*/
-#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cachable, qword load */
+#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cacheable, qword load */
#define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */
-#define ASI_TWINX_REAL 0x26 /* twin load, real, cachable */
+#define ASI_TWINX_REAL 0x26 /* twin load, real, cacheable */
#define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */
#define ASI_TWINX_N 0x27 /* twin load, nucleus */
#define ASI_TWINX_AIUP_L 0x2a /* twin load, primary user, LE */
#define ASI_TWINX_AIUS_L 0x2b /* twin load, secondary user, LE */
-#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, l-endian */
-#define ASI_TWINX_REAL_L 0x2e /* twin load, real, cachable, LE */
+#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cacheable, qword load, l-endian */
+#define ASI_TWINX_REAL_L 0x2e /* twin load, real, cacheable, LE */
#define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */
#define ASI_TWINX_NL 0x2f /* twin load, nucleus, LE */
#define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */
@@ -231,7 +231,7 @@
#define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */
#define ASI_CORE_ID 0x63 /* (CMT) LP ID register */
#define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */
-#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */
+#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */
#define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */
#define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */
#define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index e329a7a..130ab8f 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -673,8 +673,8 @@
"cleanwin: %d cwp: %d\n",
env->cansave, env->canrestore, env->otherwin, env->wstate,
env->cleanwin, env->nwindows - 1 - env->cwp);
- qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: "
- TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs);
+ qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: %016x\n",
+ env->fsr, env->y, env->fprs);
#else
qemu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 95d2d0d..9804457 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -521,7 +521,7 @@
uint64_t igregs[8]; /* interrupt general registers */
uint64_t mgregs[8]; /* mmu general registers */
uint64_t glregs[8 * MAXTL_MAX];
- uint64_t fprs;
+ uint32_t fprs;
uint64_t tick_cmpr, stick_cmpr;
CPUTimer *tick, *stick;
#define TICK_NPT_MASK 0x8000000000000000ULL
diff --git a/target/sparc/machine.c b/target/sparc/machine.c
index 44b9e7d..274e121 100644
--- a/target/sparc/machine.c
+++ b/target/sparc/machine.c
@@ -168,7 +168,8 @@
VMSTATE_UINT64_ARRAY(env.bgregs, SPARCCPU, 8),
VMSTATE_UINT64_ARRAY(env.igregs, SPARCCPU, 8),
VMSTATE_UINT64_ARRAY(env.mgregs, SPARCCPU, 8),
- VMSTATE_UINT64(env.fprs, SPARCCPU),
+ VMSTATE_UNUSED(4), /* was unused high half of uint64_t fprs */
+ VMSTATE_UINT32(env.fprs, SPARCCPU),
VMSTATE_UINT64(env.tick_cmpr, SPARCCPU),
VMSTATE_UINT64(env.stick_cmpr, SPARCCPU),
VMSTATE_CPU_TIMER(env.tick, SPARCCPU),
diff --git a/target/sparc/monitor.c b/target/sparc/monitor.c
index 3184136..73f15aa 100644
--- a/target/sparc/monitor.c
+++ b/target/sparc/monitor.c
@@ -154,7 +154,7 @@
{ "otherwin", offsetof(CPUSPARCState, otherwin) },
{ "wstate", offsetof(CPUSPARCState, wstate) },
{ "cleanwin", offsetof(CPUSPARCState, cleanwin) },
- { "fprs", offsetof(CPUSPARCState, fprs) },
+ { "fprs", offsetof(CPUSPARCState, fprs), NULL, MD_I32 },
#endif
{ NULL },
};
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index f15169b..133a9ac 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -104,18 +104,18 @@
}
/* Some features automatically imply others */
- if (tricore_feature(env, TRICORE_FEATURE_162)) {
+ if (tricore_has_feature(env, TRICORE_FEATURE_162)) {
set_feature(env, TRICORE_FEATURE_161);
}
- if (tricore_feature(env, TRICORE_FEATURE_161)) {
+ if (tricore_has_feature(env, TRICORE_FEATURE_161)) {
set_feature(env, TRICORE_FEATURE_16);
}
- if (tricore_feature(env, TRICORE_FEATURE_16)) {
+ if (tricore_has_feature(env, TRICORE_FEATURE_16)) {
set_feature(env, TRICORE_FEATURE_131);
}
- if (tricore_feature(env, TRICORE_FEATURE_131)) {
+ if (tricore_has_feature(env, TRICORE_FEATURE_131)) {
set_feature(env, TRICORE_FEATURE_13);
}
cpu_reset(cs);
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index a50b91c..3708405 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -277,7 +277,7 @@
TRICORE_FEATURE_162,
};
-static inline int tricore_feature(CPUTriCoreState *env, int feature)
+static inline int tricore_has_feature(CPUTriCoreState *env, int feature)
{
return (env->features & (1ULL << feature)) != 0;
}
diff --git a/target/tricore/csfr.h.inc b/target/tricore/csfr.h.inc
index ff004cb..cdfaf1d 100644
--- a/target/tricore/csfr.h.inc
+++ b/target/tricore/csfr.h.inc
@@ -1,4 +1,4 @@
-/* A(ll) access permited
+/* A(ll) access permitted
R(ead only) access
E(nd init protected) access
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index 951024d..6d076ac 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -57,7 +57,7 @@
return phys_addr;
}
-/* TODO: Add exeption support*/
+/* TODO: Add exception support */
static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address,
int rw, int tlb_error)
{
@@ -155,7 +155,7 @@
#define FIELD_GETTER_WITH_FEATURE(NAME, REG, FIELD, FEATURE) \
uint32_t NAME(CPUTriCoreState *env) \
{ \
- if (tricore_feature(env, TRICORE_FEATURE_##FEATURE)) { \
+ if (tricore_has_feature(env, TRICORE_FEATURE_##FEATURE)) { \
return FIELD_EX32(env->REG, REG, FIELD ## _ ## FEATURE); \
} \
return FIELD_EX32(env->REG, REG, FIELD ## _13); \
@@ -170,7 +170,7 @@
#define FIELD_SETTER_WITH_FEATURE(NAME, REG, FIELD, FEATURE) \
void NAME(CPUTriCoreState *env, uint32_t val) \
{ \
- if (tricore_feature(env, TRICORE_FEATURE_##FEATURE)) { \
+ if (tricore_has_feature(env, TRICORE_FEATURE_##FEATURE)) { \
env->REG = FIELD_DP32(env->REG, REG, FIELD ## _ ## FEATURE, val); \
} \
env->REG = FIELD_DP32(env->REG, REG, FIELD ## _13, val); \
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 821a4b6..89be1ed 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2584,7 +2584,7 @@
/* PCXI = new_PCXI; */
env->PCXI = new_PCXI;
- if (tricore_feature(env, TRICORE_FEATURE_131)) {
+ if (tricore_has_feature(env, TRICORE_FEATURE_131)) {
/* PSW = {new_PSW[31:26], PSW[25:24], new_PSW[23:0]}; */
psw_write(env, (new_PSW & ~(0x3000000)) + (psw & (0x3000000)));
} else { /* TRICORE_FEATURE_13 only */
@@ -2695,7 +2695,7 @@
env->gpr_a[10] = cpu_ldl_data(env, env->DCX+8);
env->gpr_a[11] = cpu_ldl_data(env, env->DCX+12);
- if (tricore_feature(env, TRICORE_FEATURE_131)) {
+ if (tricore_has_feature(env, TRICORE_FEATURE_131)) {
env->DBGTCR = 0;
}
}
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 2f32463..1947733 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -128,7 +128,7 @@
* Functions to generate micro-ops
*/
-/* Makros for generating helpers */
+/* Macros for generating helpers */
#define gen_helper_1arg(name, arg) do { \
TCGv_i32 helper_tmp = tcg_constant_i32(arg); \
@@ -336,8 +336,8 @@
/* We generate loads and store to core special function register (csfr) through
the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
- makros R, A and E, which allow read-only, all and endinit protected access.
- These makros also specify in which ISA version the csfr was introduced. */
+ macros R, A and E, which allow read-only, all and endinit protected access.
+ These macros also specify in which ISA version the csfr was introduced. */
#define R(ADDRESS, REG, FEATURE) \
case ADDRESS: \
if (has_feature(ctx, FEATURE)) { \
@@ -362,7 +362,7 @@
#undef E
#define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
- since no execption occurs */
+ since no exception occurs */
#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
case ADDRESS: \
if (has_feature(ctx, FEATURE)) { \
diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
index 2462c26..462289f 100644
--- a/tests/tcg/Makefile.target
+++ b/tests/tcg/Makefile.target
@@ -120,7 +120,7 @@
%: %.S
$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
else
-# For softmmu targets we include a different Makefile fragement as the
+# For softmmu targets we include a different Makefile fragment as the
# build options for bare programs are usually pretty different. They
# are expected to provide their own build recipes.
EXTRA_CFLAGS += -ffreestanding
@@ -154,7 +154,7 @@
# pre-requistes manually here as we can't use stems to handle it. We
# only expand MULTIARCH_TESTS which are common on most of our targets
# to avoid an exponential explosion as new tests are added. We also
-# add some special helpers the run-plugin- rules can use bellow.
+# add some special helpers the run-plugin- rules can use below.
ifneq ($(MULTIARCH_TESTS),)
$(foreach p,$(PLUGINS), \
diff --git a/tests/tcg/aarch64/gdbstub/test-sve.py b/tests/tcg/aarch64/gdbstub/test-sve.py
index b96bdbb..ef57c74 100644
--- a/tests/tcg/aarch64/gdbstub/test-sve.py
+++ b/tests/tcg/aarch64/gdbstub/test-sve.py
@@ -1,6 +1,6 @@
from __future__ import print_function
#
-# Test the SVE registers are visable and changeable via gdbstub
+# Test the SVE registers are visible and changeable via gdbstub
#
# This is launched via tests/guest-debug/run-test.py
#
diff --git a/tests/tcg/aarch64/sme-outprod1.c b/tests/tcg/aarch64/sme-outprod1.c
index 6e5972d..0c814ed 100644
--- a/tests/tcg/aarch64/sme-outprod1.c
+++ b/tests/tcg/aarch64/sme-outprod1.c
@@ -28,7 +28,7 @@
" fmopa za1.s, p0/m, p0/m, z0.s, z0.s\n"
/*
* Read the first 4x4 sub-matrix of elements from tile 1:
- * Note that za1h should be interchangable here.
+ * Note that za1h should be interchangeable here.
*/
" mov w12, #0\n"
" mova z0.s, p0/m, za1v.s[w12, #0]\n"
diff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boot.S
index f136363..501685d 100644
--- a/tests/tcg/aarch64/system/boot.S
+++ b/tests/tcg/aarch64/system/boot.S
@@ -9,7 +9,7 @@
/*
* Semihosting interface on ARM AArch64
- * See "Semihosting for AArch32 and AArch64 Relase 2.0" by ARM
+ * See "Semihosting for AArch32 and AArch64 Release 2.0" by ARM
* w0 - semihosting call number
* x1 - semihosting parameter
*/
@@ -147,7 +147,7 @@
* T0SZ[5:0] = 2^(64 - 25)
*
* The size of T0SZ controls what the initial lookup level. It
- * would be nice to start at level 2 but unfortunatly for a
+ * would be nice to start at level 2 but unfortunately for a
* flat-mapping on the virt machine we need to handle IA's
* with at least 1gb range to see RAM. So we start with a
* level 1 lookup.
@@ -189,7 +189,7 @@
msr cpacr_el1, x0
/* Setup some stack space and enter the test code.
- * Assume everthing except the return value is garbage when we
+ * Assume everything except the return value is garbage when we
* return, we won't need it.
*/
adrp x0, stack_end
diff --git a/tests/tcg/aarch64/system/semiheap.c b/tests/tcg/aarch64/system/semiheap.c
index 693a1b0..1a8c0f3 100644
--- a/tests/tcg/aarch64/system/semiheap.c
+++ b/tests/tcg/aarch64/system/semiheap.c
@@ -86,7 +86,7 @@
}
ptr_to_heap++;
}
- ml_printf("r/w to heap upto %p\n", ptr_to_heap);
+ ml_printf("r/w to heap up to %p\n", ptr_to_heap);
ml_printf("Passed HeapInfo checks\n");
return 0;
diff --git a/tests/tcg/multiarch/sha512.c b/tests/tcg/multiarch/sha512.c
index 9e701bc..12c2b6c 100644
--- a/tests/tcg/multiarch/sha512.c
+++ b/tests/tcg/multiarch/sha512.c
@@ -453,7 +453,7 @@
/* From hex.h */
/**
* hex_decode - Unpack a hex string.
- * @str: the hexidecimal string
+ * @str: the hexadecimal string
* @slen: the length of @str
* @buf: the buffer to write the data into
* @bufsize: the length of @buf
diff --git a/tests/tcg/multiarch/system/Makefile.softmmu-target b/tests/tcg/multiarch/system/Makefile.softmmu-target
index fe40195..7ba9053 100644
--- a/tests/tcg/multiarch/system/Makefile.softmmu-target
+++ b/tests/tcg/multiarch/system/Makefile.softmmu-target
@@ -3,7 +3,7 @@
# Multiarch system tests
#
# We just collect the tests together here and rely on the actual guest
-# architecture to add to the test dependancies and deal with the
+# architecture to add to the test dependencies and deal with the
# complications of building.
#
diff --git a/tests/tcg/s390x/mvc.c b/tests/tcg/s390x/mvc.c
index 7ae4c44..b572aa3 100644
--- a/tests/tcg/s390x/mvc.c
+++ b/tests/tcg/s390x/mvc.c
@@ -85,7 +85,7 @@
}
}
- /* test if MVC works now correctly accross page boundaries */
+ /* test if MVC works now correctly across page boundaries */
mvc_256(dst + 4096 - 128, src + 4096 - 128);
for (i = 0; i < ALLOC_SIZE; i++) {
if (src[i] != 0xff) {
diff --git a/tests/tcg/tricore/c/crt0-tc2x.S b/tests/tcg/tricore/c/crt0-tc2x.S
index 3100da1..399f112 100644
--- a/tests/tcg/tricore/c/crt0-tc2x.S
+++ b/tests/tcg/tricore/c/crt0-tc2x.S
@@ -263,7 +263,7 @@
ld.w %d3,[%a13+]4 # %d3 = block length
jeq %d3,-1,__copy_table_done # length == -1 => end of table
sh %d0,%d3,-3 # %d0 = length / 8 (doublewords)
- and %d1,%d3,7 # %d1 = lenght % 8 (rem. bytes)
+ and %d1,%d3,7 # %d1 = length % 8 (rem. bytes)
jz %d0,__copy_word # block size < 8 => copy word
addi %d0,%d0,-1 # else doublewords -= 1
mov.a %a2,%d0 # %a2 = loop counter
@@ -274,7 +274,7 @@
__copy_word:
jz %d1,__copy_table_next
sh %d0,%d1,-2 # %d0 = length / 4 (words)
- and %d1,%d1,3 # %d1 = lenght % 4 (rem. bytes)
+ and %d1,%d1,3 # %d1 = length % 4 (rem. bytes)
jz %d0,__copy_hword # block size < 4 => copy hword
ld.w %d14,[%a15+]4 # copy one word
st.w [%a14+]4,%d14
diff --git a/tests/tcg/x86_64/system/boot.S b/tests/tcg/x86_64/system/boot.S
index ed0f638..dac9bd5 100644
--- a/tests/tcg/x86_64/system/boot.S
+++ b/tests/tcg/x86_64/system/boot.S
@@ -121,7 +121,7 @@
// Setup stack ASAP
movq $stack_end,%rsp
- /* don't worry about stack frame, assume everthing is garbage when we return */
+ /* don't worry about stack frame, assume everything is garbage when we return */
call main
_exit: /* output any non-zero result in eax to isa-debug-exit device */
@@ -195,7 +195,7 @@
*
* This describes various memory areas (segments) through
* segment descriptors. In 32 bit mode each segment each
- * segement is associated with segment registers which are
+ * segment is associated with segment registers which are
* implicitly (or explicitly) referenced depending on the
* instruction. However in 64 bit mode selectors are flat and
* segmented addressing isn't used.
