)]}'
{
  "commit": "5fbe0fc35a3ea39ff089ea6cda86747ebbb68102",
  "tree": "efdc3e96dcd897531b9a11a32705c590e6cc8cab",
  "parents": [
    "d8e135369a363750b4a131ee3e272813f5e9419a"
  ],
  "author": {
    "name": "Yubin Zou",
    "email": "yubinz@google.com",
    "time": "Fri Dec 19 07:04:14 2025 +0000"
  },
  "committer": {
    "name": "Cédric Le Goater",
    "email": "clg@redhat.com",
    "time": "Mon Jan 05 10:38:02 2026 +0100"
  },
  "message": "hw/gpio/aspeed_sgpio: Add basic device model for Aspeed SGPIO\n\nThis initial implementation includes the basic device structure,\nmemory-mapped register definitions, and read/write handlers for the\nSGPIO control registers.\n\nSigned-off-by: Yubin Zou \u003cyubinz@google.com\u003e\nReviewed-by: Kane Chen \u003ckane_chen@aspeedtech.com\u003e\nLink: https://lore.kernel.org/qemu-devel/20251219-aspeed-sgpio-v5-1-fd5593178144@google.com\nSigned-off-by: Cédric Le Goater \u003cclg@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "538fb5145c3d7a0e6afecb8ca786cb0240403bef",
      "new_mode": 33188,
      "new_path": "hw/gpio/aspeed_sgpio.c"
    },
    {
      "type": "modify",
      "old_id": "74840619c01bf4d9a02c058c434c3ec9d2a55bee",
      "old_mode": 33188,
      "old_path": "hw/gpio/meson.build",
      "new_id": "6a67ee958faace69ffd3fe08e8ade31ced0faf7e",
      "new_mode": 33188,
      "new_path": "hw/gpio/meson.build"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "7da48920eebff234000017dc34d83f2c44c48c5d",
      "new_mode": 33188,
      "new_path": "include/hw/gpio/aspeed_sgpio.h"
    }
  ]
}