commit 58d2a9aef4cacb3056f5b12c1eb92105704183fe
author Aurelien Jarno <aurelien@aurel32.net> Mon May 01 23:20:43 2017 +0200
committer Aurelien Jarno <aurelien@aurel32.net> Sat May 13 11:18:26 2017 +0200
tree d58e1eae93317e26c0b1ca80f8b79e17ea5b7d07
parent b3995c23edff05631f90143f68866aed776e80f9

target/sh4: optimize gen_store_fpr64

Using extr and avoiding intermediate temps.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

target/sh4/translate.c

diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index a4c7a08..fe8bff5 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -305,13 +305,7 @@
 
 static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
 {
-    TCGv_i32 tmp = tcg_temp_new_i32();
-    tcg_gen_extrl_i64_i32(tmp, t);
-    tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp);
-    tcg_gen_shri_i64(t, t, 32);
-    tcg_gen_extrl_i64_i32(tmp, t);
-    tcg_gen_mov_i32(cpu_fregs[reg], tmp);
-    tcg_temp_free_i32(tmp);
+    tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t);
 }
 
 #define B3_0 (ctx->opcode & 0xf)