fpu: Rename float_flag_input_denormal to float_flag_input_denormal_flushed
Our float_flag_input_denormal exception flag is set when the fpu code
flushes an input denormal to zero. This is what many guest
architectures (eg classic Arm behaviour) require, but it is not the
only donarmal-related reason we might want to set an exception flag.
The x86 behaviour (which we do not currently model correctly) wants
to see an exception flag when a denormal input is *not* flushed to
zero and is actually used in an arithmetic operation. Arm's FEAT_AFP
also wants these semantics.
Rename float_flag_input_denormal to float_flag_input_denormal_flushed
to make it clearer when it is set and to allow us to add a new
float_flag_input_denormal_used next to it for the x86/FEAT_AFP
semantics.
Commit created with
for f in `git grep -l float_flag_input_denormal`; do sed -i -e 's/float_flag_input_denormal/float_flag_input_denormal_flushed/' $f; done
and manual editing of softfloat-types.h and softfloat.c to clean
up the indentation afterwards and to fix a comment which wasn't
using the full name of the flag.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-20-peter.maydell@linaro.org
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index ebde429..b3d693e 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -198,7 +198,7 @@
if (likely(frac_eqz(p))) {
p->cls = float_class_zero;
} else if (status->flush_inputs_to_zero) {
- float_raise(float_flag_input_denormal, status);
+ float_raise(float_flag_input_denormal_flushed, status);
p->cls = float_class_zero;
frac_clear(p);
} else {
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 8d75d66..648050b 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -132,7 +132,7 @@
if (unlikely(soft_t ## _is_denormal(*a))) { \
*a = soft_t ## _set_sign(soft_t ## _zero, \
soft_t ## _is_neg(*a)); \
- float_raise(float_flag_input_denormal, s); \
+ float_raise(float_flag_input_denormal_flushed, s); \
} \
}
@@ -4848,7 +4848,7 @@
static bool parts_squash_denormal(FloatParts64 p, float_status *status)
{
if (p.exp == 0 && p.frac != 0) {
- float_raise(float_flag_input_denormal, status);
+ float_raise(float_flag_input_denormal_flushed, status);
return true;
}
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 9d37cdf..24cd290 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -154,7 +154,8 @@
float_flag_overflow = 0x0004,
float_flag_underflow = 0x0008,
float_flag_inexact = 0x0010,
- float_flag_input_denormal = 0x0020,
+ /* We flushed an input denormal to 0 (because of flush_inputs_to_zero) */
+ float_flag_input_denormal_flushed = 0x0020,
float_flag_output_denormal = 0x0040,
float_flag_invalid_isi = 0x0080, /* inf - inf */
float_flag_invalid_imz = 0x0100, /* inf * 0 */
@@ -302,7 +303,7 @@
bool tininess_before_rounding;
/* should denormalised results go to zero and set the inexact flag? */
bool flush_to_zero;
- /* should denormalised inputs go to zero and set the input_denormal flag? */
+ /* should denormalised inputs go to zero and set input_denormal_flushed? */
bool flush_inputs_to_zero;
bool default_nan_mode;
/*
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
index d0865de..9837c5bc 100644
--- a/target/arm/tcg/sve_helper.c
+++ b/target/arm/tcg/sve_helper.c
@@ -4658,7 +4658,7 @@
return -15 - clz32(frac);
}
/* flush to zero */
- float_raise(float_flag_input_denormal, s);
+ float_raise(float_flag_input_denormal_flushed, s);
}
} else if (unlikely(exp == 0x1f)) {
if (frac == 0) {
@@ -4686,7 +4686,7 @@
return -127 - clz32(frac);
}
/* flush to zero */
- float_raise(float_flag_input_denormal, s);
+ float_raise(float_flag_input_denormal_flushed, s);
}
} else if (unlikely(exp == 0xff)) {
if (frac == 0) {
@@ -4714,7 +4714,7 @@
return -1023 - clz64(frac);
}
/* flush to zero */
- float_raise(float_flag_input_denormal, s);
+ float_raise(float_flag_input_denormal_flushed, s);
}
} else if (unlikely(exp == 0x7ff)) {
if (frac == 0) {
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 3ed69d7..444702a 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -53,7 +53,7 @@
if (host_bits & float_flag_inexact) {
target_bits |= FPSR_IXC;
}
- if (host_bits & float_flag_input_denormal) {
+ if (host_bits & float_flag_input_denormal_flushed) {
target_bits |= FPSR_IDC;
}
return target_bits;
@@ -68,11 +68,11 @@
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
/* FZ16 does not generate an input denormal exception. */
i |= (get_float_exception_flags(&env->vfp.fp_status_f16_a32)
- & ~float_flag_input_denormal);
+ & ~float_flag_input_denormal_flushed);
i |= (get_float_exception_flags(&env->vfp.fp_status_f16_a64)
- & ~float_flag_input_denormal);
+ & ~float_flag_input_denormal_flushed);
i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16)
- & ~float_flag_input_denormal);
+ & ~float_flag_input_denormal_flushed);
return vfp_exceptbits_from_host(i);
}
@@ -1133,7 +1133,7 @@
/* Normal inexact, denormal with flush-to-zero, or overflow or NaN */
inexact = e_new & (float_flag_inexact |
- float_flag_input_denormal |
+ float_flag_input_denormal_flushed |
float_flag_invalid);
/* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index d0a1e2f..9c33ac7 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -204,7 +204,7 @@
(new_flags & float_flag_overflow ? FPUS_OE : 0) |
(new_flags & float_flag_underflow ? FPUS_UE : 0) |
(new_flags & float_flag_inexact ? FPUS_PE : 0) |
- (new_flags & float_flag_input_denormal ? FPUS_DE : 0)));
+ (new_flags & float_flag_input_denormal_flushed ? FPUS_DE : 0)));
}
static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 b)
@@ -1829,7 +1829,7 @@
int shift = clz64(temp.l.lower);
temp.l.lower <<= shift;
expdif = 1 - EXPBIAS - shift;
- float_raise(float_flag_input_denormal, &env->fp_status);
+ float_raise(float_flag_input_denormal_flushed, &env->fp_status);
} else {
expdif = EXPD(temp) - EXPBIAS;
}
@@ -3258,7 +3258,7 @@
uint8_t flags = get_float_exception_flags(&env->sse_status);
/*
* The MXCSR denormal flag has opposite semantics to
- * float_flag_input_denormal (the softfloat code sets that flag
+ * float_flag_input_denormal_flushed (the softfloat code sets that flag
* only when flushing input denormals to zero, but SSE sets it
* only when not flushing them to zero), so is not converted
* here.
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index 1d40383..aeab6a1 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -6231,7 +6231,7 @@
enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
/* Set Inexact (I) when flushing inputs to zero */
- if ((ieee_exception_flags & float_flag_input_denormal) &&
+ if ((ieee_exception_flags & float_flag_input_denormal_flushed) &&
(env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
if (action & CLEAR_IS_INEXACT) {
mips_exception_flags &= ~FP_INEXACT;
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
index 691a12b..59dd1ae 100644
--- a/target/rx/op_helper.c
+++ b/target/rx/op_helper.c
@@ -99,7 +99,7 @@
if (xcpt & float_flag_inexact) {
SET_FPSW(X);
}
- if ((xcpt & (float_flag_input_denormal
+ if ((xcpt & (float_flag_input_denormal_flushed
| float_flag_output_denormal))
&& !FIELD_EX32(env->fpsw, FPSW, DN)) {
env->fpsw = FIELD_DP32(env->fpsw, FPSW, CE, 1);
