Merge tag 'pull-tcg-20240507' of https://gitlab.com/rth7680/qemu into staging
tcg: Add write_aofs to GVecGen3i
tcg/i386: Simplify immediate 8-bit logical vector shifts
tcg/i386: Optimize setcond of TST{EQ,NE} with 0xffffffff
tcg/optimize: Optimize setcond with zmask
accel/tcg: Introduce CF_BP_PAGE
target/sh4: Update DisasContextBase.insn_start
gitlab: Drop --static from s390x linux-user build
gitlab: Streamline ubuntu-22.04-s390x
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# =FJCW
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 May 2024 07:28:16 AM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-tcg-20240507' of https://gitlab.com/rth7680/qemu:
gitlab: Streamline ubuntu-22.04-s390x
gitlab: Drop --static from s390x linux-user build
gitlab: Drop --disable-libssh from ubuntu-22.04-s390x.yml
target/sh4: Update DisasContextBase.insn_start
accel/tcg: Introduce CF_BP_PAGE
tcg/optimize: Optimize setcond with zmask
tcg/i386: Optimize setcond of TST{EQ,NE} with 0xffffffff
tcg/i386: Simplify immediate 8-bit logical vector shifts
tcg: Add write_aofs to GVecGen3i
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/MAINTAINERS b/MAINTAINERS
index 2f08cc5..8439177 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -167,6 +167,7 @@
F: include/exec/helper*.h
F: include/exec/helper*.h.inc
F: include/exec/helper-info.c.inc
+F: include/exec/page-protection.h
F: include/sysemu/cpus.h
F: include/sysemu/tcg.h
F: include/hw/core/tcg-cpu-ops.h
@@ -284,7 +285,7 @@
M: Philippe Mathieu-Daudé <philmd@linaro.org>
R: Aurelien Jarno <aurelien@aurel32.net>
R: Jiaxun Yang <jiaxun.yang@flygoat.com>
-R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
+R: Aleksandar Rikalo <arikalo@gmail.com>
S: Odd Fixes
F: target/mips/
F: disas/*mips.c
@@ -319,7 +320,7 @@
RISC-V TCG CPUs
M: Palmer Dabbelt <palmer@dabbelt.com>
M: Alistair Francis <alistair.francis@wdc.com>
-M: Bin Meng <bin.meng@windriver.com>
+M: Bin Meng <bmeng.cn@gmail.com>
R: Weiwei Li <liwei1518@gmail.com>
R: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
@@ -1334,7 +1335,7 @@
Jazz
M: Hervé Poussineau <hpoussin@reactos.org>
-R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
+R: Aleksandar Rikalo <arikalo@gmail.com>
S: Maintained
F: hw/mips/jazz.c
F: hw/display/g364fb.c
@@ -1356,7 +1357,7 @@
F: tests/avocado/machine_mips_malta.py
Mipssim
-R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
+R: Aleksandar Rikalo <arikalo@gmail.com>
S: Orphan
F: hw/mips/mipssim.c
F: hw/net/mipsnet.c
@@ -1384,7 +1385,7 @@
Boston
M: Paul Burton <paulburton@kernel.org>
-R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
+R: Aleksandar Rikalo <arikalo@gmail.com>
S: Odd Fixes
F: hw/core/loader-fit.c
F: hw/mips/boston.c
@@ -1602,7 +1603,7 @@
F: include/hw/*/ibex_*.h
Microchip PolarFire SoC Icicle Kit
-M: Bin Meng <bin.meng@windriver.com>
+M: Bin Meng <bmeng.cn@gmail.com>
L: qemu-riscv@nongnu.org
S: Supported
F: docs/system/riscv/microchip-icicle-kit.rst
@@ -1629,7 +1630,7 @@
SiFive Machines
M: Alistair Francis <Alistair.Francis@wdc.com>
-M: Bin Meng <bin.meng@windriver.com>
+M: Bin Meng <bmeng.cn@gmail.com>
M: Palmer Dabbelt <palmer@dabbelt.com>
L: qemu-riscv@nongnu.org
S: Supported
@@ -2125,7 +2126,7 @@
SD (Secure Card)
M: Philippe Mathieu-Daudé <philmd@linaro.org>
-M: Bin Meng <bin.meng@windriver.com>
+M: Bin Meng <bmeng.cn@gmail.com>
L: qemu-block@nongnu.org
S: Odd Fixes
F: include/hw/sd/sd*
@@ -3761,7 +3762,7 @@
R: Aurelien Jarno <aurelien@aurel32.net>
R: Huacai Chen <chenhuacai@kernel.org>
R: Jiaxun Yang <jiaxun.yang@flygoat.com>
-R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
+R: Aleksandar Rikalo <arikalo@gmail.com>
S: Odd Fixes
F: tcg/mips/
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 6a764f5..2972f75 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -147,6 +147,16 @@
}
#endif /* CONFIG USER ONLY */
+bool tcg_cflags_has(CPUState *cpu, uint32_t flags)
+{
+ return cpu->tcg_cflags & flags;
+}
+
+void tcg_cflags_set(CPUState *cpu, uint32_t flags)
+{
+ cpu->tcg_cflags |= flags;
+}
+
uint32_t curr_cflags(CPUState *cpu)
{
uint32_t cflags = cpu->tcg_cflags;
@@ -900,8 +910,6 @@
vaddr pc, TranslationBlock **last_tb,
int *tb_exit)
{
- int32_t insns_left;
-
trace_exec_tb(tb, pc);
tb = cpu_tb_exec(cpu, tb, tb_exit);
if (*tb_exit != TB_EXIT_REQUESTED) {
@@ -910,8 +918,7 @@
}
*last_tb = NULL;
- insns_left = qatomic_read(&cpu->neg.icount_decr.u32);
- if (insns_left < 0) {
+ if (cpu_loop_exit_requested(cpu)) {
/* Something asked us to stop executing chained TBs; just
* continue round the main loop. Whatever requested the exit
* will also have set something else (eg exit_request or
@@ -928,7 +935,7 @@
/* Ensure global icount has gone forward */
icount_update(cpu);
/* Refill decrementer and continue execution. */
- insns_left = MIN(0xffff, cpu->icount_budget);
+ int32_t insns_left = MIN(0xffff, cpu->icount_budget);
cpu->neg.icount_decr.u16.low = insns_left;
cpu->icount_extra = cpu->icount_budget - insns_left;
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 953c437..cdb3e12 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -21,6 +21,7 @@
#include "qemu/main-loop.h"
#include "hw/core/tcg-cpu-ops.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "exec/memory.h"
#include "exec/cpu_ldst.h"
#include "exec/cputlb.h"
diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h
index edefd0d..cff43d2 100644
--- a/accel/tcg/internal-common.h
+++ b/accel/tcg/internal-common.h
@@ -9,6 +9,7 @@
#ifndef ACCEL_TCG_INTERNAL_COMMON_H
#define ACCEL_TCG_INTERNAL_COMMON_H
+#include "exec/cpu-common.h"
#include "exec/translation-block.h"
extern int64_t max_delay;
@@ -20,7 +21,24 @@
*/
static inline bool cpu_in_serial_context(CPUState *cs)
{
- return !(cs->tcg_cflags & CF_PARALLEL) || cpu_in_exclusive_context(cs);
+ return !tcg_cflags_has(cs, CF_PARALLEL) || cpu_in_exclusive_context(cs);
+}
+
+/**
+ * cpu_plugin_mem_cbs_enabled() - are plugin memory callbacks enabled?
+ * @cs: CPUState pointer
+ *
+ * The memory callbacks are installed if a plugin has instrumented an
+ * instruction for memory. This can be useful to know if you want to
+ * force a slow path for a series of memory accesses.
+ */
+static inline bool cpu_plugin_mem_cbs_enabled(const CPUState *cpu)
+{
+#ifdef CONFIG_PLUGIN
+ return !!cpu->neg.plugin_mem_cbs;
+#else
+ return false;
+#endif
}
#endif
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index 3db74ae..49f5d1c 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -55,7 +55,7 @@
* Tracking memory accesses performed from helpers requires extra work.
* If an instruction is emulated with helpers, we do two things:
* (1) copy the CB descriptors, and keep track of it so that they can be
- * freed later on, and (2) point CPUState.plugin_mem_cbs to the
+ * freed later on, and (2) point CPUState.neg.plugin_mem_cbs to the
* descriptors, so that we can read them at run-time
* (i.e. when the helper executes).
* This run-time access is performed from qemu_plugin_vcpu_mem_cb.
@@ -90,14 +90,14 @@
qemu_plugin_add_dyn_cb_arr(arr);
tcg_gen_st_ptr(tcg_constant_ptr((intptr_t)arr), tcg_env,
- offsetof(CPUState, plugin_mem_cbs) -
+ offsetof(CPUState, neg.plugin_mem_cbs) -
offsetof(ArchCPU, env));
}
static void gen_disable_mem_helper(void)
{
tcg_gen_st_ptr(tcg_constant_ptr(0), tcg_env,
- offsetof(CPUState, plugin_mem_cbs) -
+ offsetof(CPUState, neg.plugin_mem_cbs) -
offsetof(ArchCPU, env));
}
diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c
index da39a43..19ae679 100644
--- a/accel/tcg/tb-maint.c
+++ b/accel/tcg/tb-maint.c
@@ -23,6 +23,7 @@
#include "exec/cputlb.h"
#include "exec/log.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "exec/tb-flush.h"
#include "exec/translate-all.h"
#include "sysemu/tcg.h"
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
index 2c7b0cc..1433e38 100644
--- a/accel/tcg/tcg-accel-ops.c
+++ b/accel/tcg/tcg-accel-ops.c
@@ -62,7 +62,7 @@
cflags |= parallel ? CF_PARALLEL : 0;
cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;
- cpu->tcg_cflags |= cflags;
+ tcg_cflags_set(cpu, cflags);
}
void tcg_cpu_destroy(CPUState *cpu)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 83cc14f..fdf6d8a 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -644,15 +644,6 @@
cpu_loop_exit_noexc(cpu);
}
-#else /* CONFIG_USER_ONLY */
-
-void cpu_interrupt(CPUState *cpu, int mask)
-{
- g_assert(bql_locked());
- cpu->interrupt_request |= mask;
- qatomic_set(&cpu->neg.icount_decr.u16.high, -1);
-}
-
#endif /* CONFIG_USER_ONLY */
/*
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 1c62147..80d2454 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -24,7 +24,9 @@
#include "qemu/bitops.h"
#include "qemu/rcu.h"
#include "exec/cpu_ldst.h"
+#include "qemu/main-loop.h"
#include "exec/translate-all.h"
+#include "exec/page-protection.h"
#include "exec/helper-proto.h"
#include "qemu/atomic128.h"
#include "trace/trace-root.h"
@@ -37,6 +39,13 @@
//#define DEBUG_SIGNAL
+void cpu_interrupt(CPUState *cpu, int mask)
+{
+ g_assert(bql_locked());
+ cpu->interrupt_request |= mask;
+ qatomic_set(&cpu->neg.icount_decr.u16.high, -1);
+}
+
/*
* Adjust the pc to pass to cpu_restore_state; return the memop type.
*/
@@ -765,7 +774,7 @@
if (prot & PAGE_EXEC) {
prot = (prot & ~PAGE_EXEC) | PAGE_READ;
}
- mprotect((void *)g2h_untagged(start), len, prot & PAGE_BITS);
+ mprotect((void *)g2h_untagged(start), len, prot & PAGE_RWX);
}
mmap_unlock();
diff --git a/accel/tcg/vcpu-state.h b/accel/tcg/vcpu-state.h
new file mode 100644
index 0000000..e407d91
--- /dev/null
+++ b/accel/tcg/vcpu-state.h
@@ -0,0 +1,18 @@
+/*
+ * SPDX-FileContributor: Philippe Mathieu-Daudé <philmd@linaro.org>
+ * SPDX-FileCopyrightText: 2023 Linaro Ltd.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef ACCEL_TCG_VCPU_STATE_H
+#define ACCEL_TCG_VCPU_STATE_H
+
+#include "hw/core/cpu.h"
+
+#ifdef CONFIG_USER_ONLY
+static inline TaskState *get_task_state(const CPUState *cs)
+{
+ return cs->opaque;
+}
+#endif
+
+#endif
diff --git a/bsd-user/bsd-mem.h b/bsd-user/bsd-mem.h
index 21d9bab..eef6b22 100644
--- a/bsd-user/bsd-mem.h
+++ b/bsd-user/bsd-mem.h
@@ -56,6 +56,7 @@
#include <fcntl.h>
#include "qemu-bsd.h"
+#include "exec/page-protection.h"
extern struct bsd_shm_regions bsd_shm_regions[];
extern abi_ulong target_brk;
diff --git a/bsd-user/mmap.c b/bsd-user/mmap.c
index 3ef11b2..f3a4f17 100644
--- a/bsd-user/mmap.c
+++ b/bsd-user/mmap.c
@@ -17,6 +17,7 @@
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
+#include "exec/page-protection.h"
#include "qemu.h"
@@ -96,7 +97,7 @@
end = host_end;
}
ret = mprotect(g2h_untagged(host_start),
- qemu_host_page_size, prot1 & PAGE_BITS);
+ qemu_host_page_size, prot1 & PAGE_RWX);
if (ret != 0)
goto error;
host_start += qemu_host_page_size;
@@ -107,7 +108,7 @@
prot1 |= page_get_flags(addr);
}
ret = mprotect(g2h_untagged(host_end - qemu_host_page_size),
- qemu_host_page_size, prot1 & PAGE_BITS);
+ qemu_host_page_size, prot1 & PAGE_RWX);
if (ret != 0)
goto error;
host_end -= qemu_host_page_size;
@@ -174,7 +175,7 @@
return -1;
prot1 = prot;
}
- prot1 &= PAGE_BITS;
+ prot1 &= PAGE_RWX;
prot_new = prot | prot1;
if (fd != -1) {
diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index a916724..9d2fc71 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -34,7 +34,9 @@
#include "target_os_signal.h"
#include "target.h"
#include "exec/gdbstub.h"
+#include "exec/page-protection.h"
#include "qemu/clang-tsa.h"
+#include "accel/tcg/vcpu-state.h"
#include "qemu-os.h"
/*
@@ -75,7 +77,7 @@
/*
* NOTE: we force a big alignment so that the stack stored after is aligned too
*/
-typedef struct TaskState {
+struct TaskState {
pid_t ts_tid; /* tid (or pid) of this task */
struct TaskState *next;
@@ -113,12 +115,7 @@
/* This thread's sigaltstack, if it has one */
struct target_sigaltstack sigaltstack_used;
-} __attribute__((aligned(16))) TaskState;
-
-static inline TaskState *get_task_state(CPUState *cs)
-{
- return cs->opaque;
-}
+} __attribute__((aligned(16)));
void stop_all_tasks(void);
extern const char *interp_prefix;
diff --git a/bsd-user/signal.c b/bsd-user/signal.c
index b2faf1d..8b6654b 100644
--- a/bsd-user/signal.c
+++ b/bsd-user/signal.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu.h"
+#include "exec/page-protection.h"
#include "user/tswap-target.h"
#include "gdbstub/user.h"
#include "signal-common.h"
diff --git a/cpu-target.c b/cpu-target.c
index f88649c..5af120e 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -21,6 +21,7 @@
#include "qapi/error.h"
#include "exec/target_page.h"
+#include "exec/page-protection.h"
#include "hw/qdev-core.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 7b8aafa..03f8b1b 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -194,6 +194,15 @@
an alias, but for consistency these will get removed in a future
release, too. Use ``power5p_v2.1`` and ``power7p_v2.1`` instead.
+``Sun-UltraSparc-IIIi+`` and ``Sun-UltraSparc-IV+`` CPU names (since 9.1)
+'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+The character "+" in device (and thus also CPU) names is not allowed
+in the QEMU object model anymore. ``Sun-UltraSparc-IIIi+`` and
+``Sun-UltraSparc-IV+`` are currently still supported via a workaround,
+but for consistency these will get removed in a future release, too.
+Use ``Sun-UltraSparc-IIIi-plus`` and ``Sun-UltraSparc-IV-plus`` instead.
+
CRIS CPU architecture (since 9.0)
'''''''''''''''''''''''''''''''''
diff --git a/docs/sphinx/qapidoc.py b/docs/sphinx/qapidoc.py
index 8d428c6..f270b49 100644
--- a/docs/sphinx/qapidoc.py
+++ b/docs/sphinx/qapidoc.py
@@ -145,22 +145,22 @@
term.extend(self._nodes_for_ifcond(member.ifcond))
return term
- def _nodes_for_variant_when(self, variants, variant):
+ def _nodes_for_variant_when(self, branches, variant):
"""Return list of Text, literal nodes for variant 'when' clause
Return a list of doctree nodes which give text like
'when tagname is variant (If: ...)' suitable for use in
- the 'variants' part of a definition list.
+ the 'branches' part of a definition list.
"""
term = [nodes.Text(' when '),
- nodes.literal('', variants.tag_member.name),
+ nodes.literal('', branches.tag_member.name),
nodes.Text(' is '),
nodes.literal('', '"%s"' % variant.name)]
if variant.ifcond.is_present():
term.extend(self._nodes_for_ifcond(variant.ifcond))
return term
- def _nodes_for_members(self, doc, what, base=None, variants=None):
+ def _nodes_for_members(self, doc, what, base=None, branches=None):
"""Return list of doctree nodes for the table of members"""
dlnode = nodes.definition_list()
for section in doc.args.values():
@@ -178,14 +178,14 @@
nodes.literal('', base.doc_type())],
None)
- if variants:
- for v in variants.variants:
+ if branches:
+ for v in branches.variants:
if v.type.name == 'q_empty':
continue
assert not v.type.is_implicit()
term = [nodes.Text('The members of '),
nodes.literal('', v.type.doc_type())]
- term.extend(self._nodes_for_variant_when(variants, v))
+ term.extend(self._nodes_for_variant_when(branches, v))
dlnode += self._make_dlitem(term, None)
if not dlnode.children:
@@ -308,17 +308,18 @@
+ self._nodes_for_if_section(ifcond))
def visit_object_type(self, name, info, ifcond, features,
- base, members, variants):
+ base, members, branches):
doc = self._cur_doc
if base and base.is_implicit():
base = None
self._add_doc('Object',
- self._nodes_for_members(doc, 'Members', base, variants)
+ self._nodes_for_members(doc, 'Members', base, branches)
+ self._nodes_for_features(doc)
+ self._nodes_for_sections(doc)
+ self._nodes_for_if_section(ifcond))
- def visit_alternate_type(self, name, info, ifcond, features, variants):
+ def visit_alternate_type(self, name, info, ifcond, features,
+ alternatives):
doc = self._cur_doc
self._add_doc('Alternate',
self._nodes_for_members(doc, 'Members')
diff --git a/docs/system/target-sparc.rst b/docs/system/target-sparc.rst
index 9ec8c90..4116cac 100644
--- a/docs/system/target-sparc.rst
+++ b/docs/system/target-sparc.rst
@@ -27,6 +27,11 @@
The emulation is somewhat complete. SMP up to 16 CPUs is supported, but
Linux limits the number of usable CPUs to 4.
+The list of available CPUs can be viewed by starting QEMU with ``-cpu help``.
+Optional boolean features can be added with a "+" in front of the feature name,
+or disabled with a "-" in front of the name, for example
+``-cpu TI-SuperSparc-II,+float128``.
+
QEMU emulates the following sun4m peripherals:
- IOMMU
@@ -55,8 +60,5 @@
is to implement a 100% IEEE 1275-1994 (referred to as Open Firmware)
compliant firmware.
-A sample Linux 2.6 series kernel and ram disk image are available on the
-QEMU web site. There are still issues with NetBSD and OpenBSD, but most
-kernel versions work. Please note that currently older Solaris kernels
-don't work probably due to interface issues between OpenBIOS and
-Solaris.
+Please note that currently older Solaris kernels don't work; this is probably
+due to interface issues between OpenBIOS and Solaris.
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 9c2b8b5..b357499 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -32,6 +32,7 @@
#include "exec/gdbstub.h"
#include "gdbstub/syscalls.h"
#ifdef CONFIG_USER_ONLY
+#include "accel/tcg/vcpu-state.h"
#include "gdbstub/user.h"
#else
#include "hw/cpu/cluster.h"
@@ -1661,7 +1662,7 @@
#if defined(CONFIG_USER_ONLY)
#if defined(CONFIG_LINUX)
- if (gdbserver_state.c_cpu->opaque) {
+ if (get_task_state(gdbserver_state.c_cpu)) {
g_string_append(gdbserver_state.str_buf, ";qXfer:auxv:read+");
}
g_string_append(gdbserver_state.str_buf, ";QCatchSyscalls+");
diff --git a/gdbstub/user-target.c b/gdbstub/user-target.c
index 6646684..a9c6c64 100644
--- a/gdbstub/user-target.c
+++ b/gdbstub/user-target.c
@@ -216,7 +216,7 @@
{
TaskState *ts;
- ts = gdbserver_state.c_cpu->opaque;
+ ts = get_task_state(gdbserver_state.c_cpu);
g_string_printf(gdbserver_state.str_buf,
"Text=" TARGET_ABI_FMT_lx
";Data=" TARGET_ABI_FMT_lx
@@ -252,7 +252,7 @@
offset = get_param(params, 0)->val_ul;
len = get_param(params, 1)->val_ul;
- ts = gdbserver_state.c_cpu->opaque;
+ ts = get_task_state(gdbserver_state.c_cpu);
saved_auxv = ts->info->saved_auxv;
auxv_len = ts->info->auxv_len;
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index a72d48d..0f0a247 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -30,7 +30,9 @@
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "trace.h"
+#ifdef CONFIG_PLUGIN
#include "qemu/plugin.h"
+#endif
CPUState *cpu_by_arch_id(int64_t id)
{
@@ -236,9 +238,11 @@
CPUState *cpu = CPU(dev);
/* Call the plugin hook before clearing the cpu is fully unrealized */
+#ifdef CONFIG_PLUGIN
if (tcg_enabled()) {
qemu_plugin_vcpu_exit_hook(cpu);
}
+#endif
/* NOTE: latest generic point before the cpu is fully unrealized */
cpu_exec_unrealizefn(cpu);
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index e18f57e..73f80cf 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -15,6 +15,7 @@
#include "qemu/units.h"
#include "qemu/datadir.h"
#include "qemu/error-report.h"
+#include "exec/page-protection.h"
#include "net/net.h"
#include "hw/pci/pci.h"
#include "hw/boards.h"
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index d42b677..8dc75fb 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -21,6 +21,7 @@
#include "kvm_ppc.h"
#include "sysemu/device_tree.h"
#include "sysemu/block-backend.h"
+#include "exec/page-protection.h"
#include "hw/loader.h"
#include "elf.h"
#include "exec/memory.h"
diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
index d02f330..c49da1f 100644
--- a/hw/ppc/virtex_ml507.c
+++ b/hw/ppc/virtex_ml507.c
@@ -25,6 +25,7 @@
#include "qemu/osdep.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
+#include "exec/page-protection.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/char/serial.h"
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index cff6d5a..4ece1ac 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -793,6 +793,12 @@
sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
}
+static GlobalProperty hw_compat_sparc64[] = {
+ { "virtio-pci", "disable-legacy", "on", .optional = true },
+ { "virtio-device", "iommu_platform", "on" },
+};
+static const size_t hw_compat_sparc64_len = G_N_ELEMENTS(hw_compat_sparc64);
+
static void sun4u_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -810,6 +816,7 @@
mc->default_nic = "sunhme";
mc->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL);
fwc->get_dev_path = sun4u_fw_dev_path;
+ compat_props_add(mc->compat_props, hw_compat_sparc64, hw_compat_sparc64_len);
}
static const TypeInfo sun4u_type = {
diff --git a/hw/xen/xen-mapcache.c b/hw/xen/xen-mapcache.c
index 7f59080..fa6813b 100644
--- a/hw/xen/xen-mapcache.c
+++ b/hw/xen/xen-mapcache.c
@@ -74,14 +74,14 @@
static MapCache *mapcache;
-static inline void mapcache_lock(void)
+static inline void mapcache_lock(MapCache *mc)
{
- qemu_mutex_lock(&mapcache->lock);
+ qemu_mutex_lock(&mc->lock);
}
-static inline void mapcache_unlock(void)
+static inline void mapcache_unlock(MapCache *mc)
{
- qemu_mutex_unlock(&mapcache->lock);
+ qemu_mutex_unlock(&mc->lock);
}
static inline int test_bits(int nr, int size, const unsigned long *addr)
@@ -93,23 +93,44 @@
return 0;
}
-void xen_map_cache_init(phys_offset_to_gaddr_t f, void *opaque)
+static MapCache *xen_map_cache_init_single(phys_offset_to_gaddr_t f,
+ void *opaque,
+ unsigned long max_size)
{
unsigned long size;
+ MapCache *mc;
+
+ mc = g_new0(MapCache, 1);
+
+ mc->phys_offset_to_gaddr = f;
+ mc->opaque = opaque;
+ qemu_mutex_init(&mc->lock);
+
+ QTAILQ_INIT(&mc->locked_entries);
+
+ mc->max_mcache_size = max_size;
+
+ mc->nr_buckets =
+ (((mc->max_mcache_size >> XC_PAGE_SHIFT) +
+ (1UL << (MCACHE_BUCKET_SHIFT - XC_PAGE_SHIFT)) - 1) >>
+ (MCACHE_BUCKET_SHIFT - XC_PAGE_SHIFT));
+
+ size = mc->nr_buckets * sizeof(MapCacheEntry);
+ size = (size + XC_PAGE_SIZE - 1) & ~(XC_PAGE_SIZE - 1);
+ trace_xen_map_cache_init(mc->nr_buckets, size);
+ mc->entry = g_malloc0(size);
+ return mc;
+}
+
+void xen_map_cache_init(phys_offset_to_gaddr_t f, void *opaque)
+{
struct rlimit rlimit_as;
-
- mapcache = g_new0(MapCache, 1);
-
- mapcache->phys_offset_to_gaddr = f;
- mapcache->opaque = opaque;
- qemu_mutex_init(&mapcache->lock);
-
- QTAILQ_INIT(&mapcache->locked_entries);
+ unsigned long max_mcache_size;
if (geteuid() == 0) {
rlimit_as.rlim_cur = RLIM_INFINITY;
rlimit_as.rlim_max = RLIM_INFINITY;
- mapcache->max_mcache_size = MCACHE_MAX_SIZE;
+ max_mcache_size = MCACHE_MAX_SIZE;
} else {
getrlimit(RLIMIT_AS, &rlimit_as);
rlimit_as.rlim_cur = rlimit_as.rlim_max;
@@ -119,27 +140,18 @@
" memory is not infinity");
}
if (rlimit_as.rlim_max < MCACHE_MAX_SIZE + NON_MCACHE_MEMORY_SIZE) {
- mapcache->max_mcache_size = rlimit_as.rlim_max -
- NON_MCACHE_MEMORY_SIZE;
+ max_mcache_size = rlimit_as.rlim_max - NON_MCACHE_MEMORY_SIZE;
} else {
- mapcache->max_mcache_size = MCACHE_MAX_SIZE;
+ max_mcache_size = MCACHE_MAX_SIZE;
}
}
+ mapcache = xen_map_cache_init_single(f, opaque, max_mcache_size);
setrlimit(RLIMIT_AS, &rlimit_as);
-
- mapcache->nr_buckets =
- (((mapcache->max_mcache_size >> XC_PAGE_SHIFT) +
- (1UL << (MCACHE_BUCKET_SHIFT - XC_PAGE_SHIFT)) - 1) >>
- (MCACHE_BUCKET_SHIFT - XC_PAGE_SHIFT));
-
- size = mapcache->nr_buckets * sizeof (MapCacheEntry);
- size = (size + XC_PAGE_SIZE - 1) & ~(XC_PAGE_SIZE - 1);
- trace_xen_map_cache_init(mapcache->nr_buckets, size);
- mapcache->entry = g_malloc0(size);
}
-static void xen_remap_bucket(MapCacheEntry *entry,
+static void xen_remap_bucket(MapCache *mc,
+ MapCacheEntry *entry,
void *vaddr,
hwaddr size,
hwaddr address_index,
@@ -240,8 +252,9 @@
g_free(err);
}
-static uint8_t *xen_map_cache_unlocked(hwaddr phys_addr, hwaddr size,
- uint8_t lock, bool dma)
+static uint8_t *xen_map_cache_unlocked(MapCache *mc,
+ hwaddr phys_addr, hwaddr size,
+ uint8_t lock, bool dma, bool is_write)
{
MapCacheEntry *entry, *pentry = NULL,
*free_entry = NULL, *free_pentry = NULL;
@@ -269,16 +282,16 @@
test_bit_size = XC_PAGE_SIZE;
}
- if (mapcache->last_entry != NULL &&
- mapcache->last_entry->paddr_index == address_index &&
+ if (mc->last_entry != NULL &&
+ mc->last_entry->paddr_index == address_index &&
!lock && !size &&
test_bits(address_offset >> XC_PAGE_SHIFT,
test_bit_size >> XC_PAGE_SHIFT,
- mapcache->last_entry->valid_mapping)) {
+ mc->last_entry->valid_mapping)) {
trace_xen_map_cache_return(
- mapcache->last_entry->vaddr_base + address_offset
+ mc->last_entry->vaddr_base + address_offset
);
- return mapcache->last_entry->vaddr_base + address_offset;
+ return mc->last_entry->vaddr_base + address_offset;
}
/* size is always a multiple of MCACHE_BUCKET_SIZE */
@@ -291,7 +304,7 @@
cache_size = MCACHE_BUCKET_SIZE;
}
- entry = &mapcache->entry[address_index % mapcache->nr_buckets];
+ entry = &mc->entry[address_index % mc->nr_buckets];
while (entry && (lock || entry->lock) && entry->vaddr_base &&
(entry->paddr_index != address_index || entry->size != cache_size ||
@@ -312,24 +325,24 @@
if (!entry) {
entry = g_new0(MapCacheEntry, 1);
pentry->next = entry;
- xen_remap_bucket(entry, NULL, cache_size, address_index, dummy);
+ xen_remap_bucket(mc, entry, NULL, cache_size, address_index, dummy);
} else if (!entry->lock) {
if (!entry->vaddr_base || entry->paddr_index != address_index ||
entry->size != cache_size ||
!test_bits(address_offset >> XC_PAGE_SHIFT,
test_bit_size >> XC_PAGE_SHIFT,
entry->valid_mapping)) {
- xen_remap_bucket(entry, NULL, cache_size, address_index, dummy);
+ xen_remap_bucket(mc, entry, NULL, cache_size, address_index, dummy);
}
}
if(!test_bits(address_offset >> XC_PAGE_SHIFT,
test_bit_size >> XC_PAGE_SHIFT,
entry->valid_mapping)) {
- mapcache->last_entry = NULL;
+ mc->last_entry = NULL;
#ifdef XEN_COMPAT_PHYSMAP
- if (!translated && mapcache->phys_offset_to_gaddr) {
- phys_addr = mapcache->phys_offset_to_gaddr(phys_addr, size);
+ if (!translated && mc->phys_offset_to_gaddr) {
+ phys_addr = mc->phys_offset_to_gaddr(phys_addr, size);
translated = true;
goto tryagain;
}
@@ -342,7 +355,7 @@
return NULL;
}
- mapcache->last_entry = entry;
+ mc->last_entry = entry;
if (lock) {
MapCacheRev *reventry = g_new0(MapCacheRev, 1);
entry->lock++;
@@ -352,30 +365,32 @@
abort();
}
reventry->dma = dma;
- reventry->vaddr_req = mapcache->last_entry->vaddr_base + address_offset;
- reventry->paddr_index = mapcache->last_entry->paddr_index;
+ reventry->vaddr_req = mc->last_entry->vaddr_base + address_offset;
+ reventry->paddr_index = mc->last_entry->paddr_index;
reventry->size = entry->size;
- QTAILQ_INSERT_HEAD(&mapcache->locked_entries, reventry, next);
+ QTAILQ_INSERT_HEAD(&mc->locked_entries, reventry, next);
}
trace_xen_map_cache_return(
- mapcache->last_entry->vaddr_base + address_offset
+ mc->last_entry->vaddr_base + address_offset
);
- return mapcache->last_entry->vaddr_base + address_offset;
+ return mc->last_entry->vaddr_base + address_offset;
}
-uint8_t *xen_map_cache(hwaddr phys_addr, hwaddr size,
- uint8_t lock, bool dma)
+uint8_t *xen_map_cache(MemoryRegion *mr,
+ hwaddr phys_addr, hwaddr size,
+ uint8_t lock, bool dma,
+ bool is_write)
{
uint8_t *p;
- mapcache_lock();
- p = xen_map_cache_unlocked(phys_addr, size, lock, dma);
- mapcache_unlock();
+ mapcache_lock(mapcache);
+ p = xen_map_cache_unlocked(mapcache, phys_addr, size, lock, dma, is_write);
+ mapcache_unlock(mapcache);
return p;
}
-ram_addr_t xen_ram_addr_from_mapcache(void *ptr)
+static ram_addr_t xen_ram_addr_from_mapcache_single(MapCache *mc, void *ptr)
{
MapCacheEntry *entry = NULL;
MapCacheRev *reventry;
@@ -384,8 +399,8 @@
ram_addr_t raddr;
int found = 0;
- mapcache_lock();
- QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) {
+ mapcache_lock(mc);
+ QTAILQ_FOREACH(reventry, &mc->locked_entries, next) {
if (reventry->vaddr_req == ptr) {
paddr_index = reventry->paddr_index;
size = reventry->size;
@@ -395,30 +410,32 @@
}
if (!found) {
trace_xen_ram_addr_from_mapcache_not_found(ptr);
- QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) {
- trace_xen_ram_addr_from_mapcache_found(reventry->paddr_index,
- reventry->vaddr_req);
- }
- abort();
- return 0;
+ mapcache_unlock(mc);
+ return RAM_ADDR_INVALID;
}
- entry = &mapcache->entry[paddr_index % mapcache->nr_buckets];
+ entry = &mc->entry[paddr_index % mc->nr_buckets];
while (entry && (entry->paddr_index != paddr_index || entry->size != size)) {
entry = entry->next;
}
if (!entry) {
trace_xen_ram_addr_from_mapcache_not_in_cache(ptr);
- raddr = 0;
+ raddr = RAM_ADDR_INVALID;
} else {
raddr = (reventry->paddr_index << MCACHE_BUCKET_SHIFT) +
((unsigned long) ptr - (unsigned long) entry->vaddr_base);
}
- mapcache_unlock();
+ mapcache_unlock(mc);
return raddr;
}
-static void xen_invalidate_map_cache_entry_unlocked(uint8_t *buffer)
+ram_addr_t xen_ram_addr_from_mapcache(void *ptr)
+{
+ return xen_ram_addr_from_mapcache_single(mapcache, ptr);
+}
+
+static void xen_invalidate_map_cache_entry_unlocked(MapCache *mc,
+ uint8_t *buffer)
{
MapCacheEntry *entry = NULL, *pentry = NULL;
MapCacheRev *reventry;
@@ -426,7 +443,7 @@
hwaddr size;
int found = 0;
- QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) {
+ QTAILQ_FOREACH(reventry, &mc->locked_entries, next) {
if (reventry->vaddr_req == buffer) {
paddr_index = reventry->paddr_index;
size = reventry->size;
@@ -436,7 +453,7 @@
}
if (!found) {
trace_xen_invalidate_map_cache_entry_unlocked_not_found(buffer);
- QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) {
+ QTAILQ_FOREACH(reventry, &mc->locked_entries, next) {
trace_xen_invalidate_map_cache_entry_unlocked_found(
reventry->paddr_index,
reventry->vaddr_req
@@ -444,15 +461,15 @@
}
return;
}
- QTAILQ_REMOVE(&mapcache->locked_entries, reventry, next);
+ QTAILQ_REMOVE(&mc->locked_entries, reventry, next);
g_free(reventry);
- if (mapcache->last_entry != NULL &&
- mapcache->last_entry->paddr_index == paddr_index) {
- mapcache->last_entry = NULL;
+ if (mc->last_entry != NULL &&
+ mc->last_entry->paddr_index == paddr_index) {
+ mc->last_entry = NULL;
}
- entry = &mapcache->entry[paddr_index % mapcache->nr_buckets];
+ entry = &mc->entry[paddr_index % mc->nr_buckets];
while (entry && (entry->paddr_index != paddr_index || entry->size != size)) {
pentry = entry;
entry = entry->next;
@@ -485,9 +502,9 @@
{
XenMapCacheData *data = opaque;
- mapcache_lock();
- xen_invalidate_map_cache_entry_unlocked(data->buffer);
- mapcache_unlock();
+ mapcache_lock(mapcache);
+ xen_invalidate_map_cache_entry_unlocked(mapcache, data->buffer);
+ mapcache_unlock(mapcache);
aio_co_wake(data->co);
}
@@ -503,23 +520,20 @@
xen_invalidate_map_cache_entry_bh, &data);
qemu_coroutine_yield();
} else {
- mapcache_lock();
- xen_invalidate_map_cache_entry_unlocked(buffer);
- mapcache_unlock();
+ mapcache_lock(mapcache);
+ xen_invalidate_map_cache_entry_unlocked(mapcache, buffer);
+ mapcache_unlock(mapcache);
}
}
-void xen_invalidate_map_cache(void)
+static void xen_invalidate_map_cache_single(MapCache *mc)
{
unsigned long i;
MapCacheRev *reventry;
- /* Flush pending AIO before destroying the mapcache */
- bdrv_drain_all();
+ mapcache_lock(mc);
- mapcache_lock();
-
- QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) {
+ QTAILQ_FOREACH(reventry, &mc->locked_entries, next) {
if (!reventry->dma) {
continue;
}
@@ -527,8 +541,8 @@
reventry->vaddr_req);
}
- for (i = 0; i < mapcache->nr_buckets; i++) {
- MapCacheEntry *entry = &mapcache->entry[i];
+ for (i = 0; i < mc->nr_buckets; i++) {
+ MapCacheEntry *entry = &mc->entry[i];
if (entry->vaddr_base == NULL) {
continue;
@@ -549,12 +563,21 @@
entry->valid_mapping = NULL;
}
- mapcache->last_entry = NULL;
+ mc->last_entry = NULL;
- mapcache_unlock();
+ mapcache_unlock(mc);
}
-static uint8_t *xen_replace_cache_entry_unlocked(hwaddr old_phys_addr,
+void xen_invalidate_map_cache(void)
+{
+ /* Flush pending AIO before destroying the mapcache */
+ bdrv_drain_all();
+
+ xen_invalidate_map_cache_single(mapcache);
+}
+
+static uint8_t *xen_replace_cache_entry_unlocked(MapCache *mc,
+ hwaddr old_phys_addr,
hwaddr new_phys_addr,
hwaddr size)
{
@@ -576,7 +599,7 @@
cache_size += MCACHE_BUCKET_SIZE - (cache_size % MCACHE_BUCKET_SIZE);
}
- entry = &mapcache->entry[address_index % mapcache->nr_buckets];
+ entry = &mc->entry[address_index % mc->nr_buckets];
while (entry && !(entry->paddr_index == address_index &&
entry->size == cache_size)) {
entry = entry->next;
@@ -591,7 +614,7 @@
trace_xen_replace_cache_entry_dummy(old_phys_addr, new_phys_addr);
- xen_remap_bucket(entry, entry->vaddr_base,
+ xen_remap_bucket(mc, entry, entry->vaddr_base,
cache_size, address_index, false);
if (!test_bits(address_offset >> XC_PAGE_SHIFT,
test_bit_size >> XC_PAGE_SHIFT,
@@ -611,8 +634,9 @@
{
uint8_t *p;
- mapcache_lock();
- p = xen_replace_cache_entry_unlocked(old_phys_addr, new_phys_addr, size);
- mapcache_unlock();
+ mapcache_lock(mapcache);
+ p = xen_replace_cache_entry_unlocked(mapcache, old_phys_addr,
+ new_phys_addr, size);
+ mapcache_unlock(mapcache);
return p;
}
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 032c6d9..6f09b86 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -19,6 +19,7 @@
#ifndef CPU_ALL_H
#define CPU_ALL_H
+#include "exec/page-protection.h"
#include "exec/cpu-common.h"
#include "exec/memory.h"
#include "exec/tswap.h"
@@ -139,33 +140,24 @@
#ifdef TARGET_PAGE_BITS_VARY
# include "exec/page-vary.h"
extern const TargetPageBits target_page;
-#ifdef CONFIG_DEBUG_TCG
-#define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; })
-#define TARGET_PAGE_MASK ({ assert(target_page.decided); \
- (target_long)target_page.mask; })
+# ifdef CONFIG_DEBUG_TCG
+# define TARGET_PAGE_BITS ({ assert(target_page.decided); \
+ target_page.bits; })
+# define TARGET_PAGE_MASK ({ assert(target_page.decided); \
+ (target_long)target_page.mask; })
+# else
+# define TARGET_PAGE_BITS target_page.bits
+# define TARGET_PAGE_MASK ((target_long)target_page.mask)
+# endif
+# define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
#else
-#define TARGET_PAGE_BITS target_page.bits
-#define TARGET_PAGE_MASK ((target_long)target_page.mask)
-#endif
-#define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
-#else
-#define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
-#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
-#define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
+# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
+# define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
+# define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
#endif
#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
-#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
-/* FIXME: Code that sets/uses this is broken and needs to go away. */
-#define PAGE_RESERVED 0x0100
-#endif
-/*
- * For linux-user, indicates that the page is mapped with the same semantics
- * in both guest and host.
- */
-#define PAGE_PASSTHROUGH 0x0800
-
#if defined(CONFIG_USER_ONLY)
void page_dump(FILE *f);
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 8812ba7..8bc397e 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -14,6 +14,7 @@
#endif
#include "hw/core/cpu.h"
#include "tcg/debug-assert.h"
+#include "exec/page-protection.h"
#define EXCP_INTERRUPT 0x10000 /* async interruption */
#define EXCP_HLT 0x10001 /* hlt instruction reached */
@@ -177,6 +178,13 @@
void list_cpus(void);
#ifdef CONFIG_TCG
+
+bool tcg_cflags_has(CPUState *cpu, uint32_t flags);
+void tcg_cflags_set(CPUState *cpu, uint32_t flags);
+
+/* current cflags for hashing/comparison */
+uint32_t curr_cflags(CPUState *cpu);
+
/**
* cpu_unwind_state_data:
* @cpu: the cpu context
@@ -208,36 +216,6 @@
G_NORETURN void cpu_loop_exit(CPUState *cpu);
G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
-/* same as PROT_xxx */
-#define PAGE_READ 0x0001
-#define PAGE_WRITE 0x0002
-#define PAGE_EXEC 0x0004
-#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
-#define PAGE_VALID 0x0008
-/*
- * Original state of the write flag (used when tracking self-modifying code)
- */
-#define PAGE_WRITE_ORG 0x0010
-/*
- * Invalidate the TLB entry immediately, helpful for s390x
- * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs()
- */
-#define PAGE_WRITE_INV 0x0020
-/* For use with page_set_flags: page is being replaced; target_data cleared. */
-#define PAGE_RESET 0x0040
-/* For linux-user, indicates that the page is MAP_ANON. */
-#define PAGE_ANON 0x0080
-
-/* Target-specific bits that will be used via page_get_flags(). */
-#define PAGE_TARGET_1 0x0200
-#define PAGE_TARGET_2 0x0400
-
-/*
- * For linux-user, indicates that the page is mapped with the same semantics
- * in both guest and host.
- */
-#define PAGE_PASSTHROUGH 0x0800
-
/* accel/tcg/cpu-exec.c */
int cpu_exec(CPUState *cpu);
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 4c5e470..2cd7b8f 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -510,9 +510,6 @@
#endif
}
-/* current cflags for hashing/comparison */
-uint32_t curr_cflags(CPUState *cpu);
-
/* TranslationBlock invalidate API */
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last);
diff --git a/include/exec/page-protection.h b/include/exec/page-protection.h
new file mode 100644
index 0000000..c43231a
--- /dev/null
+++ b/include/exec/page-protection.h
@@ -0,0 +1,41 @@
+/*
+ * QEMU page protection definitions.
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+#ifndef EXEC_PAGE_PROT_COMMON_H
+#define EXEC_PAGE_PROT_COMMON_H
+
+/* same as PROT_xxx */
+#define PAGE_READ 0x0001
+#define PAGE_WRITE 0x0002
+#define PAGE_EXEC 0x0004
+#define PAGE_RWX (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
+#define PAGE_VALID 0x0008
+/*
+ * Original state of the write flag (used when tracking self-modifying code)
+ */
+#define PAGE_WRITE_ORG 0x0010
+/*
+ * Invalidate the TLB entry immediately, helpful for s390x
+ * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs()
+ */
+#define PAGE_WRITE_INV 0x0020
+/* For use with page_set_flags: page is being replaced; target_data cleared. */
+#define PAGE_RESET 0x0040
+/* For linux-user, indicates that the page is MAP_ANON. */
+#define PAGE_ANON 0x0080
+
+/* Target-specific bits that will be used via page_get_flags(). */
+#define PAGE_TARGET_1 0x0200
+#define PAGE_TARGET_2 0x0400
+
+/*
+ * For linux-user, indicates that the page is mapped with the same semantics
+ * in both guest and host.
+ */
+#define PAGE_PASSTHROUGH 0x0800
+
+#endif
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 1382a98..bb398e8 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -345,12 +345,20 @@
} u16;
} IcountDecr;
-/*
- * Elements of CPUState most efficiently accessed from CPUArchState,
- * via small negative offsets.
+/**
+ * CPUNegativeOffsetState: Elements of CPUState most efficiently accessed
+ * from CPUArchState, via small negative offsets.
+ * @can_do_io: True if memory-mapped IO is allowed.
+ * @plugin_mem_cbs: active plugin memory callbacks
*/
typedef struct CPUNegativeOffsetState {
CPUTLB tlb;
+#ifdef CONFIG_PLUGIN
+ /*
+ * The callback pointer are accessed via TCG (see gen_empty_mem_helper).
+ */
+ GArray *plugin_mem_cbs;
+#endif
IcountDecr icount_decr;
bool can_do_io;
} CPUNegativeOffsetState;
@@ -407,7 +415,6 @@
* @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
* @singlestep_enabled: Flags for single-stepping.
* @icount_extra: Instructions until next timer event.
- * @neg.can_do_io: True if memory-mapped IO is allowed.
* @cpu_ases: Pointer to array of CPUAddressSpaces (which define the
* AddressSpaces this CPU has)
* @num_ases: number of CPUAddressSpaces in @cpu_ases
@@ -423,7 +430,6 @@
* @kvm_fd: vCPU file descriptor for KVM.
* @work_mutex: Lock to prevent multiple access to @work_list.
* @work_list: List of pending asynchronous work.
- * @plugin_mem_cbs: active plugin memory callbacks
* @plugin_state: per-CPU plugin state
* @ignore_memory_transaction_failures: Cached copy of the MachineState
* flag of the same name: allows the board to suppress calling of the
@@ -518,11 +524,6 @@
QemuLockCnt in_ioctl_lock;
#ifdef CONFIG_PLUGIN
- /*
- * The callback pointer stays in the main CPUState as it is
- * accessed via TCG (see gen_empty_mem_helper).
- */
- GArray *plugin_mem_cbs;
CPUPluginState *plugin_state;
#endif
@@ -1119,23 +1120,6 @@
#endif
/**
- * cpu_plugin_mem_cbs_enabled() - are plugin memory callbacks enabled?
- * @cs: CPUState pointer
- *
- * The memory callbacks are installed if a plugin has instrumented an
- * instruction for memory. This can be useful to know if you want to
- * force a slow path for a series of memory accesses.
- */
-static inline bool cpu_plugin_mem_cbs_enabled(const CPUState *cpu)
-{
-#ifdef CONFIG_PLUGIN
- return !!cpu->plugin_mem_cbs;
-#else
- return false;
-#endif
-}
-
-/**
* cpu_get_address_space:
* @cpu: CPU to get address space from
* @asidx: index identifying which address space to get
diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h
index 1806252..b535bfd 100644
--- a/include/qemu/plugin.h
+++ b/include/qemu/plugin.h
@@ -180,7 +180,7 @@
static inline void qemu_plugin_disable_mem_helpers(CPUState *cpu)
{
- cpu->plugin_mem_cbs = NULL;
+ cpu->neg.plugin_mem_cbs = NULL;
}
/**
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index 2ff50bf..b47e717 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -110,6 +110,7 @@
typedef struct SSIBus SSIBus;
typedef struct TCGCPUOps TCGCPUOps;
typedef struct TCGHelperInfo TCGHelperInfo;
+typedef struct TaskState TaskState;
typedef struct TranslationBlock TranslationBlock;
typedef struct VirtIODevice VirtIODevice;
typedef struct Visitor Visitor;
diff --git a/include/semihosting/uaccess.h b/include/semihosting/uaccess.h
index dd289af..c2fa5a6 100644
--- a/include/semihosting/uaccess.h
+++ b/include/semihosting/uaccess.h
@@ -17,6 +17,7 @@
#include "exec/cpu-common.h"
#include "exec/cpu-defs.h"
#include "exec/tswap.h"
+#include "exec/page-protection.h"
#define get_user_u64(val, addr) \
({ uint64_t val_ = 0; \
diff --git a/include/sysemu/xen-mapcache.h b/include/sysemu/xen-mapcache.h
index 10c2e30..1ec9e66 100644
--- a/include/sysemu/xen-mapcache.h
+++ b/include/sysemu/xen-mapcache.h
@@ -18,8 +18,9 @@
void xen_map_cache_init(phys_offset_to_gaddr_t f,
void *opaque);
-uint8_t *xen_map_cache(hwaddr phys_addr, hwaddr size,
- uint8_t lock, bool dma);
+uint8_t *xen_map_cache(MemoryRegion *mr, hwaddr phys_addr, hwaddr size,
+ uint8_t lock, bool dma,
+ bool is_write);
ram_addr_t xen_ram_addr_from_mapcache(void *ptr);
void xen_invalidate_map_cache_entry(uint8_t *buffer);
void xen_invalidate_map_cache(void);
@@ -33,10 +34,12 @@
{
}
-static inline uint8_t *xen_map_cache(hwaddr phys_addr,
+static inline uint8_t *xen_map_cache(MemoryRegion *mr,
+ hwaddr phys_addr,
hwaddr size,
uint8_t lock,
- bool dma)
+ bool dma,
+ bool is_write)
{
abort();
}
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
index db1a41e..ec66586 100644
--- a/linux-user/arm/cpu_loop.c
+++ b/linux-user/arm/cpu_loop.c
@@ -24,6 +24,7 @@
#include "cpu_loop-common.h"
#include "signal-common.h"
#include "semihosting/common-semi.h"
+#include "exec/page-protection.h"
#include "target/arm/syndrome.h"
#define get_user_code_u32(x, gaddr, env) \
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index f9461d2..b473cda 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -8,6 +8,7 @@
#include "qemu.h"
#include "user/tswap-target.h"
+#include "exec/page-protection.h"
#include "user/guest-base.h"
#include "user-internals.h"
#include "signal-common.h"
@@ -968,24 +969,44 @@
#endif /* TARGET_ARM */
#ifdef TARGET_SPARC
-#ifdef TARGET_SPARC64
-#define ELF_HWCAP (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | HWCAP_SPARC_SWAP \
- | HWCAP_SPARC_MULDIV | HWCAP_SPARC_V9)
-#ifndef TARGET_ABI32
-#define elf_check_arch(x) ( (x) == EM_SPARCV9 || (x) == EM_SPARC32PLUS )
+#ifndef TARGET_SPARC64
+# define ELF_CLASS ELFCLASS32
+# define ELF_ARCH EM_SPARC
+#elif defined(TARGET_ABI32)
+# define ELF_CLASS ELFCLASS32
+# define elf_check_arch(x) ((x) == EM_SPARC32PLUS || (x) == EM_SPARC)
#else
-#define elf_check_arch(x) ( (x) == EM_SPARC32PLUS || (x) == EM_SPARC )
+# define ELF_CLASS ELFCLASS64
+# define ELF_ARCH EM_SPARCV9
#endif
-#define ELF_CLASS ELFCLASS64
-#define ELF_ARCH EM_SPARCV9
-#else
-#define ELF_HWCAP (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | HWCAP_SPARC_SWAP \
- | HWCAP_SPARC_MULDIV)
-#define ELF_CLASS ELFCLASS32
-#define ELF_ARCH EM_SPARC
-#endif /* TARGET_SPARC64 */
+#include "elf.h"
+
+#define ELF_HWCAP get_elf_hwcap()
+
+static uint32_t get_elf_hwcap(void)
+{
+ /* There are not many sparc32 hwcap bits -- we have all of them. */
+ uint32_t r = HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
+ HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV;
+
+#ifdef TARGET_SPARC64
+ CPUSPARCState *env = cpu_env(thread_cpu);
+ uint32_t features = env->def.features;
+
+ r |= HWCAP_SPARC_V9 | HWCAP_SPARC_V8PLUS;
+ /* 32x32 multiply and divide are efficient. */
+ r |= HWCAP_SPARC_MUL32 | HWCAP_SPARC_DIV32;
+ /* We don't have an internal feature bit for this. */
+ r |= HWCAP_SPARC_POPC;
+ r |= features & CPU_FEATURE_FSMULD ? HWCAP_SPARC_FSMULD : 0;
+ r |= features & CPU_FEATURE_VIS1 ? HWCAP_SPARC_VIS : 0;
+ r |= features & CPU_FEATURE_VIS2 ? HWCAP_SPARC_VIS2 : 0;
+#endif
+
+ return r;
+}
static inline void init_thread(struct target_pt_regs *regs,
struct image_info *infop)
@@ -2361,7 +2382,7 @@
if (start_bss < align_bss) {
int flags = page_get_flags(start_bss);
- if (!(flags & PAGE_BITS)) {
+ if (!(flags & PAGE_RWX)) {
/*
* The whole address space of the executable was reserved
* at the start, therefore all pages will be VALID.
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
index be3b9a6..4d09a72 100644
--- a/linux-user/mmap.c
+++ b/linux-user/mmap.c
@@ -20,6 +20,7 @@
#include <sys/shm.h>
#include "trace.h"
#include "exec/log.h"
+#include "exec/page-protection.h"
#include "qemu.h"
#include "user-internals.h"
#include "user-mmap.h"
@@ -117,7 +118,7 @@
static int validate_prot_to_pageflags(int prot)
{
int valid = PROT_READ | PROT_WRITE | PROT_EXEC | TARGET_PROT_SEM;
- int page_flags = (prot & PAGE_BITS) | PAGE_VALID;
+ int page_flags = (prot & PAGE_RWX) | PAGE_VALID;
#ifdef TARGET_AARCH64
{
@@ -959,8 +960,8 @@
*/
if (ret != -1 && (flags & MAP_TYPE) != MAP_PRIVATE) {
CPUState *cpu = thread_cpu;
- if (!(cpu->tcg_cflags & CF_PARALLEL)) {
- cpu->tcg_cflags |= CF_PARALLEL;
+ if (!tcg_cflags_has(cpu, CF_PARALLEL)) {
+ tcg_cflags_set(cpu, CF_PARALLEL);
tb_flush(cpu);
}
}
@@ -1399,8 +1400,8 @@
* supported by the host -- anything that requires EXCP_ATOMIC will not
* be atomic with respect to an external process.
*/
- if (!(cpu->tcg_cflags & CF_PARALLEL)) {
- cpu->tcg_cflags |= CF_PARALLEL;
+ if (!tcg_cflags_has(cpu, CF_PARALLEL)) {
+ tcg_cflags_set(cpu, CF_PARALLEL);
tb_flush(cpu);
}
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
index 263f445..2e90a97 100644
--- a/linux-user/qemu.h
+++ b/linux-user/qemu.h
@@ -8,6 +8,7 @@
#include "syscall_defs.h"
#include "target_syscall.h"
+#include "accel/tcg/vcpu-state.h"
/*
* This is the size of the host kernel's sigset_t, needed where we make
@@ -95,7 +96,7 @@
target_siginfo_t info;
};
-typedef struct TaskState {
+struct TaskState {
pid_t ts_tid; /* tid (or pid) of this task */
#ifdef TARGET_ARM
# ifdef TARGET_ABI32
@@ -158,12 +159,7 @@
/* Start time of task after system boot in clock ticks */
uint64_t start_boottime;
-} TaskState;
-
-static inline TaskState *get_task_state(CPUState *cs)
-{
- return cs->opaque;
-}
+};
abi_long do_brk(abi_ulong new_brk);
int do_guest_openat(CPUArchState *cpu_env, int dirfd, const char *pathname,
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 05dc4af..63ac2df 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "qemu/bitops.h"
#include "gdbstub/user.h"
+#include "exec/page-protection.h"
#include "hw/core/tcg-cpu-ops.h"
#include <sys/ucontext.h>
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 41659b6..b9b5a38 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -25,6 +25,7 @@
#include "qemu/plugin.h"
#include "tcg/startup.h"
#include "target_mman.h"
+#include "exec/page-protection.h"
#include <elf.h>
#include <endian.h>
#include <grp.h>
@@ -6462,7 +6463,7 @@
case PR_GET_TID_ADDRESS:
{
- TaskState *ts = env_cpu(env)->opaque;
+ TaskState *ts = get_task_state(env_cpu(env));
return put_user_ual(ts->child_tidptr, arg2);
}
@@ -6582,8 +6583,8 @@
* generate code for parallel execution and flush old translations.
* Do this now so that the copy gets CF_PARALLEL too.
*/
- if (!(cpu->tcg_cflags & CF_PARALLEL)) {
- cpu->tcg_cflags |= CF_PARALLEL;
+ if (!tcg_cflags_has(cpu, CF_PARALLEL)) {
+ tcg_cflags_set(cpu, CF_PARALLEL);
tb_flush(cpu);
}
@@ -8123,7 +8124,7 @@
static int open_self_maps_1(CPUArchState *env, int fd, bool smaps)
{
struct open_self_maps_data d = {
- .ts = env_cpu(env)->opaque,
+ .ts = get_task_state(env_cpu(env)),
.host_maps = read_self_maps(),
.fd = fd,
.smaps = smaps
diff --git a/plugins/core.c b/plugins/core.c
index 081323d..1e58a57 100644
--- a/plugins/core.c
+++ b/plugins/core.c
@@ -533,7 +533,7 @@
void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr,
MemOpIdx oi, enum qemu_plugin_mem_rw rw)
{
- GArray *arr = cpu->plugin_mem_cbs;
+ GArray *arr = cpu->neg.plugin_mem_cbs;
size_t i;
if (arr == NULL) {
diff --git a/qom/object.c b/qom/object.c
index 44ec8f6..157a45c 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -157,14 +157,6 @@
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
"0123456789-_.");
- /* Allow some legacy names with '+' in it for compatibility reasons */
- if (name[plen] == '+') {
- if (plen >= 17 && g_str_has_prefix(name, "Sun-UltraSparc-I")) {
- /* Allow "Sun-UltraSparc-IV+" and "Sun-UltraSparc-IIIi+" */
- return true;
- }
- }
-
return plen == slen;
}
diff --git a/scripts/qapi/commands.py b/scripts/qapi/commands.py
index d1fdf41..79951a8 100644
--- a/scripts/qapi/commands.py
+++ b/scripts/qapi/commands.py
@@ -64,7 +64,7 @@
assert arg_type
argstr = '&arg, '
elif arg_type:
- assert not arg_type.variants
+ assert not arg_type.branches
for memb in arg_type.members:
assert not memb.ifcond.is_present()
if memb.need_has():
diff --git a/scripts/qapi/events.py b/scripts/qapi/events.py
index 3cf01e9..d1f6399 100644
--- a/scripts/qapi/events.py
+++ b/scripts/qapi/events.py
@@ -51,7 +51,7 @@
Initialize it with the function arguments defined in `gen_event_send`.
"""
- assert not typ.variants
+ assert not typ.branches
ret = mcgen('''
%(c_name)s param = {
''',
diff --git a/scripts/qapi/gen.py b/scripts/qapi/gen.py
index 5412716..6a8abe0 100644
--- a/scripts/qapi/gen.py
+++ b/scripts/qapi/gen.py
@@ -118,7 +118,7 @@
ret += '%s arg' % arg_type.c_param_type()
sep = ', '
elif arg_type:
- assert not arg_type.variants
+ assert not arg_type.branches
for memb in arg_type.members:
assert not memb.ifcond.is_present()
ret += sep
diff --git a/scripts/qapi/introspect.py b/scripts/qapi/introspect.py
index 4679b1b..86c075a 100644
--- a/scripts/qapi/introspect.py
+++ b/scripts/qapi/introspect.py
@@ -26,6 +26,8 @@
from .gen import QAPISchemaMonolithicCVisitor
from .schema import (
QAPISchema,
+ QAPISchemaAlternatives,
+ QAPISchemaBranches,
QAPISchemaArrayType,
QAPISchemaBuiltinType,
QAPISchemaEntity,
@@ -36,7 +38,6 @@
QAPISchemaObjectTypeMember,
QAPISchemaType,
QAPISchemaVariant,
- QAPISchemaVariants,
)
from .source import QAPISourceInfo
@@ -335,24 +336,24 @@
ifcond: QAPISchemaIfCond,
features: List[QAPISchemaFeature],
members: List[QAPISchemaObjectTypeMember],
- variants: Optional[QAPISchemaVariants]) -> None:
+ branches: Optional[QAPISchemaBranches]) -> None:
obj: SchemaInfoObject = {
'members': [self._gen_object_member(m) for m in members]
}
- if variants:
- obj['tag'] = variants.tag_member.name
- obj['variants'] = [self._gen_variant(v) for v in variants.variants]
+ if branches:
+ obj['tag'] = branches.tag_member.name
+ obj['variants'] = [self._gen_variant(v) for v in branches.variants]
self._gen_tree(name, 'object', obj, ifcond, features)
def visit_alternate_type(self, name: str, info: Optional[QAPISourceInfo],
ifcond: QAPISchemaIfCond,
features: List[QAPISchemaFeature],
- variants: QAPISchemaVariants) -> None:
+ alternatives: QAPISchemaAlternatives) -> None:
self._gen_tree(
name, 'alternate',
{'members': [Annotated({'type': self._use_type(m.type)},
m.ifcond)
- for m in variants.variants]},
+ for m in alternatives.variants]},
ifcond, features
)
diff --git a/scripts/qapi/schema.py b/scripts/qapi/schema.py
index 5924947..721c470 100644
--- a/scripts/qapi/schema.py
+++ b/scripts/qapi/schema.py
@@ -215,7 +215,7 @@
features: List[QAPISchemaFeature],
base: Optional[QAPISchemaObjectType],
members: List[QAPISchemaObjectTypeMember],
- variants: Optional[QAPISchemaVariants],
+ branches: Optional[QAPISchemaBranches],
) -> None:
pass
@@ -226,7 +226,7 @@
ifcond: QAPISchemaIfCond,
features: List[QAPISchemaFeature],
members: List[QAPISchemaObjectTypeMember],
- variants: Optional[QAPISchemaVariants],
+ branches: Optional[QAPISchemaBranches],
) -> None:
pass
@@ -236,7 +236,7 @@
info: Optional[QAPISourceInfo],
ifcond: QAPISchemaIfCond,
features: List[QAPISchemaFeature],
- variants: QAPISchemaVariants,
+ alternatives: QAPISchemaAlternatives,
) -> None:
pass
@@ -524,20 +524,20 @@
features: Optional[List[QAPISchemaFeature]],
base: Optional[str],
local_members: List[QAPISchemaObjectTypeMember],
- variants: Optional[QAPISchemaVariants],
+ branches: Optional[QAPISchemaBranches],
):
- # struct has local_members, optional base, and no variants
- # union has base, variants, and no local_members
+ # struct has local_members, optional base, and no branches
+ # union has base, branches, and no local_members
super().__init__(name, info, doc, ifcond, features)
- self.meta = 'union' if variants else 'struct'
+ self.meta = 'union' if branches else 'struct'
for m in local_members:
m.set_defined_in(name)
- if variants is not None:
- variants.set_defined_in(name)
+ if branches is not None:
+ branches.set_defined_in(name)
self._base_name = base
self.base = None
self.local_members = local_members
- self.variants = variants
+ self.branches = branches
self.members: List[QAPISchemaObjectTypeMember]
self._check_complete = False
@@ -561,7 +561,7 @@
self.base = schema.resolve_type(self._base_name, self.info,
"'base'")
if (not isinstance(self.base, QAPISchemaObjectType)
- or self.base.variants):
+ or self.base.branches):
raise QAPISemError(
self.info,
"'base' requires a struct type, %s isn't"
@@ -577,9 +577,9 @@
# Cast down to the subtype.
members = cast(List[QAPISchemaObjectTypeMember], list(seen.values()))
- if self.variants:
- self.variants.check(schema, seen)
- self.variants.check_clash(self.info, seen)
+ if self.branches:
+ self.branches.check(schema, seen)
+ self.branches.check_clash(self.info, seen)
self.members = members
self._check_complete = True # mark completed
@@ -595,8 +595,8 @@
assert self._checked
for m in self.members:
m.check_clash(info, seen)
- if self.variants:
- self.variants.check_clash(info, seen)
+ if self.branches:
+ self.branches.check_clash(info, seen)
def connect_doc(self, doc: Optional[QAPIDoc] = None) -> None:
super().connect_doc(doc)
@@ -612,7 +612,7 @@
return self.name.startswith('q_')
def is_empty(self) -> bool:
- return not self.members and not self.variants
+ return not self.members and not self.branches
def has_conditional_members(self) -> bool:
return any(m.ifcond.is_present() for m in self.members)
@@ -635,10 +635,10 @@
super().visit(visitor)
visitor.visit_object_type(
self.name, self.info, self.ifcond, self.features,
- self.base, self.local_members, self.variants)
+ self.base, self.local_members, self.branches)
visitor.visit_object_type_flat(
self.name, self.info, self.ifcond, self.features,
- self.members, self.variants)
+ self.members, self.branches)
class QAPISchemaAlternateType(QAPISchemaType):
@@ -651,25 +651,25 @@
doc: Optional[QAPIDoc],
ifcond: Optional[QAPISchemaIfCond],
features: List[QAPISchemaFeature],
- variants: QAPISchemaVariants,
+ alternatives: QAPISchemaAlternatives,
):
super().__init__(name, info, doc, ifcond, features)
- assert variants.tag_member
- variants.set_defined_in(name)
- variants.tag_member.set_defined_in(self.name)
- self.variants = variants
+ assert alternatives.tag_member
+ alternatives.set_defined_in(name)
+ alternatives.tag_member.set_defined_in(self.name)
+ self.alternatives = alternatives
def check(self, schema: QAPISchema) -> None:
super().check(schema)
- self.variants.tag_member.check(schema)
- # Not calling self.variants.check_clash(), because there's nothing
- # to clash with
- self.variants.check(schema, {})
+ self.alternatives.tag_member.check(schema)
+ # Not calling self.alternatives.check_clash(), because there's
+ # nothing to clash with
+ self.alternatives.check(schema, {})
# Alternate branch names have no relation to the tag enum values;
# so we have to check for potential name collisions ourselves.
seen: Dict[str, QAPISchemaMember] = {}
types_seen: Dict[str, str] = {}
- for v in self.variants.variants:
+ for v in self.alternatives.variants:
v.check_clash(self.info, seen)
qtype = v.type.alternate_qtype()
if not qtype:
@@ -700,7 +700,7 @@
def connect_doc(self, doc: Optional[QAPIDoc] = None) -> None:
super().connect_doc(doc)
doc = doc or self.doc
- for v in self.variants.variants:
+ for v in self.alternatives.variants:
v.connect_doc(doc)
def c_type(self) -> str:
@@ -712,94 +712,86 @@
def visit(self, visitor: QAPISchemaVisitor) -> None:
super().visit(visitor)
visitor.visit_alternate_type(
- self.name, self.info, self.ifcond, self.features, self.variants)
+ self.name, self.info, self.ifcond, self.features,
+ self.alternatives)
class QAPISchemaVariants:
def __init__(
self,
- tag_name: Optional[str],
info: QAPISourceInfo,
- tag_member: Optional[QAPISchemaObjectTypeMember],
variants: List[QAPISchemaVariant],
):
- # Unions pass tag_name but not tag_member.
- # Alternates pass tag_member but not tag_name.
- # After check(), tag_member is always set.
- assert bool(tag_member) != bool(tag_name)
- assert (isinstance(tag_name, str) or
- isinstance(tag_member, QAPISchemaObjectTypeMember))
- self._tag_name = tag_name
self.info = info
- self._tag_member = tag_member
+ self.tag_member: QAPISchemaObjectTypeMember
self.variants = variants
- @property
- def tag_member(self) -> QAPISchemaObjectTypeMember:
- if self._tag_member is None:
- raise RuntimeError(
- "QAPISchemaVariants has no tag_member property until "
- "after check() has been run."
- )
- return self._tag_member
-
def set_defined_in(self, name: str) -> None:
for v in self.variants:
v.set_defined_in(name)
def check(
- self, schema: QAPISchema, seen: Dict[str, QAPISchemaMember]
+ self, schema: QAPISchema, seen: Dict[str, QAPISchemaMember]
) -> None:
- if self._tag_name: # union
- # We need to narrow the member type:
- tmp = seen.get(c_name(self._tag_name))
- assert tmp is None or isinstance(tmp, QAPISchemaObjectTypeMember)
- self._tag_member = tmp
+ for v in self.variants:
+ v.check(schema)
- base = "'base'"
- # Pointing to the base type when not implicit would be
- # nice, but we don't know it here
- if not self._tag_member or self._tag_name != self._tag_member.name:
- raise QAPISemError(
- self.info,
- "discriminator '%s' is not a member of %s"
- % (self._tag_name, base))
- # Here we do:
- assert self.tag_member.defined_in
- base_type = schema.lookup_type(self.tag_member.defined_in)
- assert base_type
- if not base_type.is_implicit():
- base = "base type '%s'" % self.tag_member.defined_in
- if not isinstance(self.tag_member.type, QAPISchemaEnumType):
- raise QAPISemError(
- self.info,
- "discriminator member '%s' of %s must be of enum type"
- % (self._tag_name, base))
- if self.tag_member.optional:
- raise QAPISemError(
- self.info,
- "discriminator member '%s' of %s must not be optional"
- % (self._tag_name, base))
- if self.tag_member.ifcond.is_present():
- raise QAPISemError(
- self.info,
- "discriminator member '%s' of %s must not be conditional"
- % (self._tag_name, base))
- else: # alternate
- assert self._tag_member
- assert isinstance(self.tag_member.type, QAPISchemaEnumType)
- assert not self.tag_member.optional
- assert not self.tag_member.ifcond.is_present()
- if self._tag_name: # union
- # branches that are not explicitly covered get an empty type
- assert self.tag_member.defined_in
- cases = {v.name for v in self.variants}
- for m in self.tag_member.type.members:
- if m.name not in cases:
- v = QAPISchemaVariant(m.name, self.info,
- 'q_empty', m.ifcond)
- v.set_defined_in(self.tag_member.defined_in)
- self.variants.append(v)
+
+class QAPISchemaBranches(QAPISchemaVariants):
+ def __init__(self,
+ info: QAPISourceInfo,
+ variants: List[QAPISchemaVariant],
+ tag_name: str):
+ super().__init__(info, variants)
+ self._tag_name = tag_name
+
+ def check(
+ self, schema: QAPISchema, seen: Dict[str, QAPISchemaMember]
+ ) -> None:
+ # We need to narrow the member type:
+ tag_member = seen.get(c_name(self._tag_name))
+ assert (tag_member is None
+ or isinstance(tag_member, QAPISchemaObjectTypeMember))
+
+ base = "'base'"
+ # Pointing to the base type when not implicit would be
+ # nice, but we don't know it here
+ if not tag_member or self._tag_name != tag_member.name:
+ raise QAPISemError(
+ self.info,
+ "discriminator '%s' is not a member of %s"
+ % (self._tag_name, base))
+ self.tag_member = tag_member
+ # Here we do:
+ assert tag_member.defined_in
+ base_type = schema.lookup_type(tag_member.defined_in)
+ assert base_type
+ if not base_type.is_implicit():
+ base = "base type '%s'" % tag_member.defined_in
+ if not isinstance(tag_member.type, QAPISchemaEnumType):
+ raise QAPISemError(
+ self.info,
+ "discriminator member '%s' of %s must be of enum type"
+ % (self._tag_name, base))
+ if tag_member.optional:
+ raise QAPISemError(
+ self.info,
+ "discriminator member '%s' of %s must not be optional"
+ % (self._tag_name, base))
+ if tag_member.ifcond.is_present():
+ raise QAPISemError(
+ self.info,
+ "discriminator member '%s' of %s must not be conditional"
+ % (self._tag_name, base))
+ # branches that are not explicitly covered get an empty type
+ assert tag_member.defined_in
+ cases = {v.name for v in self.variants}
+ for m in tag_member.type.members:
+ if m.name not in cases:
+ v = QAPISchemaVariant(m.name, self.info,
+ 'q_empty', m.ifcond)
+ v.set_defined_in(tag_member.defined_in)
+ self.variants.append(v)
if not self.variants:
raise QAPISemError(self.info, "union has no branches")
for v in self.variants:
@@ -807,11 +799,11 @@
# Union names must match enum values; alternate names are
# checked separately. Use 'seen' to tell the two apart.
if seen:
- if v.name not in self.tag_member.type.member_names():
+ if v.name not in tag_member.type.member_names():
raise QAPISemError(
self.info,
"branch '%s' is not a value of %s"
- % (v.name, self.tag_member.type.describe()))
+ % (v.name, tag_member.type.describe()))
if not isinstance(v.type, QAPISchemaObjectType):
raise QAPISemError(
self.info,
@@ -833,6 +825,23 @@
v.type.check_clash(info, dict(seen))
+class QAPISchemaAlternatives(QAPISchemaVariants):
+ def __init__(self,
+ info: QAPISourceInfo,
+ variants: List[QAPISchemaVariant],
+ tag_member: QAPISchemaObjectTypeMember):
+ super().__init__(info, variants)
+ self.tag_member = tag_member
+
+ def check(
+ self, schema: QAPISchema, seen: Dict[str, QAPISchemaMember]
+ ) -> None:
+ super().check(schema, seen)
+ assert isinstance(self.tag_member.type, QAPISchemaEnumType)
+ assert not self.tag_member.optional
+ assert not self.tag_member.ifcond.is_present()
+
+
class QAPISchemaMember:
""" Represents object members, enum members and features """
role = 'member'
@@ -1019,7 +1028,7 @@
"command's 'data' cannot take %s"
% arg_type.describe())
self.arg_type = arg_type
- if self.arg_type.variants and not self.boxed:
+ if self.arg_type.branches and not self.boxed:
raise QAPISemError(
self.info,
"command's 'data' can take %s only with 'boxed': true"
@@ -1087,7 +1096,7 @@
"event's 'data' cannot take %s"
% typ.describe())
self.arg_type = typ
- if self.arg_type.variants and not self.boxed:
+ if self.arg_type.branches and not self.boxed:
raise QAPISemError(
self.info,
"event's 'data' can take %s only with 'boxed': true"
@@ -1388,8 +1397,8 @@
self._def_definition(
QAPISchemaObjectType(name, info, expr.doc, ifcond, features,
base, members,
- QAPISchemaVariants(
- tag_name, info, None, variants)))
+ QAPISchemaBranches(
+ info, variants, tag_name)))
def _def_alternate_type(self, expr: QAPIExpression) -> None:
name = expr['alternate']
@@ -1407,7 +1416,7 @@
self._def_definition(
QAPISchemaAlternateType(
name, info, expr.doc, ifcond, features,
- QAPISchemaVariants(None, info, tag_member, variants)))
+ QAPISchemaAlternatives(info, variants, tag_member)))
def _def_command(self, expr: QAPIExpression) -> None:
name = expr['command']
diff --git a/scripts/qapi/types.py b/scripts/qapi/types.py
index c39d054..0dd0b00 100644
--- a/scripts/qapi/types.py
+++ b/scripts/qapi/types.py
@@ -23,6 +23,8 @@
)
from .schema import (
QAPISchema,
+ QAPISchemaAlternatives,
+ QAPISchemaBranches,
QAPISchemaEnumMember,
QAPISchemaFeature,
QAPISchemaIfCond,
@@ -169,7 +171,7 @@
if not isinstance(obj, QAPISchemaObjectType):
continue
ret += gen_object(obj.name, obj.ifcond, obj.base,
- obj.local_members, obj.variants)
+ obj.local_members, obj.branches)
ret += mcgen('''
@@ -348,13 +350,13 @@
features: List[QAPISchemaFeature],
base: Optional[QAPISchemaObjectType],
members: List[QAPISchemaObjectTypeMember],
- variants: Optional[QAPISchemaVariants]) -> None:
+ branches: Optional[QAPISchemaBranches]) -> None:
# Nothing to do for the special empty builtin
if name == 'q_empty':
return
with ifcontext(ifcond, self._genh):
self._genh.preamble_add(gen_fwd_object_or_array(name))
- self._genh.add(gen_object(name, ifcond, base, members, variants))
+ self._genh.add(gen_object(name, ifcond, base, members, branches))
with ifcontext(ifcond, self._genh, self._genc):
if base and not base.is_implicit():
self._genh.add(gen_upcast(name, base))
@@ -369,11 +371,11 @@
info: Optional[QAPISourceInfo],
ifcond: QAPISchemaIfCond,
features: List[QAPISchemaFeature],
- variants: QAPISchemaVariants) -> None:
+ alternatives: QAPISchemaAlternatives) -> None:
with ifcontext(ifcond, self._genh):
self._genh.preamble_add(gen_fwd_object_or_array(name))
self._genh.add(gen_object(name, ifcond, None,
- [variants.tag_member], variants))
+ [alternatives.tag_member], alternatives))
with ifcontext(ifcond, self._genh, self._genc):
self._gen_type_cleanup(name)
diff --git a/scripts/qapi/visit.py b/scripts/qapi/visit.py
index a21b7b1..e766aca 100644
--- a/scripts/qapi/visit.py
+++ b/scripts/qapi/visit.py
@@ -28,6 +28,8 @@
)
from .schema import (
QAPISchema,
+ QAPISchemaAlternatives,
+ QAPISchemaBranches,
QAPISchemaEnumMember,
QAPISchemaEnumType,
QAPISchemaFeature,
@@ -35,7 +37,6 @@
QAPISchemaObjectType,
QAPISchemaObjectTypeMember,
QAPISchemaType,
- QAPISchemaVariants,
)
from .source import QAPISourceInfo
@@ -63,7 +64,7 @@
def gen_visit_object_members(name: str,
base: Optional[QAPISchemaObjectType],
members: List[QAPISchemaObjectTypeMember],
- variants: Optional[QAPISchemaVariants]) -> str:
+ branches: Optional[QAPISchemaBranches]) -> str:
ret = mcgen('''
bool visit_type_%(c_name)s_members(Visitor *v, %(c_name)s *obj, Error **errp)
@@ -131,8 +132,8 @@
''')
ret += memb.ifcond.gen_endif()
- if variants:
- tag_member = variants.tag_member
+ if branches:
+ tag_member = branches.tag_member
assert isinstance(tag_member.type, QAPISchemaEnumType)
ret += mcgen('''
@@ -140,7 +141,7 @@
''',
c_name=c_name(tag_member.name))
- for var in variants.variants:
+ for var in branches.variants:
case_str = c_enum_const(tag_member.type.name, var.name,
tag_member.type.prefix)
ret += var.ifcond.gen_if()
@@ -222,7 +223,8 @@
c_name=c_name(name))
-def gen_visit_alternate(name: str, variants: QAPISchemaVariants) -> str:
+def gen_visit_alternate(name: str,
+ alternatives: QAPISchemaAlternatives) -> str:
ret = mcgen('''
bool visit_type_%(c_name)s(Visitor *v, const char *name,
@@ -244,7 +246,7 @@
''',
c_name=c_name(name))
- for var in variants.variants:
+ for var in alternatives.variants:
ret += var.ifcond.gen_if()
ret += mcgen('''
case %(case)s:
@@ -393,14 +395,14 @@
features: List[QAPISchemaFeature],
base: Optional[QAPISchemaObjectType],
members: List[QAPISchemaObjectTypeMember],
- variants: Optional[QAPISchemaVariants]) -> None:
+ branches: Optional[QAPISchemaBranches]) -> None:
# Nothing to do for the special empty builtin
if name == 'q_empty':
return
with ifcontext(ifcond, self._genh, self._genc):
self._genh.add(gen_visit_members_decl(name))
self._genc.add(gen_visit_object_members(name, base,
- members, variants))
+ members, branches))
# TODO Worth changing the visitor signature, so we could
# directly use rather than repeat type.is_implicit()?
if not name.startswith('q_'):
@@ -413,10 +415,10 @@
info: Optional[QAPISourceInfo],
ifcond: QAPISchemaIfCond,
features: List[QAPISchemaFeature],
- variants: QAPISchemaVariants) -> None:
+ alternatives: QAPISchemaAlternatives) -> None:
with ifcontext(ifcond, self._genh, self._genc):
self._genh.add(gen_visit_decl(name))
- self._genc.add(gen_visit_alternate(name, variants))
+ self._genc.add(gen_visit_alternate(name, alternatives))
def gen_visit(schema: QAPISchema,
diff --git a/system/physmem.c b/system/physmem.c
index 6dc58b3..d3a3d8a 100644
--- a/system/physmem.c
+++ b/system/physmem.c
@@ -31,6 +31,7 @@
#endif /* CONFIG_TCG */
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "exec/target_page.h"
#include "hw/qdev-core.h"
#include "hw/qdev-properties.h"
@@ -2188,43 +2189,28 @@
}
#endif /* !_WIN32 */
-/* Return a host pointer to ram allocated with qemu_ram_alloc.
- * This should not be used for general purpose DMA. Use address_space_map
- * or address_space_rw instead. For local memory (e.g. video ram) that the
- * device owns, use memory_region_get_ram_ptr.
+/*
+ * Return a host pointer to guest's ram.
+ * For Xen, foreign mappings get created if they don't already exist.
*
- * Called within RCU critical section.
- */
-void *qemu_map_ram_ptr(RAMBlock *block, ram_addr_t addr)
-{
- if (block == NULL) {
- block = qemu_get_ram_block(addr);
- addr -= block->offset;
- }
-
- if (xen_enabled() && block->host == NULL) {
- /* We need to check if the requested address is in the RAM
- * because we don't want to map the entire memory in QEMU.
- * In that case just map until the end of the page.
- */
- if (block->offset == 0) {
- return xen_map_cache(addr, 0, 0, false);
- }
-
- block->host = xen_map_cache(block->offset, block->max_length, 1, false);
- }
- return ramblock_ptr(block, addr);
-}
-
-/* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
- * but takes a size argument.
+ * @block: block for the RAM to lookup (optional and may be NULL).
+ * @addr: address within the memory region.
+ * @size: pointer to requested size (optional and may be NULL).
+ * size may get modified and return a value smaller than
+ * what was requested.
+ * @lock: wether to lock the mapping in xen-mapcache until invalidated.
+ * @is_write: hint wether to map RW or RO in the xen-mapcache.
+ * (optional and may always be set to true).
*
* Called within RCU critical section.
*/
static void *qemu_ram_ptr_length(RAMBlock *block, ram_addr_t addr,
- hwaddr *size, bool lock)
+ hwaddr *size, bool lock,
+ bool is_write)
{
- if (*size == 0) {
+ hwaddr len = 0;
+
+ if (size && *size == 0) {
return NULL;
}
@@ -2232,7 +2218,10 @@
block = qemu_get_ram_block(addr);
addr -= block->offset;
}
- *size = MIN(*size, block->max_length - addr);
+ if (size) {
+ *size = MIN(*size, block->max_length - addr);
+ len = *size;
+ }
if (xen_enabled() && block->host == NULL) {
/* We need to check if the requested address is in the RAM
@@ -2240,15 +2229,31 @@
* In that case just map the requested area.
*/
if (block->offset == 0) {
- return xen_map_cache(addr, *size, lock, lock);
+ return xen_map_cache(block->mr, addr, len, lock, lock,
+ is_write);
}
- block->host = xen_map_cache(block->offset, block->max_length, 1, lock);
+ block->host = xen_map_cache(block->mr, block->offset,
+ block->max_length, 1,
+ lock, is_write);
}
return ramblock_ptr(block, addr);
}
+/*
+ * Return a host pointer to ram allocated with qemu_ram_alloc.
+ * This should not be used for general purpose DMA. Use address_space_map
+ * or address_space_rw instead. For local memory (e.g. video ram) that the
+ * device owns, use memory_region_get_ram_ptr.
+ *
+ * Called within RCU critical section.
+ */
+void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
+{
+ return qemu_ram_ptr_length(ram_block, addr, NULL, false, true);
+}
+
/* Return the offset of a hostpointer within a ramblock */
ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host)
{
@@ -2756,7 +2761,7 @@
} else {
/* RAM case */
uint8_t *ram_ptr = qemu_ram_ptr_length(mr->ram_block, mr_addr, l,
- false);
+ false, true);
memmove(ram_ptr, buf, *l);
invalidate_and_set_dirty(mr, mr_addr, *l);
@@ -2849,7 +2854,7 @@
} else {
/* RAM case */
uint8_t *ram_ptr = qemu_ram_ptr_length(mr->ram_block, mr_addr, l,
- false);
+ false, false);
memcpy(buf, ram_ptr, *l);
@@ -3243,7 +3248,7 @@
*plen = flatview_extend_translation(fv, addr, len, mr, xlat,
l, is_write, attrs);
fuzz_dma_read_cb(addr, *plen, mr);
- return qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
+ return qemu_ram_ptr_length(mr->ram_block, xlat, plen, true, is_write);
}
/* Unmaps a memory region previously mapped by address_space_map().
@@ -3339,7 +3344,8 @@
l = flatview_extend_translation(cache->fv, addr, len, mr,
cache->xlat, l, is_write,
MEMTXATTRS_UNSPECIFIED);
- cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
+ cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true,
+ is_write);
} else {
cache->ptr = NULL;
}
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index c5e4958..2f1000c 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -21,6 +21,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "fpu/softfloat-types.h"
#include "exec/helper-proto.h"
#include "qemu/qemu-print.h"
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index fdc3eda..77f8c9c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1941,7 +1941,7 @@
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
/* Use pc-relative instructions in system-mode */
- cs->tcg_cflags |= CF_PCREL;
+ tcg_cflags_set(cs, CF_PCREL);
#endif
/* If we needed to query the host kernel for the CPU features
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a550bcd..c17264c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -26,6 +26,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "exec/gdbstub.h"
+#include "exec/page-protection.h"
#include "qapi/qapi-types-common.h"
#include "target/arm/multiprocessing.h"
#include "target/arm/gtimer.h"
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 31ae43f..4476b32 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -11,6 +11,7 @@
#include "qemu/range.h"
#include "qemu/main-loop.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "cpu.h"
#include "internals.h"
#include "cpu-features.h"
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
index d1f1e02..23d7f73 100644
--- a/target/arm/tcg/m_helper.c
+++ b/target/arm/tcg/m_helper.c
@@ -16,6 +16,7 @@
#include "qemu/bitops.h"
#include "qemu/log.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#ifdef CONFIG_TCG
#include "exec/cpu_ldst.h"
#include "semihosting/common-semi.h"
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index d971b81..037ac6d 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -22,6 +22,7 @@
#include "cpu.h"
#include "internals.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "exec/ram_addr.h"
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
index 6853f58..dd49e67 100644
--- a/target/arm/tcg/sve_helper.c
+++ b/target/arm/tcg/sve_helper.c
@@ -21,6 +21,7 @@
#include "cpu.h"
#include "internals.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h"
#include "fpu/softfloat.h"
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 71ce62a..f53e119 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -55,7 +55,7 @@
static void avr_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
- tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+ tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
cpu_env(cs)->pc_w = tb->pc / 2; /* internally PC points to words */
}
diff --git a/target/avr/helper.c b/target/avr/helper.c
index eeca415..345708a 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -24,6 +24,7 @@
#include "cpu.h"
#include "hw/core/tcg-cpu-ops.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "exec/cpu_ldst.h"
#include "exec/address-spaces.h"
#include "exec/helper-proto.h"
diff --git a/target/cris/mmu.c b/target/cris/mmu.c
index b574ec6..d51008c 100644
--- a/target/cris/mmu.c
+++ b/target/cris/mmu.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "mmu.h"
#ifdef DEBUG
@@ -333,7 +334,7 @@
if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
res->phy = vaddr;
- res->prot = PAGE_BITS;
+ res->prot = PAGE_RWX;
goto done;
}
@@ -344,7 +345,7 @@
miss = 0;
base = cris_mmu_translate_seg(env, seg);
res->phy = base | (0x0fffffff & vaddr);
- res->prot = PAGE_BITS;
+ res->prot = PAGE_RWX;
} else {
miss = cris_mmu_translate_page(res, env, vaddr, access_type,
is_user, debug);
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index a56bb4b..64cc05c 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -257,7 +257,7 @@
static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
- tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+ tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
cpu_env(cs)->gpr[HEX_REG_PC] = tb->pc;
}
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 3831cb6..393a819 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -48,7 +48,7 @@
{
HPPACPU *cpu = HPPA_CPU(cs);
- tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+ tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
#ifdef CONFIG_USER_ONLY
cpu->env.iaoq_f = tb->pc;
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 84785b5..d09877a 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -21,6 +21,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "exec/helper-proto.h"
#include "hw/core/cpu.h"
#include "trace.h"
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 42fa480..6d45611 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -22,6 +22,7 @@
#include "disas/disas.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "tcg/tcg-op.h"
#include "tcg/tcg-op-gvec.h"
#include "exec/helper-proto.h"
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e5723f2..3ef30a7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7382,7 +7382,7 @@
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
/* Use pc-relative instructions in system-mode */
- cs->tcg_cflags |= CF_PCREL;
+ tcg_cflags_set(cs, CF_PCREL);
#endif
if (cpu->apic_id == UNASSIGNED_APIC_ID) {
diff --git a/target/i386/helper.c b/target/i386/helper.c
index 23ccb23..48d1513 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -523,7 +523,7 @@
}
/* Per x86_restore_state_to_opc. */
- if (cs->tcg_cflags & CF_PCREL) {
+ if (tcg_cflags_has(cs, CF_PCREL)) {
return (env->eip & TARGET_PAGE_MASK) | data[0];
} else {
return data[0] - env->segs[R_CS].base;
diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c
index 7a57b7d..8fb05b1 100644
--- a/target/i386/tcg/sysemu/excp_helper.c
+++ b/target/i386/tcg/sysemu/excp_helper.c
@@ -21,6 +21,7 @@
#include "cpu.h"
#include "exec/cpu_ldst.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "tcg/helper-tcg.h"
typedef struct TranslateParams {
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 1ebba04..96da1a6 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -336,7 +336,7 @@
static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
- tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+ tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
set_pc(cpu_env(cs), tb->pc);
}
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 57f5308..d6331f9 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -13,6 +13,7 @@
#include "internals.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "exec/cpu_ldst.h"
#include "exec/log.h"
#include "cpu-csr.h"
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 7a91f33..7967ad1 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "exec/gdbstub.h"
#include "exec/helper-proto.h"
#include "gdbstub/helpers.h"
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 9eb7374..41ad47d 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -99,7 +99,7 @@
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
- tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+ tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
cpu->env.pc = tb->pc;
cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
}
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index d25c9eb..5d3259c 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "qemu/host-utils.h"
#include "exec/log.h"
@@ -51,7 +52,7 @@
if (mmu_idx == MMU_NOMMU_IDX) {
/* MMU disabled or not available. */
address &= TARGET_PAGE_MASK;
- prot = PAGE_BITS;
+ prot = PAGE_RWX;
tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx,
TARGET_PAGE_SIZE);
return true;
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 2340066..2423ac6 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -22,6 +22,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
static unsigned int tlb_decode_size(unsigned int f)
{
diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c
index 5c5184e..505781d 100644
--- a/target/mips/sysemu/physaddr.c
+++ b/target/mips/sysemu/physaddr.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "../internal.h"
static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c
index 13275d1..4886d08 100644
--- a/target/mips/tcg/exception.c
+++ b/target/mips/tcg/exception.c
@@ -81,7 +81,7 @@
{
CPUMIPSState *env = cpu_env(cs);
- tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+ tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
env->active_tc.PC = tb->pc;
env->hflags &= ~MIPS_HFLAG_BMASK;
env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/sysemu/special_helper.c
index 5baa253..9ce5e2c 100644
--- a/target/mips/tcg/sysemu/special_helper.c
+++ b/target/mips/tcg/sysemu/special_helper.c
@@ -93,7 +93,7 @@
CPUMIPSState *env = cpu_env(cs);
if ((env->hflags & MIPS_HFLAG_BMASK) != 0
- && !(cs->tcg_cflags & CF_PCREL) && env->active_tc.PC != tb->pc) {
+ && !tcg_cflags_has(cs, CF_PCREL) && env->active_tc.PC != tb->pc) {
env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
env->hflags &= ~MIPS_HFLAG_BMASK;
return true;
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
index 119eae7..3ba6d36 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -22,6 +22,7 @@
#include "cpu.h"
#include "internal.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "exec/cpu_ldst.h"
#include "exec/log.h"
#include "exec/helper-proto.h"
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index d711035..fdaaa09 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -45,7 +45,7 @@
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
- tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+ tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
cpu->env.pc = tb->pc;
}
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index 603c267..c632d52 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -22,6 +22,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "gdbstub/helpers.h"
#include "qemu/host-utils.h"
#include "hw/loader.h"
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 601c0b5..98b41a9 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -20,6 +20,7 @@
#include "exec/breakpoint.h"
#include "hw/registerfields.h"
+#include "exec/page-protection.h"
/* PM instructions */
typedef enum {
diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c
index 3976416..6dfedab 100644
--- a/target/ppc/mmu-hash32.c
+++ b/target/ppc/mmu-hash32.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "sysemu/kvm.h"
#include "kvm_ppc.h"
#include "internal.h"
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index d645c0b..5a0d80f 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -21,6 +21,7 @@
#include "qemu/units.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "qemu/error-report.h"
#include "qemu/qemu-print.h"
#include "sysemu/hw_accel.h"
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 690dff7..8daf71d 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "qemu/error-report.h"
#include "sysemu/kvm.h"
#include "kvm_ppc.h"
diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h
index 4c768aa..c5c04a1 100644
--- a/target/ppc/mmu-radix64.h
+++ b/target/ppc/mmu-radix64.h
@@ -3,6 +3,8 @@
#ifndef CONFIG_USER_ONLY
+#include "exec/page-protection.h"
+
/* Radix Quadrants */
#define R_EADDR_MASK 0x3FFFFFFFFFFFFFFF
#define R_EADDR_VALID_MASK 0xC00FFFFFFFFFFFFF
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 751403f..4fde7fd 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -25,6 +25,7 @@
#include "mmu-hash64.h"
#include "mmu-hash32.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "exec/log.h"
#include "helper_regs.h"
#include "qemu/error-report.h"
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index c071b4d..b35a93c 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -25,6 +25,7 @@
#include "mmu-hash64.h"
#include "mmu-hash32.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "exec/log.h"
#include "helper_regs.h"
#include "qemu/error-report.h"
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index fc090d7..8ad546a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -24,6 +24,7 @@
#include "internals.h"
#include "pmu.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "instmap.h"
#include "tcg/tcg-op.h"
#include "trace.h"
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 2a76b61..9eea397 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -25,6 +25,7 @@
#include "cpu.h"
#include "trace.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
uint8_t val);
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index b5b95e0..40054a3 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -96,7 +96,7 @@
CPURISCVState *env = &cpu->env;
RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
- tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+ tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
if (xl == MXL_RV32) {
env->pc = (int32_t) tb->pc;
@@ -890,7 +890,7 @@
CPURISCVState *env = &cpu->env;
Error *local_err = NULL;
- CPU(cs)->tcg_cflags |= CF_PCREL;
+ tcg_cflags_set(CPU(cs), CF_PCREL);
if (cpu->cfg.ext_sstc) {
riscv_timer_init(cpu);
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index fa13904..1b4d5a8 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -23,6 +23,7 @@
#include "exec/memop.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
+#include "exec/page-protection.h"
#include "exec/helper-proto.h"
#include "fpu/softfloat.h"
#include "tcg/tcg-gvec-desc.h"
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index e3dfb09..8a584f0 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -22,6 +22,7 @@
#include "cpu.h"
#include "migration/vmstate.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "hw/loader.h"
#include "fpu/softfloat.h"
#include "tcg/debug-assert.h"
@@ -45,7 +46,7 @@
{
RXCPU *cpu = RX_CPU(cs);
- tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+ tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
cpu->env.pc = tb->pc;
}
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
index fbb2f1b..f3a2f25 100644
--- a/target/s390x/mmu_helper.c
+++ b/target/s390x/mmu_helper.c
@@ -24,6 +24,7 @@
#include "sysemu/kvm.h"
#include "sysemu/tcg.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "trace.h"
#include "hw/hw.h"
#include "hw/s390x/storage-keys.h"
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index 557831d..6a308c5 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -25,6 +25,7 @@
#include "tcg_s390x.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "exec/cpu_ldst.h"
#include "hw/core/tcg-cpu-ops.h"
#include "qemu/int128.h"
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 43e35ec..618aa71 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -47,7 +47,7 @@
{
SuperHCPU *cpu = SUPERH_CPU(cs);
- tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+ tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
cpu->env.pc = tb->pc;
cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
}
@@ -74,7 +74,7 @@
CPUSH4State *env = cpu_env(cs);
if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND))
- && !(cs->tcg_cflags & CF_PCREL) && env->pc != tb->pc) {
+ && !tcg_cflags_has(cs, CF_PCREL) && env->pc != tb->pc) {
env->pc -= 2;
env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND);
return true;
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 7c6f9d3..6702910 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -21,6 +21,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "exec/log.h"
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 485d416..5be1592 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -206,7 +206,7 @@
static const sparc_def_t sparc_defs[] = {
#ifdef TARGET_SPARC64
{
- .name = "Fujitsu Sparc64",
+ .name = "Fujitsu-Sparc64",
.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
.fpu_version = 0x00000000,
.mmu_version = mmu_us_12,
@@ -215,7 +215,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "Fujitsu Sparc64 III",
+ .name = "Fujitsu-Sparc64-III",
.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
.fpu_version = 0x00000000,
.mmu_version = mmu_us_12,
@@ -224,7 +224,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "Fujitsu Sparc64 IV",
+ .name = "Fujitsu-Sparc64-IV",
.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
.fpu_version = 0x00000000,
.mmu_version = mmu_us_12,
@@ -233,7 +233,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "Fujitsu Sparc64 V",
+ .name = "Fujitsu-Sparc64-V",
.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
.fpu_version = 0x00000000,
.mmu_version = mmu_us_12,
@@ -242,7 +242,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "TI UltraSparc I",
+ .name = "TI-UltraSparc-I",
.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
.fpu_version = 0x00000000,
.mmu_version = mmu_us_12,
@@ -251,7 +251,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "TI UltraSparc II",
+ .name = "TI-UltraSparc-II",
.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
.fpu_version = 0x00000000,
.mmu_version = mmu_us_12,
@@ -260,7 +260,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "TI UltraSparc IIi",
+ .name = "TI-UltraSparc-IIi",
.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
.fpu_version = 0x00000000,
.mmu_version = mmu_us_12,
@@ -269,7 +269,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "TI UltraSparc IIe",
+ .name = "TI-UltraSparc-IIe",
.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
.fpu_version = 0x00000000,
.mmu_version = mmu_us_12,
@@ -278,7 +278,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "Sun UltraSparc III",
+ .name = "Sun-UltraSparc-III",
.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
.fpu_version = 0x00000000,
.mmu_version = mmu_us_12,
@@ -287,7 +287,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "Sun UltraSparc III Cu",
+ .name = "Sun-UltraSparc-III-Cu",
.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
.fpu_version = 0x00000000,
.mmu_version = mmu_us_3,
@@ -296,7 +296,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "Sun UltraSparc IIIi",
+ .name = "Sun-UltraSparc-IIIi",
.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
.fpu_version = 0x00000000,
.mmu_version = mmu_us_12,
@@ -305,7 +305,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "Sun UltraSparc IV",
+ .name = "Sun-UltraSparc-IV",
.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
.fpu_version = 0x00000000,
.mmu_version = mmu_us_4,
@@ -314,7 +314,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "Sun UltraSparc IV+",
+ .name = "Sun-UltraSparc-IV-plus",
.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
.fpu_version = 0x00000000,
.mmu_version = mmu_us_12,
@@ -323,7 +323,7 @@
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
},
{
- .name = "Sun UltraSparc IIIi+",
+ .name = "Sun-UltraSparc-IIIi-plus",
.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
.fpu_version = 0x00000000,
.mmu_version = mmu_us_3,
@@ -332,7 +332,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "Sun UltraSparc T1",
+ .name = "Sun-UltraSparc-T1",
/* defined in sparc_ifu_fdp.v and ctu.h */
.iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
.fpu_version = 0x00000000,
@@ -343,7 +343,7 @@
| CPU_FEATURE_GL,
},
{
- .name = "Sun UltraSparc T2",
+ .name = "Sun-UltraSparc-T2",
/* defined in tlu_asi_ctl.v and n2_revid_cust.v */
.iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
.fpu_version = 0x00000000,
@@ -354,7 +354,7 @@
| CPU_FEATURE_GL,
},
{
- .name = "NEC UltraSparc I",
+ .name = "NEC-UltraSparc-I",
.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
.fpu_version = 0x00000000,
.mmu_version = mmu_us_12,
@@ -364,7 +364,7 @@
},
#else
{
- .name = "Fujitsu MB86904",
+ .name = "Fujitsu-MB86904",
.iu_version = 0x04 << 24, /* Impl 0, ver 4 */
.fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
@@ -377,7 +377,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "Fujitsu MB86907",
+ .name = "Fujitsu-MB86907",
.iu_version = 0x05 << 24, /* Impl 0, ver 5 */
.fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
@@ -390,7 +390,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "TI MicroSparc I",
+ .name = "TI-MicroSparc-I",
.iu_version = 0x41000000,
.fpu_version = 4 << FSR_VER_SHIFT,
.mmu_version = 0x41000000,
@@ -403,7 +403,7 @@
.features = CPU_FEATURE_MUL | CPU_FEATURE_DIV,
},
{
- .name = "TI MicroSparc II",
+ .name = "TI-MicroSparc-II",
.iu_version = 0x42000000,
.fpu_version = 4 << FSR_VER_SHIFT,
.mmu_version = 0x02000000,
@@ -416,7 +416,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "TI MicroSparc IIep",
+ .name = "TI-MicroSparc-IIep",
.iu_version = 0x42000000,
.fpu_version = 4 << FSR_VER_SHIFT,
.mmu_version = 0x04000000,
@@ -429,7 +429,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "TI SuperSparc 40", /* STP1020NPGA */
+ .name = "TI-SuperSparc-40", /* STP1020NPGA */
.iu_version = 0x41000000, /* SuperSPARC 2.x */
.fpu_version = 0 << FSR_VER_SHIFT,
.mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
@@ -442,7 +442,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "TI SuperSparc 50", /* STP1020PGA */
+ .name = "TI-SuperSparc-50", /* STP1020PGA */
.iu_version = 0x40000000, /* SuperSPARC 3.x */
.fpu_version = 0 << FSR_VER_SHIFT,
.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
@@ -455,7 +455,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "TI SuperSparc 51",
+ .name = "TI-SuperSparc-51",
.iu_version = 0x40000000, /* SuperSPARC 3.x */
.fpu_version = 0 << FSR_VER_SHIFT,
.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
@@ -469,7 +469,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "TI SuperSparc 60", /* STP1020APGA */
+ .name = "TI-SuperSparc-60", /* STP1020APGA */
.iu_version = 0x40000000, /* SuperSPARC 3.x */
.fpu_version = 0 << FSR_VER_SHIFT,
.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
@@ -482,7 +482,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "TI SuperSparc 61",
+ .name = "TI-SuperSparc-61",
.iu_version = 0x44000000, /* SuperSPARC 3.x */
.fpu_version = 0 << FSR_VER_SHIFT,
.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
@@ -496,7 +496,7 @@
.features = CPU_DEFAULT_FEATURES,
},
{
- .name = "TI SuperSparc II",
+ .name = "TI-SuperSparc-II",
.iu_version = 0x40000000, /* SuperSPARC II 1.x */
.fpu_version = 0 << FSR_VER_SHIFT,
.mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
@@ -702,7 +702,7 @@
{
SPARCCPU *cpu = SPARC_CPU(cs);
- tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+ tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
cpu->env.pc = tb->pc;
cpu->env.npc = tb->cs_base;
}
@@ -762,6 +762,16 @@
char *typename;
typename = sparc_cpu_type_name(cpu_model);
+
+ /* Fix up legacy names with '+' in it */
+ if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV+"))) {
+ g_free(typename);
+ typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV-plus"));
+ } else if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi+"))) {
+ g_free(typename);
+ typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi-plus"));
+ }
+
oc = object_class_by_name(typename);
g_free(typename);
return oc;
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index b8087d0..97fbf6f 100644
--- a/target/sparc/helper.h
+++ b/target/sparc/helper.h
@@ -94,15 +94,12 @@
DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_WG, s64, env, f64)
DEF_HELPER_FLAGS_2(fqtox, TCG_CALL_NO_WG, s64, env, i128)
-DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64)
-DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
-DEF_HELPER_FLAGS_2(fmul8x16al, TCG_CALL_NO_RWG_SE, i64, i64, i64)
-DEF_HELPER_FLAGS_2(fmul8x16au, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i32, i32)
+DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i32, i64)
+DEF_HELPER_FLAGS_2(fmul8x16a, TCG_CALL_NO_RWG_SE, i64, i32, s32)
DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fmul8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
-DEF_HELPER_FLAGS_2(fmuld8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
-DEF_HELPER_FLAGS_2(fmuld8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
-DEF_HELPER_FLAGS_2(fexpand, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_1(fexpand, TCG_CALL_NO_RWG_SE, i64, i32)
DEF_HELPER_FLAGS_3(pdist, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_NO_RWG_SE, i32, i64, i64)
DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 2d26404..e2d8a07 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -352,7 +352,7 @@
FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @r_r_r
FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r
BSHUFFLE 10 ..... 110110 ..... 0 0100 1100 ..... @r_r_r
- FEXPAND 10 ..... 110110 ..... 0 0100 1101 ..... @r_r_r
+ FEXPAND 10 ..... 110110 00000 0 0100 1101 ..... @r_r2
FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d
FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 2846a86..7bdf99e 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -23,6 +23,7 @@
#include "tcg/tcg.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "exec/cpu_ldst.h"
#include "asi.h"
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index ad1591d..9ff0602 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -21,6 +21,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "qemu/qemu-print.h"
#include "trace.h"
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 571b3e3..99c6f3c 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -45,6 +45,7 @@
# define gen_helper_clear_softint(E, S) qemu_build_not_reached()
# define gen_helper_done(E) qemu_build_not_reached()
# define gen_helper_flushw(E) qemu_build_not_reached()
+# define gen_helper_fmul8x16a(D, S1, S2) qemu_build_not_reached()
# define gen_helper_rdccr(D, E) qemu_build_not_reached()
# define gen_helper_rdcwp(D, E) qemu_build_not_reached()
# define gen_helper_restored(E) qemu_build_not_reached()
@@ -72,11 +73,7 @@
# define gen_helper_fexpand ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fmul8sux16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fmul8ulx16 ({ qemu_build_not_reached(); NULL; })
-# define gen_helper_fmul8x16al ({ qemu_build_not_reached(); NULL; })
-# define gen_helper_fmul8x16au ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fmul8x16 ({ qemu_build_not_reached(); NULL; })
-# define gen_helper_fmuld8sux16 ({ qemu_build_not_reached(); NULL; })
-# define gen_helper_fmuld8ulx16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fqtox ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fstox ({ qemu_build_not_reached(); NULL; })
@@ -719,6 +716,60 @@
#endif
}
+static void gen_op_fmul8x16al(TCGv_i64 dst, TCGv_i32 src1, TCGv_i32 src2)
+{
+ tcg_gen_ext16s_i32(src2, src2);
+ gen_helper_fmul8x16a(dst, src1, src2);
+}
+
+static void gen_op_fmul8x16au(TCGv_i64 dst, TCGv_i32 src1, TCGv_i32 src2)
+{
+ tcg_gen_sari_i32(src2, src2, 16);
+ gen_helper_fmul8x16a(dst, src1, src2);
+}
+
+static void gen_op_fmuld8ulx16(TCGv_i64 dst, TCGv_i32 src1, TCGv_i32 src2)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ tcg_gen_ext8u_i32(t0, src1);
+ tcg_gen_ext16s_i32(t1, src2);
+ tcg_gen_mul_i32(t0, t0, t1);
+
+ tcg_gen_extract_i32(t1, src1, 16, 8);
+ tcg_gen_sextract_i32(t2, src2, 16, 16);
+ tcg_gen_mul_i32(t1, t1, t2);
+
+ tcg_gen_concat_i32_i64(dst, t0, t1);
+}
+
+static void gen_op_fmuld8sux16(TCGv_i64 dst, TCGv_i32 src1, TCGv_i32 src2)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /*
+ * The insn description talks about extracting the upper 8 bits
+ * of the signed 16-bit input rs1, performing the multiply, then
+ * shifting left by 8 bits. Instead, zap the lower 8 bits of
+ * the rs1 input, which avoids the need for two shifts.
+ */
+ tcg_gen_ext16s_i32(t0, src1);
+ tcg_gen_andi_i32(t0, t0, ~0xff);
+ tcg_gen_ext16s_i32(t1, src2);
+ tcg_gen_mul_i32(t0, t0, t1);
+
+ tcg_gen_sextract_i32(t1, src1, 16, 16);
+ tcg_gen_andi_i32(t1, t1, ~0xff);
+ tcg_gen_sextract_i32(t2, src2, 16, 16);
+ tcg_gen_mul_i32(t1, t1, t2);
+
+ tcg_gen_concat_i32_i64(dst, t0, t1);
+}
+
static void finishing_insn(DisasContext *dc)
{
/*
@@ -4358,6 +4409,25 @@
TRANS(FxTOd, 64, do_env_dd, a, gen_helper_fxtod)
TRANS(FdTOx, 64, do_env_dd, a, gen_helper_fdtox)
+static bool do_df(DisasContext *dc, arg_r_r *a,
+ void (*func)(TCGv_i64, TCGv_i32))
+{
+ TCGv_i64 dst;
+ TCGv_i32 src;
+
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+
+ dst = tcg_temp_new_i64();
+ src = gen_load_fpr_F(dc, a->rs);
+ func(dst, src);
+ gen_store_fpr_D(dc, a->rd, dst);
+ return advance_pc(dc);
+}
+
+TRANS(FEXPAND, VIS1, do_df, a, gen_helper_fexpand)
+
static bool do_env_df(DisasContext *dc, arg_r_r *a,
void (*func)(TCGv_i64, TCGv_env, TCGv_i32))
{
@@ -4564,6 +4634,50 @@
TRANS(FMULs, ALL, do_env_fff, a, gen_helper_fmuls)
TRANS(FDIVs, ALL, do_env_fff, a, gen_helper_fdivs)
+static bool do_dff(DisasContext *dc, arg_r_r_r *a,
+ void (*func)(TCGv_i64, TCGv_i32, TCGv_i32))
+{
+ TCGv_i64 dst;
+ TCGv_i32 src1, src2;
+
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+
+ dst = gen_dest_fpr_D(dc, a->rd);
+ src1 = gen_load_fpr_F(dc, a->rs1);
+ src2 = gen_load_fpr_F(dc, a->rs2);
+ func(dst, src1, src2);
+ gen_store_fpr_D(dc, a->rd, dst);
+ return advance_pc(dc);
+}
+
+TRANS(FMUL8x16AU, VIS1, do_dff, a, gen_op_fmul8x16au)
+TRANS(FMUL8x16AL, VIS1, do_dff, a, gen_op_fmul8x16al)
+TRANS(FMULD8SUx16, VIS1, do_dff, a, gen_op_fmuld8sux16)
+TRANS(FMULD8ULx16, VIS1, do_dff, a, gen_op_fmuld8ulx16)
+TRANS(FPMERGE, VIS1, do_dff, a, gen_helper_fpmerge)
+
+static bool do_dfd(DisasContext *dc, arg_r_r_r *a,
+ void (*func)(TCGv_i64, TCGv_i32, TCGv_i64))
+{
+ TCGv_i64 dst, src2;
+ TCGv_i32 src1;
+
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+
+ dst = gen_dest_fpr_D(dc, a->rd);
+ src1 = gen_load_fpr_F(dc, a->rs1);
+ src2 = gen_load_fpr_D(dc, a->rs2);
+ func(dst, src1, src2);
+ gen_store_fpr_D(dc, a->rd, dst);
+ return advance_pc(dc);
+}
+
+TRANS(FMUL8x16, VIS1, do_dfd, a, gen_helper_fmul8x16)
+
static bool do_ddd(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv_i64, TCGv_i64, TCGv_i64))
{
@@ -4581,15 +4695,8 @@
return advance_pc(dc);
}
-TRANS(FMUL8x16, VIS1, do_ddd, a, gen_helper_fmul8x16)
-TRANS(FMUL8x16AU, VIS1, do_ddd, a, gen_helper_fmul8x16au)
-TRANS(FMUL8x16AL, VIS1, do_ddd, a, gen_helper_fmul8x16al)
TRANS(FMUL8SUx16, VIS1, do_ddd, a, gen_helper_fmul8sux16)
TRANS(FMUL8ULx16, VIS1, do_ddd, a, gen_helper_fmul8ulx16)
-TRANS(FMULD8SUx16, VIS1, do_ddd, a, gen_helper_fmuld8sux16)
-TRANS(FMULD8ULx16, VIS1, do_ddd, a, gen_helper_fmuld8ulx16)
-TRANS(FPMERGE, VIS1, do_ddd, a, gen_helper_fpmerge)
-TRANS(FEXPAND, VIS1, do_ddd, a, gen_helper_fexpand)
TRANS(FPADD16, VIS1, do_ddd, a, tcg_gen_vec_add16_i64)
TRANS(FPADD32, VIS1, do_ddd, a, tcg_gen_vec_add32_i64)
diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c
index 7763b16..e15c6bb 100644
--- a/target/sparc/vis_helper.c
+++ b/target/sparc/vis_helper.c
@@ -44,6 +44,7 @@
#if HOST_BIG_ENDIAN
#define VIS_B64(n) b[7 - (n)]
+#define VIS_SB64(n) sb[7 - (n)]
#define VIS_W64(n) w[3 - (n)]
#define VIS_SW64(n) sw[3 - (n)]
#define VIS_L64(n) l[1 - (n)]
@@ -51,6 +52,7 @@
#define VIS_W32(n) w[1 - (n)]
#else
#define VIS_B64(n) b[n]
+#define VIS_SB64(n) sb[n]
#define VIS_W64(n) w[n]
#define VIS_SW64(n) sw[n]
#define VIS_L64(n) l[n]
@@ -60,6 +62,7 @@
typedef union {
uint8_t b[8];
+ int8_t sb[8];
uint16_t w[4];
int16_t sw[4];
uint32_t l[2];
@@ -74,94 +77,60 @@
float32 f;
} VIS32;
-uint64_t helper_fpmerge(uint64_t src1, uint64_t src2)
+uint64_t helper_fpmerge(uint32_t src1, uint32_t src2)
{
- VIS64 s, d;
+ VIS32 s1, s2;
+ VIS64 d;
- s.ll = src1;
- d.ll = src2;
+ s1.l = src1;
+ s2.l = src2;
+ d.ll = 0;
- /* Reverse calculation order to handle overlap */
- d.VIS_B64(7) = s.VIS_B64(3);
- d.VIS_B64(6) = d.VIS_B64(3);
- d.VIS_B64(5) = s.VIS_B64(2);
- d.VIS_B64(4) = d.VIS_B64(2);
- d.VIS_B64(3) = s.VIS_B64(1);
- d.VIS_B64(2) = d.VIS_B64(1);
- d.VIS_B64(1) = s.VIS_B64(0);
- /* d.VIS_B64(0) = d.VIS_B64(0); */
+ d.VIS_B64(7) = s1.VIS_B32(3);
+ d.VIS_B64(6) = s2.VIS_B32(3);
+ d.VIS_B64(5) = s1.VIS_B32(2);
+ d.VIS_B64(4) = s2.VIS_B32(2);
+ d.VIS_B64(3) = s1.VIS_B32(1);
+ d.VIS_B64(2) = s2.VIS_B32(1);
+ d.VIS_B64(1) = s1.VIS_B32(0);
+ d.VIS_B64(0) = s2.VIS_B32(0);
return d.ll;
}
-uint64_t helper_fmul8x16(uint64_t src1, uint64_t src2)
+static inline int do_ms16b(int x, int y)
{
- VIS64 s, d;
- uint32_t tmp;
+ return ((x * y) + 0x80) >> 8;
+}
- s.ll = src1;
+uint64_t helper_fmul8x16(uint32_t src1, uint64_t src2)
+{
+ VIS64 d;
+ VIS32 s;
+
+ s.l = src1;
d.ll = src2;
-#define PMUL(r) \
- tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
- if ((tmp & 0xff) > 0x7f) { \
- tmp += 0x100; \
- } \
- d.VIS_W64(r) = tmp >> 8;
-
- PMUL(0);
- PMUL(1);
- PMUL(2);
- PMUL(3);
-#undef PMUL
+ d.VIS_W64(0) = do_ms16b(s.VIS_B32(0), d.VIS_SW64(0));
+ d.VIS_W64(1) = do_ms16b(s.VIS_B32(1), d.VIS_SW64(1));
+ d.VIS_W64(2) = do_ms16b(s.VIS_B32(2), d.VIS_SW64(2));
+ d.VIS_W64(3) = do_ms16b(s.VIS_B32(3), d.VIS_SW64(3));
return d.ll;
}
-uint64_t helper_fmul8x16al(uint64_t src1, uint64_t src2)
+uint64_t helper_fmul8x16a(uint32_t src1, int32_t src2)
{
- VIS64 s, d;
- uint32_t tmp;
+ VIS32 s;
+ VIS64 d;
- s.ll = src1;
- d.ll = src2;
+ s.l = src1;
+ d.ll = 0;
-#define PMUL(r) \
- tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
- if ((tmp & 0xff) > 0x7f) { \
- tmp += 0x100; \
- } \
- d.VIS_W64(r) = tmp >> 8;
-
- PMUL(0);
- PMUL(1);
- PMUL(2);
- PMUL(3);
-#undef PMUL
-
- return d.ll;
-}
-
-uint64_t helper_fmul8x16au(uint64_t src1, uint64_t src2)
-{
- VIS64 s, d;
- uint32_t tmp;
-
- s.ll = src1;
- d.ll = src2;
-
-#define PMUL(r) \
- tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
- if ((tmp & 0xff) > 0x7f) { \
- tmp += 0x100; \
- } \
- d.VIS_W64(r) = tmp >> 8;
-
- PMUL(0);
- PMUL(1);
- PMUL(2);
- PMUL(3);
-#undef PMUL
+ d.VIS_W64(0) = do_ms16b(s.VIS_B32(0), src2);
+ d.VIS_W64(1) = do_ms16b(s.VIS_B32(1), src2);
+ d.VIS_W64(2) = do_ms16b(s.VIS_B32(2), src2);
+ d.VIS_W64(3) = do_ms16b(s.VIS_B32(3), src2);
return d.ll;
}
@@ -169,23 +138,14 @@
uint64_t helper_fmul8sux16(uint64_t src1, uint64_t src2)
{
VIS64 s, d;
- uint32_t tmp;
s.ll = src1;
d.ll = src2;
-#define PMUL(r) \
- tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
- if ((tmp & 0xff) > 0x7f) { \
- tmp += 0x100; \
- } \
- d.VIS_W64(r) = tmp >> 8;
-
- PMUL(0);
- PMUL(1);
- PMUL(2);
- PMUL(3);
-#undef PMUL
+ d.VIS_W64(0) = do_ms16b(s.VIS_SB64(1), d.VIS_SW64(0));
+ d.VIS_W64(1) = do_ms16b(s.VIS_SB64(3), d.VIS_SW64(1));
+ d.VIS_W64(2) = do_ms16b(s.VIS_SB64(5), d.VIS_SW64(2));
+ d.VIS_W64(3) = do_ms16b(s.VIS_SB64(7), d.VIS_SW64(3));
return d.ll;
}
@@ -193,80 +153,25 @@
uint64_t helper_fmul8ulx16(uint64_t src1, uint64_t src2)
{
VIS64 s, d;
- uint32_t tmp;
s.ll = src1;
d.ll = src2;
-#define PMUL(r) \
- tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
- if ((tmp & 0xff) > 0x7f) { \
- tmp += 0x100; \
- } \
- d.VIS_W64(r) = tmp >> 8;
-
- PMUL(0);
- PMUL(1);
- PMUL(2);
- PMUL(3);
-#undef PMUL
+ d.VIS_W64(0) = do_ms16b(s.VIS_B64(0), d.VIS_SW64(0));
+ d.VIS_W64(1) = do_ms16b(s.VIS_B64(2), d.VIS_SW64(1));
+ d.VIS_W64(2) = do_ms16b(s.VIS_B64(4), d.VIS_SW64(2));
+ d.VIS_W64(3) = do_ms16b(s.VIS_B64(6), d.VIS_SW64(3));
return d.ll;
}
-uint64_t helper_fmuld8sux16(uint64_t src1, uint64_t src2)
-{
- VIS64 s, d;
- uint32_t tmp;
-
- s.ll = src1;
- d.ll = src2;
-
-#define PMUL(r) \
- tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
- if ((tmp & 0xff) > 0x7f) { \
- tmp += 0x100; \
- } \
- d.VIS_L64(r) = tmp;
-
- /* Reverse calculation order to handle overlap */
- PMUL(1);
- PMUL(0);
-#undef PMUL
-
- return d.ll;
-}
-
-uint64_t helper_fmuld8ulx16(uint64_t src1, uint64_t src2)
-{
- VIS64 s, d;
- uint32_t tmp;
-
- s.ll = src1;
- d.ll = src2;
-
-#define PMUL(r) \
- tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
- if ((tmp & 0xff) > 0x7f) { \
- tmp += 0x100; \
- } \
- d.VIS_L64(r) = tmp;
-
- /* Reverse calculation order to handle overlap */
- PMUL(1);
- PMUL(0);
-#undef PMUL
-
- return d.ll;
-}
-
-uint64_t helper_fexpand(uint64_t src1, uint64_t src2)
+uint64_t helper_fexpand(uint32_t src2)
{
VIS32 s;
VIS64 d;
- s.l = (uint32_t)src1;
- d.ll = src2;
+ s.l = src2;
+ d.ll = 0;
d.VIS_W64(0) = s.VIS_B32(0) << 4;
d.VIS_W64(1) = s.VIS_B32(1) << 4;
d.VIS_W64(2) = s.VIS_B32(2) << 4;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 8f9b72c..bdefb84 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -47,7 +47,7 @@
static void tricore_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
- tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+ tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
cpu_env(cs)->PC = tb->pc;
}
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index 76bd226..7014255 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -20,6 +20,7 @@
#include "hw/registerfields.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#include "fpu/softfloat-helpers.h"
#include "qemu/qemu-print.h"
diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
index 47063b0..997b21d 100644
--- a/target/xtensa/mmu_helper.c
+++ b/target/xtensa/mmu_helper.c
@@ -33,6 +33,7 @@
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
+#include "exec/page-protection.h"
#define XTENSA_MPU_SEGMENT_MASK 0x0000001f
#define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
index 496754b..028d4e0 100644
--- a/target/xtensa/op_helper.c
+++ b/target/xtensa/op_helper.c
@@ -28,6 +28,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
+#include "exec/page-protection.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
#include "qemu/atomic.h"
diff --git a/tests/qapi-schema/test-qapi.py b/tests/qapi-schema/test-qapi.py
index 4009543..7e3f9f4 100755
--- a/tests/qapi-schema/test-qapi.py
+++ b/tests/qapi-schema/test-qapi.py
@@ -48,7 +48,7 @@
self._print_if(ifcond)
def visit_object_type(self, name, info, ifcond, features,
- base, members, variants):
+ base, members, branches):
print('object %s' % name)
if base:
print(' base %s' % base.name)
@@ -57,13 +57,14 @@
% (m.name, m.type.name, m.optional))
self._print_if(m.ifcond, 8)
self._print_features(m.features, indent=8)
- self._print_variants(variants)
+ self._print_variants(branches)
self._print_if(ifcond)
self._print_features(features)
- def visit_alternate_type(self, name, info, ifcond, features, variants):
+ def visit_alternate_type(self, name, info, ifcond, features,
+ alternatives):
print('alternate %s' % name)
- self._print_variants(variants)
+ self._print_variants(alternatives)
self._print_if(ifcond)
self._print_features(features)
