ppc/pnv: Add cut down PSI bridge model and hookup external interrupt
The Processor Service Interface (PSI) Controller is one of the engines
of the "Bridge" unit which connects the different interfaces to the
Power Processor.
This adds just enough of the PSI bridge to handle various on-chip and
the one external interrupt. The rest of PSI has to do with the link to
the IBM FSP service processor which we don't plan to emulate (not used
on OpenPower machines).
The ics_get() and ics_resend() handlers of the XICSFabric interface of
the PowerNV machine are now defined to handle the Interrupt Control
Source of PSI. The InterruptStatsProvider interface is also modified
to dump the new ICS.
Originally from Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 96231c1..a3ed2ee 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -22,6 +22,7 @@
#include "hw/boards.h"
#include "hw/sysbus.h"
#include "hw/ppc/pnv_lpc.h"
+#include "hw/ppc/pnv_psi.h"
#define TYPE_PNV_CHIP "powernv-chip"
#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
@@ -57,6 +58,7 @@
MemoryRegion icp_mmio;
PnvLpcController lpc;
+ PnvPsi psi;
} PnvChip;
typedef struct PnvChipClass {
@@ -125,6 +127,7 @@
PnvChip **chips;
ISABus *isa_bus;
+ uint32_t cpld_irqstate;
} PnvMachineState;
#define PNV_FDT_ADDR 0x01000000
@@ -155,4 +158,14 @@
#define PNV_ICP_BASE(chip) \
(0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)
+
+#define PNV_PSIHB_SIZE 0x0000000000100000ull
+#define PNV_PSIHB_BASE(chip) \
+ (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE)
+
+#define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
+#define PNV_PSIHB_FSP_BASE(chip) \
+ (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \
+ PNV_PSIHB_FSP_SIZE)
+
#endif /* _PPC_PNV_H */
