commit 53ae2fdef1f5661cbaa2ea571c517f98e6041cb8
author Peter Maydell <peter.maydell@linaro.org> Fri Jul 15 13:33:23 2022 +0100
committer Peter Maydell <peter.maydell@linaro.org> Mon Jul 18 13:20:14 2022 +0100
tree e4bc3aa6c600c0c462b25c0617e61ee75c70d573
parent 99638ba9d86b7707adabbf0b223a6e0ae144cd88

target/arm: Don't set syndrome ISS for loads and stores with writeback

The architecture requires that for faults on loads and stores which
do writeback, the syndrome information does not have the ISS
instruction syndrome information (i.e. ISV is 0).  We got this wrong
for the load and store instructions covered by disas_ldst_reg_imm9().
Calculate iss_valid correctly so that if the insn is a writeback one
it is false.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1057
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220715123323.1550983-1-peter.maydell@linaro.org

target/arm/translate-a64.c

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b7b64f7..163df8c 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3138,7 +3138,7 @@
     bool is_store = false;
     bool is_extended = false;
     bool is_unpriv = (idx == 2);
-    bool iss_valid = !is_vector;
+    bool iss_valid;
     bool post_index;
     bool writeback;
     int memidx;
@@ -3191,6 +3191,8 @@
         g_assert_not_reached();
     }
 
+    iss_valid = !is_vector && !writeback;
+
     if (rn == 31) {
         gen_check_sp_alignment(s);
     }