commit 534ce69ff05bee2448419f9cad796d6511bc1f9a
author ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> Wed Apr 11 02:13:00 2007 +0000
committer ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> Wed Apr 11 02:13:00 2007 +0000
tree 2cdc711dc1e8643b9ab7d29a1dab08412457218c
parent e9df014c0b433ecd9785db4a423e472bc3db386a

More Context/Xcontext fixes. Ifdef some 64bit-only ops, they may
end up empty for 32bit mips, which dyngen trips over.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2648 c046a42c-6fe2-441c-8c8c-71466251a162

target-mips/translate.c

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 0d9226a..8aacbd0 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -2750,7 +2750,7 @@
         switch (sel) {
         case 0:
            /* 64 bit MMU only */
-           gen_op_mtc0_xcontext();
+           /* Nothing writable in lower 32 bits */
            rn = "XContext";
            break;
         default:
@@ -2946,6 +2946,7 @@
     generate_exception(ctx, EXCP_RI);
 }
 
+#ifdef TARGET_MIPS64
 static void gen_dmfc0 (DisasContext *ctx, int reg, int sel)
 {
     const char *rn = "invalid";
@@ -4120,6 +4121,7 @@
 #endif
     generate_exception(ctx, EXCP_RI);
 }
+#endif /* TARGET_MIPS64 */
 
 static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
 {
@@ -4140,6 +4142,7 @@
         gen_mtc0(ctx, rd, ctx->opcode & 0x7);
         opn = "mtc0";
         break;
+#ifdef TARGET_MIPS64
     case OPC_DMFC0:
         if (rt == 0) {
             /* Treat as NOP */
@@ -4154,6 +4157,7 @@
         gen_dmtc0(ctx, rd, ctx->opcode & 0x7);
         opn = "dmtc0";
         break;
+#endif
 #if defined(MIPS_USES_R4K_TLB)
     case OPC_TLBWI:
         gen_op_tlbwi();