commit 51855ecf1a9d5a8388778571b8ab32134e83f378
author Richard Henderson <rth@twiddle.net> Mon Sep 24 12:06:15 2012 -0700
committer Richard Henderson <rth@twiddle.net> Sat Jan 05 12:00:27 2013 -0800
tree 4051cc2789b484a534b55f055a84ffe90f201d73
parent 2f22e2ec79c07de03016adefb166cf01745fc852

target-s390: Fix PSW_MASK handling

We were treating psw.mask as the 32-bit quantity it is in ESA mode.
In particular, the CC field was at the wrong place.

Signed-off-by: Richard Henderson <rth@twiddle.net>

target-s390x/helper.c

diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 42e06eb..7dc4d46 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -454,18 +454,19 @@
 
     env->psw.addr = addr;
     env->psw.mask = mask;
-    env->cc_op = (mask >> 13) & 3;
+    env->cc_op = (mask >> 44) & 3;
 }
 
 static uint64_t get_psw_mask(CPUS390XState *env)
 {
-    uint64_t r = env->psw.mask;
+    uint64_t r;
 
     env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
 
-    r &= ~(3ULL << 13);
+    r = env->psw.mask;
+    r &= ~PSW_MASK_CC;
     assert(!(env->cc_op & ~3));
-    r |= env->cc_op << 13;
+    r |= (uint64_t)env->cc_op << 44;
 
     return r;
 }

target-s390x/translate.c

diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index b8f2ca8..dc0f9cc 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -4559,6 +4559,8 @@
         tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
         tcg_gen_addi_i64(tmp, tmp, 4);
         tcg_gen_qemu_ld32u(tmp3, tmp, get_mem_index(s));
+        /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK.  */
+        tcg_gen_shli_i64(tmp2, tmp2, 32);
         gen_helper_load_psw(cpu_env, tmp2, tmp3);
         tcg_temp_free_i64(tmp);
         tcg_temp_free_i64(tmp2);