diff --git a/target-ppc/dfp_helper.c b/target-ppc/dfp_helper.c
index e5574b5..23f85c4 100644
--- a/target-ppc/dfp_helper.c
+++ b/target-ppc/dfp_helper.c
@@ -376,6 +376,23 @@
     dn->bits |= DECNAN;
 }
 
+static inline int dfp_get_digit(decNumber *dn, int n)
+{
+    assert(DECDPUN == 3);
+    int unit = n / DECDPUN;
+    int dig = n % DECDPUN;
+    switch (dig) {
+    case 0:
+        return dn->lsu[unit] % 10;
+    case 1:
+        return (dn->lsu[unit] / 10) % 10;
+    case 2:
+        return dn->lsu[unit] / 100;
+    default:
+        assert(0);
+    }
+}
+
 #define DFP_HELPER_TAB(op, dnop, postprocs, size)                              \
 void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *a, uint64_t *b)      \
 {                                                                              \
@@ -703,3 +720,83 @@
 
 DFP_HELPER_QUA(dqua, 64)
 DFP_HELPER_QUA(dquaq, 128)
+
+static void _dfp_reround(uint8_t rmc, int32_t ref_sig, int32_t xmax,
+                             struct PPC_DFP *dfp)
+{
+    int msd_orig, msd_rslt;
+
+    if (unlikely((ref_sig == 0) || (dfp->b.digits <= ref_sig))) {
+        dfp->t = dfp->b;
+        if (decNumberIsSNaN(&dfp->b)) {
+            dfp_makeQNaN(&dfp->t);
+            dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXSNAN, FPSCR_VE);
+        }
+        return;
+    }
+
+    /* Reround is equivalent to quantizing b with 1**E(n) where */
+    /* n = exp(b) + numDigits(b) - reference_significance.      */
+
+    decNumberFromUInt32(&dfp->a, 1);
+    dfp->a.exponent = dfp->b.exponent + dfp->b.digits - ref_sig;
+
+    if (unlikely(dfp->a.exponent > xmax)) {
+        dfp->t.digits = 0;
+        dfp->t.bits &= ~DECNEG;
+        dfp_makeQNaN(&dfp->t);
+        dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXCVI, FPSCR_VE);
+        return;
+    }
+
+    dfp_quantize(rmc, dfp);
+
+    msd_orig = dfp_get_digit(&dfp->b, dfp->b.digits-1);
+    msd_rslt = dfp_get_digit(&dfp->t, dfp->t.digits-1);
+
+    /* If the quantization resulted in rounding up to the next magnitude, */
+    /* then we need to shift the significand and adjust the exponent.     */
+
+    if (unlikely((msd_orig == 9) && (msd_rslt == 1))) {
+
+        decNumber negone;
+
+        decNumberFromInt32(&negone, -1);
+        decNumberShift(&dfp->t, &dfp->t, &negone, &dfp->context);
+        dfp->t.exponent++;
+
+        if (unlikely(dfp->t.exponent > xmax)) {
+            dfp_makeQNaN(&dfp->t);
+            dfp->t.digits = 0;
+            dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXCVI, FP_VE);
+            /* Inhibit XX in this case */
+            decContextClearStatus(&dfp->context, DEC_Inexact);
+        }
+    }
+}
+
+#define DFP_HELPER_RRND(op, size)                                       \
+void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *a,            \
+                 uint64_t *b, uint32_t rmc)                             \
+{                                                                       \
+    struct PPC_DFP dfp;                                                 \
+    int32_t ref_sig = *a & 0x3F;                                        \
+    int32_t xmax = ((size) == 64) ? 369 : 6111;                         \
+                                                                        \
+    dfp_prepare_decimal##size(&dfp, 0, b, env);                         \
+                                                                        \
+    _dfp_reround(rmc, ref_sig, xmax, &dfp);                             \
+    decimal##size##FromNumber((decimal##size *)dfp.t64, &dfp.t,         \
+                              &dfp.context);                            \
+    QUA_PPs(&dfp);                                                      \
+                                                                        \
+    if (size == 64) {                                                   \
+        t[0] = dfp.t64[0];                                              \
+    } else if (size == 128) {                                           \
+        t[0] = dfp.t64[HI_IDX];                                         \
+        t[1] = dfp.t64[LO_IDX];                                         \
+    }                                                                   \
+}
+
+DFP_HELPER_RRND(drrnd, 64)
+DFP_HELPER_RRND(drrndq, 128)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 362e9a8..776d4d7 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -640,3 +640,5 @@
 DEF_HELPER_5(dquaiq, void, env, fprp, fprp, i32, i32)
 DEF_HELPER_5(dqua, void, env, fprp, fprp, fprp, i32)
 DEF_HELPER_5(dquaq, void, env, fprp, fprp, fprp, i32)
+DEF_HELPER_5(drrnd, void, env, fprp, fprp, fprp, i32)
+DEF_HELPER_5(drrndq, void, env, fprp, fprp, fprp, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 00dbfa8..0647a4b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -8380,6 +8380,8 @@
 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
+GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
+GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
 /***                           SPE extension                               ***/
 /* Register moves */
 
@@ -11331,6 +11333,8 @@
 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
+GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
+GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
 #undef GEN_SPE
 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
     GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)