)]}' { "commit": "50b5fd232ebc1901b2e040a8394f50a63e3f24ec", "tree": "099fc08d05ec033596b6906c86310667265bd37c", "parents": [ "f63c6c23fba52b1496420e31299de42fd342a2c6" ], "author": { "name": "Gustavo Romero", "email": "gustavo.romero@linaro.org", "time": "Tue Jul 01 15:08:31 2025 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Tue Jul 01 15:08:31 2025 +0100" }, "message": "qtest/bios-tables-test: Add blobs for its\u003doff test on aarch64\n\nAdd blobs for test_acpi_aarch64_virt_tcg_its_off(), which introduces a\nnew variant, .its_off, that requires variations of the MADT and IORT\ntables.\n\nMADT (aka APIC) diff:\n\n+[000h 0000 4] Signature : \"APIC\" [Multiple APIC Description Table (MADT)]\n+[004h 0004 4] Table Length : 000000B8\n+[008h 0008 1] Revision : 04\n+[009h 0009 1] Checksum : C1\n+[00Ah 0010 6] Oem ID : \"BOCHS \"\n+[010h 0016 8] Oem Table ID : \"BXPC \"\n+[018h 0024 4] Oem Revision : 00000001\n+[01Ch 0028 4] Asl Compiler ID : \"BXPC\"\n+[020h 0032 4] Asl Compiler Revision : 00000001\n+\n+[024h 0036 4] Local Apic Address : 00000000\n+[028h 0040 4] Flags (decoded below) : 00000000\n+ PC-AT Compatibility : 0\n+\n+[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor]\n+[02Dh 0045 1] Length : 18\n+[02Eh 0046 2] Reserved : 0000\n+[030h 0048 4] Local GIC Hardware ID : 00000000\n+[034h 0052 8] Base Address : 0000000008000000\n+[03Ch 0060 4] Interrupt Base : 00000000\n+[040h 0064 1] Version : 03\n+[041h 0065 3] Reserved : 000000\n+\n+[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller]\n+[045h 0069 1] Length : 50\n+[046h 0070 2] Reserved : 0000\n+[048h 0072 4] CPU Interface Number : 00000000\n+[04Ch 0076 4] Processor UID : 00000000\n+[050h 0080 4] Flags (decoded below) : 00000001\n+ Processor Enabled : 1\n+ Performance Interrupt Trigger Mode : 0\n+ Virtual GIC Interrupt Trigger Mode : 0\n+[054h 0084 4] Parking Protocol Version : 00000000\n+[058h 0088 4] Performance Interrupt : 00000017\n+[05Ch 0092 8] Parked Address : 0000000000000000\n+[064h 0100 8] Base Address : 0000000000000000\n+[06Ch 0108 8] Virtual GIC Base Address : 0000000000000000\n+[074h 0116 8] Hypervisor GIC Base Address : 0000000000000000\n+[07Ch 0124 4] Virtual GIC Interrupt : 00000000\n+[080h 0128 8] Redistributor Base Address : 0000000000000000\n+[088h 0136 8] ARM MPIDR : 0000000000000000\n+[090h 0144 1] Efficiency Class : 00\n+[091h 0145 1] Reserved : 00\n+[092h 0146 2] SPE Overflow Interrupt : 0000\n+\n+[094h 0148 1] Subtable Type : 0E [Generic Interrupt Redistributor]\n+[095h 0149 1] Length : 10\n+[096h 0150 2] Reserved : 0000\n+[098h 0152 8] Base Address : 00000000080A0000\n+[0A0h 0160 4] Length : 00F60000\n+\n+[0A4h 0164 1] Subtable Type : 0F [Generic Interrupt Translator]\n+[0A5h 0165 1] Length : 14\n+[0A6h 0166 2] Reserved : 0000\n+[0A8h 0168 4] Translation ID : 00000000\n+[0ACh 0172 8] Base Address : 0000000008080000\n+[0B4h 0180 4] Reserved : 00000000\n\nIORT diff:\n\n+[000h 0000 4] Signature : \"IORT\" [IO Remapping Table]\n+[004h 0004 4] Table Length : 000000EC\n+[008h 0008 1] Revision : 03\n+[009h 0009 1] Checksum : 57\n+[00Ah 0010 6] Oem ID : \"BOCHS \"\n+[010h 0016 8] Oem Table ID : \"BXPC \"\n+[018h 0024 4] Oem Revision : 00000001\n+[01Ch 0028 4] Asl Compiler ID : \"BXPC\"\n+[020h 0032 4] Asl Compiler Revision : 00000001\n+\n+[024h 0036 4] Node Count : 00000003\n+[028h 0040 4] Node Offset : 00000030\n+[02Ch 0044 4] Reserved : 00000000\n+\n+[030h 0048 1] Type : 00\n+[031h 0049 2] Length : 0018\n+[033h 0051 1] Revision : 01\n+[034h 0052 4] Reserved : 00000000\n+[038h 0056 4] Mapping Count : 00000000\n+[03Ch 0060 4] Mapping Offset : 00000000\n+\n+[040h 0064 4] ItsCount : 00000001\n+[044h 0068 4] Identifiers : 00000000\n+\n+[048h 0072 1] Type : 04\n+[049h 0073 2] Length : 0058\n+[04Bh 0075 1] Revision : 04\n+[04Ch 0076 4] Reserved : 00000001\n+[050h 0080 4] Mapping Count : 00000001\n+[054h 0084 4] Mapping Offset : 00000044\n+\n+[058h 0088 8] Base Address : 0000000009050000\n+[060h 0096 4] Flags (decoded below) : 00000001\n+ COHACC Override : 1\n+ HTTU Override : 0\n+ Proximity Domain Valid : 0\n+[064h 0100 4] Reserved : 00000000\n+[068h 0104 8] VATOS Address : 0000000000000000\n+[070h 0112 4] Model : 00000000\n+[074h 0116 4] Event GSIV : 0000006A\n+[078h 0120 4] PRI GSIV : 0000006B\n+[07Ch 0124 4] GERR GSIV : 0000006D\n+[080h 0128 4] Sync GSIV : 0000006C\n+[084h 0132 4] Proximity Domain : 00000000\n+[088h 0136 4] Device ID Mapping Index : 00000000\n+\n+[08Ch 0140 4] Input base : 00000000\n+[090h 0144 4] ID Count : 0000FFFF\n+[094h 0148 4] Output Base : 00000000\n+[098h 0152 4] Output Reference : 00000030\n+[09Ch 0156 4] Flags (decoded below) : 00000000\n+ Single Mapping : 0\n+\n+[0A0h 0160 1] Type : 02\n+[0A1h 0161 2] Length : 004C\n+[0A3h 0163 1] Revision : 03\n+[0A4h 0164 4] Reserved : 00000002\n+[0A8h 0168 4] Mapping Count : 00000002\n+[0ACh 0172 4] Mapping Offset : 00000024\n+\n+[0B0h 0176 8] Memory Properties : [IORT Memory Access Properties]\n+[0B0h 0176 4] Cache Coherency : 00000001\n+[0B4h 0180 1] Hints (decoded below) : 00\n+ Transient : 0\n+ Write Allocate : 0\n+ Read Allocate : 0\n+ Override : 0\n+[0B5h 0181 2] Reserved : 0000\n+[0B7h 0183 1] Memory Flags (decoded below) : 03\n+ Coherency : 1\n+ Device Attribute : 1\n+[0B8h 0184 4] ATS Attribute : 00000000\n+[0BCh 0188 4] PCI Segment Number : 00000000\n+[0C0h 0192 1] Memory Size Limit : 40\n+[0C1h 0193 3] Reserved : 000000\n+\n+[0C4h 0196 4] Input base : 00000000\n+[0C8h 0200 4] ID Count : 000000FF\n+[0CCh 0204 4] Output Base : 00000000\n+[0D0h 0208 4] Output Reference : 00000048\n+[0D4h 0212 4] Flags (decoded below) : 00000000\n+ Single Mapping : 0\n+\n+[0D8h 0216 4] Input base : 00000100\n+[0DCh 0220 4] ID Count : 0000FEFF\n+[0E0h 0224 4] Output Base : 00000100\n+[0E4h 0228 4] Output Reference : 00000030\n+[0E8h 0232 4] Flags (decoded below) : 00000000\n+ Single Mapping : 0\n\nSigned-off-by: Gustavo Romero \u003cgustavo.romero@linaro.org\u003e\nReviewed-by: Eric Auger \u003ceric.auger@redhat.com\u003e\nMessage-id: 20250628195722.977078-8-gustavo.romero@linaro.org\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n", "tree_diff": [ { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "37d82e970b1331cb5b259f0bd2d3654bacb2d623", "new_mode": 33188, "new_path": "tests/data/acpi/aarch64/virt/APIC.its_off" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "0fceb820d509e852ca0849baf568a8e93e426738", "new_mode": 33188, "new_path": "tests/data/acpi/aarch64/virt/IORT.its_off" }, { "type": "modify", "old_id": "a88198d5c2a5c7251e996f67e06af4be394c98d7", "old_mode": 33188, "old_path": "tests/qtest/bios-tables-test-allowed-diff.h", "new_id": "dfb8523c8bf457c471cea8d860eff394b2d3700f", "new_mode": 33188, "new_path": "tests/qtest/bios-tables-test-allowed-diff.h" } ] }