commit | ae80a3546f412c407199b9b7ebd52ac604361e10 | [log] [tgz] |
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author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | Thu Feb 28 18:23:15 2013 +0000 |
committer | Peter Maydell <peter.maydell@linaro.org> | Thu Feb 28 18:49:24 2013 +0000 |
tree | a1e979f97c5d2d0ad72c7fcba85afe21e1eb0dfc | |
parent | 1c5d07909aea7657c7c6b24223460150526369ba [diff] |
cadence_gem: fix interrupt events Bits in the ISR were continually mirroring their corresponding TX/RX SR bits. This is incorrect. The ISR bits are only ever set at the time their corresponding event occurs. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: cedfb6d108318846480b416a6041023ea5a353d6.1360901435.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>