)]}'
{
  "commit": "4f07934c4e6af1b2bf8ec0ab62bbf8076d810478",
  "tree": "2839b322c4e0ed0812f22df914bfb5e22986d869",
  "parents": [
    "b346ba5889bcfd59c8dbd3c79c16015d9154cdd3"
  ],
  "author": {
    "name": "TANG Tiancheng",
    "email": "lyndra@linux.alibaba.com",
    "time": "Fri Jul 03 13:03:37 2026 +0800"
  },
  "committer": {
    "name": "Michael Tokarev",
    "email": "mjt@tls.msk.ru",
    "time": "Tue Aug 25 10:27:16 2026 +0300"
  },
  "message": "disas/riscv: Fix 6-bit immediate extraction\n\nrv_codec_r2_imm6 is used for XThead instructions whose 6-bit\nimmediate field is encoded in bits 25:20. The old expression\nleft-shifted by 38 and then right-shifted by 60, so it kept only\nbits 25:22.\n\nUse extract32() to decode bits 25:20 directly. This fixes the\nimmediate printed for th.srri and th.tst.\n\nFixes: 318df7238b9f (\"disas/riscv: Add support for XThead* instructions\")\nSuggested-by: Alex Bennée \u003calex.bennee@linaro.org\u003e\nSigned-off-by: TANG Tiancheng \u003clyndra@linux.alibaba.com\u003e\nReviewed-by: LIU Zhiwei \u003czhiwei_liu@linux.alibaba.com\u003e\nReviewed-by: Daniel Henrique Barboza \u003cdaniel.barboza@oss.qualcomm.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nMessage-ID: \u003c20260703-b4-disas-xthead-fix-riscv-next-v4-2-84c566330bc7@linux.alibaba.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n(cherry picked from commit 7a8454ef293085a45686929577b7d5a5daded242)\nSigned-off-by: Michael Tokarev \u003cmjt@tls.msk.ru\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "5a61d1bb8083ff42a64516f2e653c72a610ca8ae",
      "old_mode": 33188,
      "old_path": "disas/riscv.c",
      "new_id": "2de092ed9219077c5b6fd97562fa40e41a28766f",
      "new_mode": 33188,
      "new_path": "disas/riscv.c"
    }
  ]
}