)]}'
{
  "commit": "4ef00a9fc4a4e77d007c94d779f041b74adff951",
  "tree": "1477f49f4570babebaf211c0368db8b366a59671",
  "parents": [
    "83927347227c91dd659e7ed718d656ed0d551ab6"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon Jul 20 19:05:29 2026 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon Jul 20 19:05:29 2026 +0100"
  },
  "message": "target/arm: GICv5 cpuif: gicr_cdia_read() ppibit should be 64 bits\n\nIn gicr_cdia_read() we turn a PPI interrupt ID into a register\nindex and a bit mask with a 1 for the bit we want to change:\n\n        ppireg \u003d id / 64;\n        ppibit \u003d 1ULL \u003c\u003c (id % 64);\n\nHowever, we used the wrong type for ppibit, making it a uint32_t.  If\n\u0027id\u0027 is too large we\u0027ll shift off the end, so we won\u0027t ever update\nthe state of PPIs with indexes above 31.\n\nThis didn\u0027t have any visible effects because the currently allocated\narchitected PPIs are indexes 0..31, so you\u0027d only see this if for\nsome reason a guest was manually marking as pending a PPI in 32..63.\n\nFix the type of ppibit to the intended 64 bit width.\n\nFixes: 3f79212abae89 (\"target/arm: GICv5 cpuif: Implement GICR CDIA command\")\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@oss.qualcomm.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-id: 20260714091806.3568281-2-peter.maydell@linaro.org\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1cdd4103d0ec176f6bb8adc17d9a719da89cc322",
      "old_mode": 33188,
      "old_path": "target/arm/tcg/gicv5-cpuif.c",
      "new_id": "8e2a08fdb6f1d4f7d9e9d7ef520a302d0e92bbbb",
      "new_mode": 33188,
      "new_path": "target/arm/tcg/gicv5-cpuif.c"
    }
  ]
}