)]}'
{
  "commit": "4bf501dc0118a28699e28c01acb34e28ddeb0acc",
  "tree": "e202e71dfd7cfa5e73efcc35fffc6420acf2932a",
  "parents": [
    "095fe72a128b34d4f9317c2798c6fa7762a9e3e6"
  ],
  "author": {
    "name": "Mayuresh Chitale",
    "email": "mchitale@ventanamicro.com",
    "time": "Thu Oct 19 12:26:44 2023 +0530"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Tue Nov 07 11:06:02 2023 +1000"
  },
  "message": "target/riscv: pmp: Clear pmp/smepmp bits on reset\n\nAs per the Priv and Smepmp specifications, certain bits such as the \u0027L\u0027\nbit of pmp entries and mseccfg.MML can only be cleared upon reset and it\nis necessary to do so to allow \u0027M\u0027 mode firmware to correctly reinitialize\nthe pmp/smpemp state across reboots. As required by the spec, also clear\nthe \u0027A\u0027 field of pmp entries.\n\nSigned-off-by: Mayuresh Chitale \u003cmchitale@ventanamicro.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nMessage-ID: \u003c20231019065644.1431798-1-mchitale@ventanamicro.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0c58c8571fb2e1da6ad27cbdfbb1bb47b4eb7e85",
      "old_mode": 33188,
      "old_path": "target/riscv/cpu.c",
      "new_id": "a2881bfa383802921431a655be4859641b107705",
      "new_mode": 33188,
      "new_path": "target/riscv/cpu.c"
    },
    {
      "type": "modify",
      "old_id": "21d2489e27e9b644034598117add95bd7bd178ae",
      "old_mode": 33188,
      "old_path": "target/riscv/pmp.c",
      "new_id": "4dfaa28fce2e41f580484c1bdb24810444f67062",
      "new_mode": 33188,
      "new_path": "target/riscv/pmp.c"
    },
    {
      "type": "modify",
      "old_id": "cf5c99f8e68d6f511e5338ca8a20ea248b246180",
      "old_mode": 33188,
      "old_path": "target/riscv/pmp.h",
      "new_id": "9af8614cd4ff9bc7d92246c361fc4294ec3b69d1",
      "new_mode": 33188,
      "new_path": "target/riscv/pmp.h"
    }
  ]
}