tree 4b745713e1629390bc544179c0485af26dd4f9fc
parent e087bd4de3369d678ed8ebda4ba1c11b782cf899
author LIU Zhiwei <zhiwei_liu@linux.alibaba.com> 1726725047 +0800
committer Alistair Francis <alistair.francis@wdc.com> 1730251327 +1000

target/riscv: Add max32 CPU for RV64 QEMU

We may need 32-bit max for RV64 QEMU. Thus we add these two CPUs
for RV64 QEMU.

The reason we don't expose them to RV32 QEMU is that we already have
max cpu with the same configuration. Another reason is that we want
to follow the RISC-V custom where addw instruction doesn't exist in
RV32 CPU.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Suggested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240919055048.562-8-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>