)]}'
{
  "commit": "48cea772c3e2ac817c2d0741b89a9e968ec2cd81",
  "tree": "4b745713e1629390bc544179c0485af26dd4f9fc",
  "parents": [
    "e087bd4de3369d678ed8ebda4ba1c11b782cf899"
  ],
  "author": {
    "name": "LIU Zhiwei",
    "email": "zhiwei_liu@linux.alibaba.com",
    "time": "Thu Sep 19 13:50:47 2024 +0800"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Wed Oct 30 11:22:07 2024 +1000"
  },
  "message": "target/riscv: Add max32 CPU for RV64 QEMU\n\nWe may need 32-bit max for RV64 QEMU. Thus we add these two CPUs\nfor RV64 QEMU.\n\nThe reason we don\u0027t expose them to RV32 QEMU is that we already have\nmax cpu with the same configuration. Another reason is that we want\nto follow the RISC-V custom where addw instruction doesn\u0027t exist in\nRV32 CPU.\n\nSigned-off-by: LIU Zhiwei \u003czhiwei_liu@linux.alibaba.com\u003e\nSuggested-by: Daniel Henrique Barboza \u003cdbarboza@ventanamicro.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nReviewed-by: Daniel Henrique Barboza \u003cdbarboza@ventanamicro.com\u003e\nMessage-ID: \u003c20240919055048.562-8-zhiwei_liu@linux.alibaba.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4464c0fd7a3ca1efd2cacc507df31de5c1a9498e",
      "old_mode": 33188,
      "old_path": "target/riscv/cpu-qom.h",
      "new_id": "62115375cdc0eccc504c3ee4e439b43209b1e48b",
      "new_mode": 33188,
      "new_path": "target/riscv/cpu-qom.h"
    },
    {
      "type": "modify",
      "old_id": "44288013cccbaa3f2558a907d4db2cfe0f4c03f5",
      "old_mode": 33188,
      "old_path": "target/riscv/cpu.c",
      "new_id": "0c8e017f71246bc97a7cfe267bb429df08ee1825",
      "new_mode": 33188,
      "new_path": "target/riscv/cpu.c"
    }
  ]
}