)]}'
{
  "commit": "48531f5adb2aede5519d072b9bbc27f46994ce2d",
  "tree": "6e6cdfc0c7374c0b271971b0fe0d8657d2b1893c",
  "parents": [
    "fba92a92e39069d7dc648cba1e561f28b7e91df6"
  ],
  "author": {
    "name": "Daniel Henrique Barboza",
    "email": "dbarboza@ventanamicro.com",
    "time": "Mon Dec 18 09:53:27 2023 -0300"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Wed Jan 10 18:47:47 2024 +1000"
  },
  "message": "target/riscv: implement svade\n\n\u0027svade\u0027 is a RVA22S64 profile requirement, a profile we\u0027re going to add\nshortly. It is a named feature (i.e. not a formal extension, not defined\nin riscv,isa DT at this moment) defined in [1] as:\n\n\"Page-fault exceptions are raised when a page is accessed when A bit is\nclear, or written when D bit is clear.\".\n\nAs far as the spec goes, \u0027svade\u0027 is one of the two distinct modes of\nhandling PTE_A and PTE_D. The other way, i.e. update PTE_A/PTE_D when\nthey\u0027re cleared, is defined by the \u0027svadu\u0027 extension. Checking\ncpu_helper.c, get_physical_address(), we can verify that QEMU is\ncompliant with that: we will update PTE_A/PTE_D if \u0027svadu\u0027 is enabled,\nor throw a page-fault exception if \u0027svadu\u0027 isn\u0027t enabled.\n\nSo, as far as we\u0027re concerned, \u0027svade\u0027 translates to \u0027svadu must be\ndisabled\u0027.\n\nWe\u0027ll implement it like \u0027zic64b\u0027: an internal flag that profiles can\nenable. The flag will not be exposed to users.\n\n[1] https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc\n\nSigned-off-by: Daniel Henrique Barboza \u003cdbarboza@ventanamicro.com\u003e\nReviewed-by: Andrew Jones \u003cajones@ventanamicro.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nMessage-ID: \u003c20231218125334.37184-20-dbarboza@ventanamicro.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "cd3c22e92b6f7e8d93c53c076d928d0ad2283446",
      "old_mode": 33188,
      "old_path": "target/riscv/cpu.c",
      "new_id": "0ec0d89070969b923c1258cb70d5f2ad99d5c8d8",
      "new_mode": 33188,
      "new_path": "target/riscv/cpu.c"
    },
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      "old_path": "target/riscv/cpu_cfg.h",
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      "new_mode": 33188,
      "new_path": "target/riscv/cpu_cfg.h"
    },
    {
      "type": "modify",
      "old_id": "f2a955873793c5a3e9899cb23bcbc44ae8a5f596",
      "old_mode": 33188,
      "old_path": "target/riscv/tcg/tcg-cpu.c",
      "new_id": "e90d929ac10cc530faf4c8a6d52f27ce70fdce07",
      "new_mode": 33188,
      "new_path": "target/riscv/tcg/tcg-cpu.c"
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}