commit 47f7be394aa7baf7855fe78f56b8ba4c69bf75d9
author Jan Kiszka <jan.kiszka@web.de> Sat Apr 09 13:18:59 2011 +0200
committer Aurelien Jarno <aurelien@aurel32.net> Wed Apr 27 20:04:51 2011 +0200
tree 9633e60e984359013a156d84e3f6c3c9ac6a0cea
parent 661bfc80e876d32da8befe53ba0234d87fc0bcc2

ioapic: Do not set irr for masked edge IRQs

So far we set IRR for edge IRQs even if the pin is masked. If the guest
later on unmasks and switches the pin to level-triggered mode, irr will
remain set, causing an IRQ storm. The point is that setting IRR is not
correct in this case according to the spec, and avoiding this resolves
the issue.

Reported-and-tested-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

hw/ioapic.c

diff --git a/hw/ioapic.c b/hw/ioapic.c
index 569327d..6c26e82 100644
--- a/hw/ioapic.c
+++ b/hw/ioapic.c
@@ -160,8 +160,9 @@
                 s->irr &= ~mask;
             }
         } else {
-            /* edge triggered */
-            if (level) {
+            /* According to the 82093AA manual, we must ignore edge requests
+             * if the input pin is masked. */
+            if (level && !(entry & IOAPIC_LVT_MASKED)) {
                 s->irr |= mask;
                 ioapic_service(s);
             }