target/openrisc: Merge tlb allocation into CPUOpenRISCState
There is no reason to allocate this separately. This was probably
copied from target/mips which makes the same mistake.
While doing so, move tlb into the clear-on-reset range. While not
all of the TLB bits are guaranteed zero on reset, all of the valid
bits are cleared, and the rest of the bits are unspecified.
Therefore clearing the whole of the TLB is correct.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index c871d6b..96b7f58 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -301,6 +301,10 @@
uint32_t dflag; /* In delay slot (boolean) */
+#ifndef CONFIG_USER_ONLY
+ CPUOpenRISCTLBContext tlb;
+#endif
+
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
@@ -310,8 +314,6 @@
uint32_t cpucfgr; /* CPU configure register */
#ifndef CONFIG_USER_ONLY
- CPUOpenRISCTLBContext * tlb;
-
QEMUTimer *timer;
uint32_t ttmr; /* Timer tick mode register */
int is_counting;
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index 25351d5..2d0b55a 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -63,8 +63,8 @@
env->sr &= ~SR_TEE;
env->pmr &= ~PMR_DME;
env->pmr &= ~PMR_SME;
- env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
- env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
+ env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
+ env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
env->lock_addr = -1;
if (exception > 0 && exception < EXCP_NR) {
diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c
index b865738..dc97b38 100644
--- a/target/openrisc/interrupt_helper.c
+++ b/target/openrisc/interrupt_helper.c
@@ -36,18 +36,18 @@
#ifndef CONFIG_USER_ONLY
if (cpu->env.sr & SR_DME) {
- cpu->env.tlb->cpu_openrisc_map_address_data =
+ cpu->env.tlb.cpu_openrisc_map_address_data =
&cpu_openrisc_get_phys_data;
} else {
- cpu->env.tlb->cpu_openrisc_map_address_data =
+ cpu->env.tlb.cpu_openrisc_map_address_data =
&cpu_openrisc_get_phys_nommu;
}
if (cpu->env.sr & SR_IME) {
- cpu->env.tlb->cpu_openrisc_map_address_code =
+ cpu->env.tlb.cpu_openrisc_map_address_code =
&cpu_openrisc_get_phys_code;
} else {
- cpu->env.tlb->cpu_openrisc_map_address_code =
+ cpu->env.tlb.cpu_openrisc_map_address_code =
&cpu_openrisc_get_phys_nommu;
}
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c
index 0a793eb..c10d28b 100644
--- a/target/openrisc/machine.c
+++ b/target/openrisc/machine.c
@@ -30,18 +30,18 @@
/* Restore MMU handlers */
if (env->sr & SR_DME) {
- env->tlb->cpu_openrisc_map_address_data =
+ env->tlb.cpu_openrisc_map_address_data =
&cpu_openrisc_get_phys_data;
} else {
- env->tlb->cpu_openrisc_map_address_data =
+ env->tlb.cpu_openrisc_map_address_data =
&cpu_openrisc_get_phys_nommu;
}
if (env->sr & SR_IME) {
- env->tlb->cpu_openrisc_map_address_code =
+ env->tlb.cpu_openrisc_map_address_code =
&cpu_openrisc_get_phys_code;
} else {
- env->tlb->cpu_openrisc_map_address_code =
+ env->tlb.cpu_openrisc_map_address_code =
&cpu_openrisc_get_phys_nommu;
}
@@ -77,10 +77,6 @@
}
};
-#define VMSTATE_CPU_TLB(_f, _s) \
- VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_tlb, CPUOpenRISCTLBContext)
-
-
static int get_sr(QEMUFile *f, void *opaque, size_t size, VMStateField *field)
{
CPUOpenRISCState *env = opaque;
@@ -143,7 +139,8 @@
VMSTATE_UINT32(fpcsr, CPUOpenRISCState),
VMSTATE_UINT64(mac, CPUOpenRISCState),
- VMSTATE_CPU_TLB(tlb, CPUOpenRISCState),
+ VMSTATE_STRUCT(tlb, CPUOpenRISCState, 1,
+ vmstate_cpu_tlb, CPUOpenRISCTLBContext),
VMSTATE_TIMER_PTR(timer, CPUOpenRISCState),
VMSTATE_UINT32(ttmr, CPUOpenRISCState),
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index 2bd782f..5665bb7 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -46,19 +46,19 @@
int idx = vpn & ITLB_MASK;
int right = 0;
- if ((cpu->env.tlb->itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
+ if ((cpu->env.tlb.itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
return TLBRET_NOMATCH;
}
- if (!(cpu->env.tlb->itlb[0][idx].mr & 1)) {
+ if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) {
return TLBRET_INVALID;
}
if (cpu->env.sr & SR_SM) { /* supervisor mode */
- if (cpu->env.tlb->itlb[0][idx].tr & SXE) {
+ if (cpu->env.tlb.itlb[0][idx].tr & SXE) {
right |= PAGE_EXEC;
}
} else {
- if (cpu->env.tlb->itlb[0][idx].tr & UXE) {
+ if (cpu->env.tlb.itlb[0][idx].tr & UXE) {
right |= PAGE_EXEC;
}
}
@@ -67,7 +67,7 @@
return TLBRET_BADADDR;
}
- *physical = (cpu->env.tlb->itlb[0][idx].tr & TARGET_PAGE_MASK) |
+ *physical = (cpu->env.tlb.itlb[0][idx].tr & TARGET_PAGE_MASK) |
(address & (TARGET_PAGE_SIZE-1));
*prot = right;
return TLBRET_MATCH;
@@ -81,25 +81,25 @@
int idx = vpn & DTLB_MASK;
int right = 0;
- if ((cpu->env.tlb->dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
+ if ((cpu->env.tlb.dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
return TLBRET_NOMATCH;
}
- if (!(cpu->env.tlb->dtlb[0][idx].mr & 1)) {
+ if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) {
return TLBRET_INVALID;
}
if (cpu->env.sr & SR_SM) { /* supervisor mode */
- if (cpu->env.tlb->dtlb[0][idx].tr & SRE) {
+ if (cpu->env.tlb.dtlb[0][idx].tr & SRE) {
right |= PAGE_READ;
}
- if (cpu->env.tlb->dtlb[0][idx].tr & SWE) {
+ if (cpu->env.tlb.dtlb[0][idx].tr & SWE) {
right |= PAGE_WRITE;
}
} else {
- if (cpu->env.tlb->dtlb[0][idx].tr & URE) {
+ if (cpu->env.tlb.dtlb[0][idx].tr & URE) {
right |= PAGE_READ;
}
- if (cpu->env.tlb->dtlb[0][idx].tr & UWE) {
+ if (cpu->env.tlb.dtlb[0][idx].tr & UWE) {
right |= PAGE_WRITE;
}
}
@@ -111,7 +111,7 @@
return TLBRET_BADADDR;
}
- *physical = (cpu->env.tlb->dtlb[0][idx].tr & TARGET_PAGE_MASK) |
+ *physical = (cpu->env.tlb.dtlb[0][idx].tr & TARGET_PAGE_MASK) |
(address & (TARGET_PAGE_SIZE-1));
*prot = right;
return TLBRET_MATCH;
@@ -126,10 +126,10 @@
if (rw == MMU_INST_FETCH) { /* ITLB */
*physical = 0;
- ret = cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical,
+ ret = cpu->env.tlb.cpu_openrisc_map_address_code(cpu, physical,
prot, address, rw);
} else { /* DTLB */
- ret = cpu->env.tlb->cpu_openrisc_map_address_data(cpu, physical,
+ ret = cpu->env.tlb.cpu_openrisc_map_address_data(cpu, physical,
prot, address, rw);
}
@@ -247,9 +247,7 @@
void cpu_openrisc_mmu_init(OpenRISCCPU *cpu)
{
- cpu->env.tlb = g_malloc0(sizeof(CPUOpenRISCTLBContext));
-
- cpu->env.tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
- cpu->env.tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
+ cpu->env.tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
+ cpu->env.tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
}
#endif
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 2c959f6..ff315f6 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -61,18 +61,18 @@
}
cpu_set_sr(env, rb);
if (env->sr & SR_DME) {
- env->tlb->cpu_openrisc_map_address_data =
+ env->tlb.cpu_openrisc_map_address_data =
&cpu_openrisc_get_phys_data;
} else {
- env->tlb->cpu_openrisc_map_address_data =
+ env->tlb.cpu_openrisc_map_address_data =
&cpu_openrisc_get_phys_nommu;
}
if (env->sr & SR_IME) {
- env->tlb->cpu_openrisc_map_address_code =
+ env->tlb.cpu_openrisc_map_address_code =
&cpu_openrisc_get_phys_code;
} else {
- env->tlb->cpu_openrisc_map_address_code =
+ env->tlb.cpu_openrisc_map_address_code =
&cpu_openrisc_get_phys_nommu;
}
break;
@@ -101,14 +101,14 @@
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
if (!(rb & 1)) {
- tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
+ tlb_flush_page(cs, env->tlb.dtlb[0][idx].mr & TARGET_PAGE_MASK);
}
- env->tlb->dtlb[0][idx].mr = rb;
+ env->tlb.dtlb[0][idx].mr = rb;
break;
case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
idx = spr - TO_SPR(1, 640);
- env->tlb->dtlb[0][idx].tr = rb;
+ env->tlb.dtlb[0][idx].tr = rb;
break;
case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
@@ -120,14 +120,14 @@
case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
if (!(rb & 1)) {
- tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
+ tlb_flush_page(cs, env->tlb.itlb[0][idx].mr & TARGET_PAGE_MASK);
}
- env->tlb->itlb[0][idx].mr = rb;
+ env->tlb.itlb[0][idx].mr = rb;
break;
case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
idx = spr - TO_SPR(2, 640);
- env->tlb->itlb[0][idx].tr = rb;
+ env->tlb.itlb[0][idx].tr = rb;
break;
case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
@@ -259,11 +259,11 @@
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
- return env->tlb->dtlb[0][idx].mr;
+ return env->tlb.dtlb[0][idx].mr;
case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
idx = spr - TO_SPR(1, 640);
- return env->tlb->dtlb[0][idx].tr;
+ return env->tlb.dtlb[0][idx].tr;
case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
@@ -275,11 +275,11 @@
case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
- return env->tlb->itlb[0][idx].mr;
+ return env->tlb.itlb[0][idx].mr;
case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
idx = spr - TO_SPR(2, 640);
- return env->tlb->itlb[0][idx].tr;
+ return env->tlb.itlb[0][idx].tr;
case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
