tree e281ea7ff1ffd1ed9cc3165eb9430e35e45d0195
parent b902ff2946adcc72d65604321ae3ca2fb41ae644
author Weiwei Li <liweiwei@iscas.ac.cn> 1684834534 +0800
committer Alistair Francis <alistair.francis@wdc.com> 1686641253 +1000

target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info

Pass RISCVCPUConfig as disassemble_info.target_info to support disas
of conflict instructions related to specific extensions.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>